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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's generate PC                                        ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  PC, interface to IC.                                        ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/20 18:46:15  simons
// Break point bug fixed
//
// Revision 1.9  2001/11/18 09:58:28  lampret
// Fixed some l.trap typos.
//
// Revision 1.8  2001/11/18 08:36:28  lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_genpc(
        // Clock and reset
        clk, rst,
 
        // External i/f to IC
        icpu_adr_o, icpu_cyc_o, icpu_stb_o, icpu_sel_o, icpu_tag_o,
        icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i,
 
        // Internal i/f
        branch_op, except_type, except_prefix,
        branch_addrofs, lr_restor, flag, taken, except_start,
        binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
        genpc_freeze, flushpipe
);
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// External i/f to IC
//
output  [31:0]                   icpu_adr_o;
output                          icpu_cyc_o;
output                          icpu_stb_o;
output  [3:0]                    icpu_sel_o;
output  [3:0]                    icpu_tag_o;
input                           icpu_ack_i;
input                           icpu_rty_i;
input                           icpu_err_i;
input   [31:0]                   icpu_adr_i;
 
//
// Internal i/f
//
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
input   [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
input                                   except_prefix;
input   [31:2]                  branch_addrofs;
input   [31:0]                   lr_restor;
input                           flag;
output                          taken;
input                           except_start;
input   [31:2]                  binsn_addr;
input   [31:0]                   epcr;
input   [31:0]                   spr_dat_i;
input                           spr_pc_we;
input                           genpc_refetch;
input                           genpc_freeze;
input                           flushpipe;
 
//
// Internal wires and regs
//
reg     [31:2]                  pcreg;
reg     [31:0]                   pc;
reg                             taken;  /* Set to in case of jump or taken branch */
reg                             dslot;  /* set when fetching delay slot insn */
reg                             btarget; /* set when fetching branch target insns */
 
//
// Address of insn to be fecthed
//
assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
 
//
// Control access to IC subsystem
//
assign icpu_cyc_o = !genpc_freeze;
assign icpu_stb_o = icpu_cyc_o;
assign icpu_sel_o = 4'b1111;
assign icpu_tag_o = `OR1200_ITAG_NI;
 
//
// Async calculation of new PC value. This value is used for addressing the IC.
//
always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type
        or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin
        casex ({spr_pc_we, except_start, branch_op})    // synopsys parallel_case
                {2'b00, `OR1200_BRANCHOP_NOP}: begin
                        pc = {pcreg + 'd1, 2'b0};
                        taken = 1'b0;
                end
                {2'b00, `OR1200_BRANCHOP_J}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_J: pc <= branch_addrofs %h", $time, branch_addrofs);
// synopsys translate_on
`endif
                        pc = {branch_addrofs, 2'b0};
                        taken = 1'b1;
                end
                {2'b00, `OR1200_BRANCHOP_JR}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_JR: pc <= lr_restor %h", $time, lr_restor);
// synopsys translate_on
`endif
                        pc = lr_restor;
                        taken = 1'b1;
                end
                {2'b00, `OR1200_BRANCHOP_BAL}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_BAL: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
                        pc = {binsn_addr + branch_addrofs, 2'b0};
                        taken = 1'b1;
                end
                {2'b00, `OR1200_BRANCHOP_BF}:
                        if (flag) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
                                pc = {binsn_addr + branch_addrofs, 2'b0};
                                taken = 1'b1;
                        end
                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BF: not taken", $time);
// synopsys translate_on
`endif
                                pc = {pcreg + 'd1, 2'b0};
                                taken = 1'b0;
                        end
                {2'b00, `OR1200_BRANCHOP_BNF}:
                        if (flag) begin
                                pc = {pcreg + 'd1, 2'b0};
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BNF: not taken", $time);
// synopsys translate_on
`endif
                                taken = 1'b0;
                        end
                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BNF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
                                pc = {binsn_addr + branch_addrofs, 2'b0};
                                taken = 1'b1;
                        end
                {2'b00, `OR1200_BRANCHOP_RFE}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);
// synopsys translate_on
`endif
                        pc = epcr;
                        taken = 1'b1;
                end
                {2'b01, 3'bxxx}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("Starting exception: %h.", except_type);
// synopsys translate_on
`endif
                        pc = { {4{except_prefix}}, 16'h0000, except_type, 8'h00};
                        taken = 1'b1;
                end
                default: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("l.mtspr writing into PC: %h.", spr_dat_i);
// synopsys translate_on
`endif
                        pc = spr_dat_i;
                        taken = 1'b0;
                end
        endcase
end
 
//
// PC register
//
always @(posedge clk or posedge rst)
        if (rst)
                pcreg <= #1 30'd63;
        else if (spr_pc_we)
                pcreg <= #1 spr_dat_i[31:2];
        else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
                pcreg <= #1 pc[31:2];
 
//
// dslot
//
always @(posedge clk or posedge rst)
        if (rst)
                dslot <= #1 1'b0;
        else if (spr_pc_we)
                dslot <= #1 1'b0;
        else if (!icpu_rty_i)
                dslot <= #1 |branch_op;
 
//
// btarget
//
always @(posedge clk or posedge rst)
        if (rst)
                btarget <= #1 1'b0;
        else if (spr_pc_we)
                btarget <= #1 1'b0;
        else if (!icpu_rty_i)
                btarget <= #1 dslot;
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// OR1200's generate PC ////`
5			`//// ////`
6			`//// This file is part of the OpenRISC 1200 project ////`
7			`//// http://www.opencores.org/cores/or1k/ ////`
8			`//// ////`
9			`//// Description ////`
10			`//// PC, interface to IC. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - make it smaller and faster ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Damjan Lampret, lampret@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	589	lampret	`// Revision 1.2 2002/01/14 06:18:22 lampret`
49			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
50			`//`
51	562	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
52			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
53			`//`
54	504	lampret	`// Revision 1.10 2001/11/20 18:46:15 simons`
55			`// Break point bug fixed`
56			`//`
57			`// Revision 1.9 2001/11/18 09:58:28 lampret`
58			`// Fixed some l.trap typos.`
59			`//`
60			`// Revision 1.8 2001/11/18 08:36:28 lampret`
61			`// For GDB changed single stepping and disabled trap exception.`
62			`//`
63			`// Revision 1.7 2001/10/21 17:57:16 lampret`
64			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
65			`//`
66			`// Revision 1.6 2001/10/14 13:12:09 lampret`
67			`// MP3 version.`
68			`//`
69			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
70			`// no message`
71			`//`
72			`// Revision 1.1 2001/08/09 13:39:33 lampret`
73			`// Major clean-up.`
74			`//`
75			`//`
76
77			`// synopsys translate_off`
78			`include "timescale.v"
79			`// synopsys translate_on`
80			`include "or1200_defines.v"
81
82			`module or1200_genpc(`
83			`// Clock and reset`
84			`clk, rst,`
85
86			`// External i/f to IC`
87			`icpu_adr_o, icpu_cyc_o, icpu_stb_o, icpu_sel_o, icpu_tag_o,`
88			`icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i,`
89
90			`// Internal i/f`
91	589	lampret	`branch_op, except_type, except_prefix,`
92	504	lampret	`branch_addrofs, lr_restor, flag, taken, except_start,`
93	562	lampret	`binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,`
94			`genpc_freeze, flushpipe`
95	504	lampret	`);`
96
97			`//`
98			`// I/O`
99			`//`
100
101			`//`
102			`// Clock and reset`
103			`//`
104			`input clk;`
105			`input rst;`
106
107			`//`
108			`// External i/f to IC`
109			`//`
110			`output [31:0] icpu_adr_o;`
111			`output icpu_cyc_o;`
112			`output icpu_stb_o;`
113			`output [3:0] icpu_sel_o;`
114			`output [3:0] icpu_tag_o;`
115			`input icpu_ack_i;`
116			`input icpu_rty_i;`
117			`input icpu_err_i;`
118			`input [31:0] icpu_adr_i;`
119
120			`//`
121			`// Internal i/f`
122			`//`
123			input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
124			input [`OR1200_EXCEPT_WIDTH-1:0] except_type;
125	589	lampret	`input except_prefix;`
126	504	lampret	`input [31:2] branch_addrofs;`
127			`input [31:0] lr_restor;`
128			`input flag;`
129			`output taken;`
130			`input except_start;`
131			`input [31:2] binsn_addr;`
132			`input [31:0] epcr;`
133			`input [31:0] spr_dat_i;`
134			`input spr_pc_we;`
135			`input genpc_refetch;`
136	562	lampret	`input genpc_freeze;`
137			`input flushpipe;`
138	504	lampret
139			`//`
140			`// Internal wires and regs`
141			`//`
142			`reg [31:2] pcreg;`
143			`reg [31:0] pc;`
144			`reg taken; /* Set to in case of jump or taken branch */`
145			`reg dslot; /* set when fetching delay slot insn */`
146			`reg btarget; /* set when fetching branch target insns */`
147
148			`//`
149			`// Address of insn to be fecthed`
150			`//`
151	562	lampret	`assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i \| genpc_refetch) ? icpu_adr_i : pc;`
152	504	lampret
153			`//`
154			`// Control access to IC subsystem`
155			`//`
156	562	lampret	`assign icpu_cyc_o = !genpc_freeze;`
157			`assign icpu_stb_o = icpu_cyc_o;`
158	504	lampret	`assign icpu_sel_o = 4'b1111;`
159			assign icpu_tag_o = `OR1200_ITAG_NI;
160
161			`//`
162			`// Async calculation of new PC value. This value is used for addressing the IC.`
163			`//`
164			`always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type`
165	589	lampret	`or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin`
166	504	lampret	`casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case`
167			{2'b00, `OR1200_BRANCHOP_NOP}: begin
168			`pc = {pcreg + 'd1, 2'b0};`
169			`taken = 1'b0;`
170			`end`
171			{2'b00, `OR1200_BRANCHOP_J}: begin
172			`ifdef OR1200_VERBOSE
173			`// synopsys translate_off`
174			`$display("%t: BRANCHOP_J: pc <= branch_addrofs %h", $time, branch_addrofs);`
175			`// synopsys translate_on`
176			`endif
177			`pc = {branch_addrofs, 2'b0};`
178			`taken = 1'b1;`
179			`end`
180			{2'b00, `OR1200_BRANCHOP_JR}: begin
181			`ifdef OR1200_VERBOSE
182			`// synopsys translate_off`
183			`$display("%t: BRANCHOP_JR: pc <= lr_restor %h", $time, lr_restor);`
184			`// synopsys translate_on`
185			`endif
186			`pc = lr_restor;`
187			`taken = 1'b1;`
188			`end`
189			{2'b00, `OR1200_BRANCHOP_BAL}: begin
190			`ifdef OR1200_VERBOSE
191			`// synopsys translate_off`
192			`$display("%t: BRANCHOP_BAL: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);`
193			`// synopsys translate_on`
194			`endif
195			`pc = {binsn_addr + branch_addrofs, 2'b0};`
196			`taken = 1'b1;`
197			`end`
198			{2'b00, `OR1200_BRANCHOP_BF}:
199			`if (flag) begin`
200			`ifdef OR1200_VERBOSE
201			`// synopsys translate_off`
202			`$display("%t: BRANCHOP_BF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);`
203			`// synopsys translate_on`
204			`endif
205			`pc = {binsn_addr + branch_addrofs, 2'b0};`
206			`taken = 1'b1;`
207			`end`
208			`else begin`
209			`ifdef OR1200_VERBOSE
210			`// synopsys translate_off`
211			`$display("%t: BRANCHOP_BF: not taken", $time);`
212			`// synopsys translate_on`
213			`endif
214			`pc = {pcreg + 'd1, 2'b0};`
215			`taken = 1'b0;`
216			`end`
217			{2'b00, `OR1200_BRANCHOP_BNF}:
218			`if (flag) begin`
219			`pc = {pcreg + 'd1, 2'b0};`
220			`ifdef OR1200_VERBOSE
221			`// synopsys translate_off`
222			`$display("%t: BRANCHOP_BNF: not taken", $time);`
223			`// synopsys translate_on`
224			`endif
225			`taken = 1'b0;`
226			`end`
227			`else begin`
228			`ifdef OR1200_VERBOSE
229			`// synopsys translate_off`
230			`$display("%t: BRANCHOP_BNF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);`
231			`// synopsys translate_on`
232			`endif
233			`pc = {binsn_addr + branch_addrofs, 2'b0};`
234			`taken = 1'b1;`
235			`end`
236			{2'b00, `OR1200_BRANCHOP_RFE}: begin
237			`ifdef OR1200_VERBOSE
238			`// synopsys translate_off`
239			`$display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);`
240			`// synopsys translate_on`
241			`endif
242			`pc = epcr;`
243			`taken = 1'b1;`
244			`end`
245			`{2'b01, 3'bxxx}: begin`
246			`ifdef OR1200_VERBOSE
247			`// synopsys translate_off`
248			`$display("Starting exception: %h.", except_type);`
249			`// synopsys translate_on`
250			`endif
251	589	lampret	`pc = { {4{except_prefix}}, 16'h0000, except_type, 8'h00};`
252	504	lampret	`taken = 1'b1;`
253			`end`
254			`default: begin`
255			`ifdef OR1200_VERBOSE
256			`// synopsys translate_off`
257			`$display("l.mtspr writing into PC: %h.", spr_dat_i);`
258			`// synopsys translate_on`
259			`endif
260			`pc = spr_dat_i;`
261			`taken = 1'b0;`
262			`end`
263			`endcase`
264			`end`
265
266			`//`
267			`// PC register`
268			`//`
269			`always @(posedge clk or posedge rst)`
270			`if (rst)`
271			`pcreg <= #1 30'd63;`
272			`else if (spr_pc_we)`
273			`pcreg <= #1 spr_dat_i[31:2];`
274	562	lampret	`else if (except_start \| !genpc_freeze & !icpu_rty_i & !genpc_refetch)`
275	504	lampret	`pcreg <= #1 pc[31:2];`
276
277			`//`
278			`// dslot`
279			`//`
280			`always @(posedge clk or posedge rst)`
281			`if (rst)`
282			`dslot <= #1 1'b0;`
283			`else if (spr_pc_we)`
284			`dslot <= #1 1'b0;`
285			`else if (!icpu_rty_i)`
286			`dslot <= #1 \|branch_op;`
287
288			`//`
289			`// btarget`
290			`//`
291			`always @(posedge clk or posedge rst)`
292			`if (rst)`
293			`btarget <= #1 1'b0;`
294			`else if (spr_pc_we)`
295			`btarget <= #1 1'b0;`
296			`else if (!icpu_rty_i)`
297			`btarget <= #1 dslot;`
298
299			`endmodule`

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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_genpc.v] - Blame information for rev 589