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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_iwb_biu.v] - Blame information for rev 1765

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's WISHBONE BIU                                       ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Implements WISHBONE interface                               ////
////                                                              ////
////  To Do:                                                      ////
////   - if biu_cyc/stb are deasserted and wb_ack_i is asserted   ////
////   and this happens even before aborted_r is asssrted,        ////
////   wb_ack_i will be delivered even though transfer is         ////
////   internally considered already aborted. However most        ////
////   wb_ack_i are externally registered and delayed. Normally   ////
////   this shouldn't cause any problems.                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6.4.1  2003/07/08 15:36:37  lampret
// Added embedded memory QMEM.
//
// Revision 1.6  2003/04/07 20:57:46  lampret
// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs.
//
// Revision 1.5  2002/12/08 08:57:56  lampret
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
//
// Revision 1.4  2002/09/16 03:09:16  lampret
// Fixed a combinational loop.
//
// Revision 1.3  2002/08/12 05:31:37  lampret
// Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers.
//
// Revision 1.2  2002/07/14 22:17:17  lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.12  2001/11/22 13:42:51  lampret
// Added wb_cyc_o assignment after it was removed by accident.
//
// Revision 1.11  2001/11/20 21:28:10  lampret
// Added optional sampling of inputs.
//
// Revision 1.10  2001/11/18 11:32:00  lampret
// OR1200_REGISTERED_OUTPUTS can now be enabled.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/14 13:12:10  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.3  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/22 03:31:54  lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1  2001/07/20 00:46:23  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_iwb_biu(
        // RISC clock, reset and clock control
        clk, rst, clmode,
 
        // WISHBONE interface
        wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,
        wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_dat_o,
`ifdef OR1200_WB_CAB
        wb_cab_o,
`endif
`ifdef OR1200_WB_B3
        wb_cti_o, wb_bte_o,
`endif
 
        // Internal RISC bus
        biu_dat_i, biu_adr_i, biu_cyc_i, biu_stb_i, biu_we_i, biu_sel_i, biu_cab_i,
        biu_dat_o, biu_ack_o, biu_err_o
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
 
//
// RISC clock, reset and clock control
//
input                   clk;            // RISC clock
input                   rst;            // RISC reset
input   [1:0]            clmode;         // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
 
//
// WISHBONE interface
//
input                   wb_clk_i;       // clock input
input                   wb_rst_i;       // reset input
input                   wb_ack_i;       // normal termination
input                   wb_err_i;       // termination w/ error
input                   wb_rty_i;       // termination w/ retry
input   [dw-1:0] wb_dat_i;       // input data bus
output                  wb_cyc_o;       // cycle valid output
output  [aw-1:0] wb_adr_o;       // address bus outputs
output                  wb_stb_o;       // strobe output
output                  wb_we_o;        // indicates write transfer
output  [3:0]            wb_sel_o;       // byte select outputs
output  [dw-1:0] wb_dat_o;       // output data bus
`ifdef OR1200_WB_CAB
output                  wb_cab_o;       // consecutive address burst
`endif
`ifdef OR1200_WB_B3
output  [2:0]            wb_cti_o;       // cycle type identifier
output  [1:0]            wb_bte_o;       // burst type extension
`endif
 
//
// Internal RISC interface
//
input   [dw-1:0] biu_dat_i;      // input data bus
input   [aw-1:0] biu_adr_i;      // address bus
input                   biu_cyc_i;      // WB cycle
input                   biu_stb_i;      // WB strobe
input                   biu_we_i;       // WB write enable
input                   biu_cab_i;      // CAB input
input   [3:0]            biu_sel_i;      // byte selects
output  [31:0]           biu_dat_o;      // output data bus
output                  biu_ack_o;      // ack output
output                  biu_err_o;      // err output
 
//
// Registers
//
reg     [1:0]            valid_div;      // Used for synchronization
`ifdef OR1200_REGISTERED_OUTPUTS
reg     [aw-1:0] wb_adr_o;       // address bus outputs
reg                     wb_cyc_o;       // cycle output
reg                     wb_stb_o;       // strobe output
reg                     wb_we_o;        // indicates write transfer
reg     [3:0]            wb_sel_o;       // byte select outputs
`ifdef OR1200_WB_CAB
reg                     wb_cab_o;       // CAB output
`endif
`ifdef OR1200_WB_B3
reg     [1:0]            burst_len;      // burst counter
reg     [2:0]            wb_cti_o;       // cycle type identifier
`endif
reg     [dw-1:0] wb_dat_o;       // output data bus
`endif
`ifdef OR1200_REGISTERED_INPUTS
reg                     long_ack_o;     // normal termination
reg                     long_err_o;     // error termination
reg     [dw-1:0] biu_dat_o;      // output data bus
`else
wire                    long_ack_o;     // normal termination
wire                    long_err_o;     // error termination
`endif
wire                    aborted;        // Graceful abort
reg                     aborted_r;      // Graceful abort
wire                    retry;          // Retry
`ifdef OR1200_WB_RETRY
reg     [`OR1200_WB_RETRY-1:0] retry_cntr;       // Retry counter
`endif
reg                     previous_complete;
wire                    same_addr;
wire                    repeated_access;
reg                     repeated_access_ack;
reg     [dw-1:0] wb_dat_r;       // saved previous data read
 
//
// WISHBONE I/F <-> Internal RISC I/F conversion
//
 
//
// Address bus
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_adr_o <= #1 {aw{1'b0}};
        else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted & ~(wb_stb_o & ~wb_ack_i) | biu_cab_i)
                wb_adr_o <= #1 biu_adr_i;
`else
assign wb_adr_o = biu_adr_i;
`endif
 
//
// Same access as previous one, store previous read data
//
assign same_addr = wb_adr_o == biu_adr_i;
assign repeated_access = same_addr & previous_complete;
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_dat_r <= #1 32'h0000_0000;
        else if (wb_ack_i)
                wb_dat_r <= #1 wb_dat_i;
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                repeated_access_ack <= #1 1'b0;
        else if (repeated_access & biu_cyc_i & biu_stb_i)
                repeated_access_ack <= #1 1'b1;
        else
                repeated_access_ack <= #1 1'b0;
 
//
// Previous access completed
//
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                previous_complete <= #1 1'b0;
        else if (wb_ack_i & biu_cyc_i & biu_stb_i)
                previous_complete <= #1 1'b1;
        else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted & ~(wb_stb_o & ~wb_ack_i))
                previous_complete <= #1 1'b0;
 
//
// Input data bus
//
`ifdef OR1200_REGISTERED_INPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                biu_dat_o <= #1 32'h0000_0000;
        else if (wb_ack_i)
                biu_dat_o <= #1 wb_dat_i;
`else
assign biu_dat_o = repeated_access_ack ? wb_dat_r : wb_dat_i;
`endif
 
//
// Output data bus
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_dat_o <= #1 {dw{1'b0}};
        else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted)
                wb_dat_o <= #1 biu_dat_i;
`else
assign wb_dat_o = biu_dat_i;
`endif
 
//
// Valid_div counts RISC clock cycles by modulo 4
// and is used to synchronize external WB i/f to
// RISC clock
//
always @(posedge clk or posedge rst)
        if (rst)
                valid_div <= #1 2'b0;
        else
                valid_div <= #1 valid_div + 1'd1;
 
//
// biu_ack_o is one RISC clock cycle long long_ack_o.
// long_ack_o is one, two or four RISC clock cycles long because
// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.
//
assign biu_ack_o = (repeated_access_ack | long_ack_o) & ~aborted_r
`ifdef OR1200_CLKDIV_2_SUPPORTED
                & (valid_div[0] | ~clmode[0])
`ifdef OR1200_CLKDIV_4_SUPPORTED
                & (valid_div[1] | ~clmode[1])
`endif
`endif
                ;
 
//
// Acknowledgment of the data to the RISC
//
// long_ack_o
//
`ifdef OR1200_REGISTERED_INPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                long_ack_o <= #1 1'b0;
        else
                long_ack_o <= #1 wb_ack_i & ~aborted;
`else
assign long_ack_o = wb_ack_i;
`endif
 
//
// biu_err_o is one RISC clock cycle long long_err_o.
// long_err_o is one, two or four RISC clock cycles long because
// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.
//
assign biu_err_o = long_err_o
`ifdef OR1200_CLKDIV_2_SUPPORTED
                & (valid_div[0] | ~clmode[0])
`ifdef OR1200_CLKDIV_4_SUPPORTED
                & (valid_div[1] | ~clmode[1])
`endif
`endif
                ;
 
//
// Error termination
//
// long_err_o
//
`ifdef OR1200_REGISTERED_INPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                long_err_o <= #1 1'b0;
        else
                long_err_o <= #1 wb_err_i & ~aborted;
`else
assign long_err_o = wb_err_i & ~aborted_r;
`endif
 
//
// Retry counter
//
// Assert 'retry' when 'wb_rty_i' is sampled high and keep it high
// until retry counter doesn't expire
// 
`ifdef OR1200_WB_RETRY
assign retry = wb_rty_i | (|retry_cntr);
`else
assign retry = 1'b0;
`endif
`ifdef OR1200_WB_RETRY
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                retry_cntr <= #1 1'b0;
        else if (wb_rty_i)
                retry_cntr <= #1 {`OR1200_WB_RETRY{1'b1}};
        else if (retry_cntr)
                retry_cntr <= #1 retry_cntr - 7'd1;
`endif
 
//
// Graceful completion of aborted transfers
//
// Assert 'aborted' when 1) current transfer is in progress (wb_stb_o; which
// we know is only asserted together with wb_cyc_o) 2) and in next WB clock cycle
// wb_stb_o would be deasserted (biu_cyc_i and biu_stb_i are low) 3) and
// there is no termination of current transfer in this WB clock cycle (wb_ack_i
// and wb_err_i are low).
// 'aborted_r' is registered 'aborted' and extended until this "aborted" transfer
// is properly terminated with wb_ack_i/wb_err_i.
// 
assign aborted = wb_stb_o & ~(biu_cyc_i & biu_stb_i) & ~(wb_ack_i | wb_err_i);
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                aborted_r <= #1 1'b0;
        else if (wb_ack_i | wb_err_i)
                aborted_r <= #1 1'b0;
        else if (aborted)
                aborted_r <= #1 1'b1;
 
//
// WB cyc_o
//
// Either 1) normal transfer initiated by biu_cyc_i (and biu_cab_i if
// bursts are enabled) and possibly suspended by 'retry'
// or 2) extended "aborted" transfer
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_cyc_o <= #1 1'b0;
        else
`ifdef OR1200_NO_BURSTS
                wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry & ~repeated_access | aborted & ~wb_ack_i;
`else
                wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry & ~repeated_access | biu_cab_i | aborted & ~wb_ack_i;
`endif
`else
`ifdef OR1200_NO_BURSTS
assign wb_cyc_o = biu_cyc_i & ~retry;
`else
assign wb_cyc_o = biu_cyc_i | biu_cab_i & ~retry;
`endif
`endif
 
//
// WB stb_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_stb_o <= #1 1'b0;
        else
                wb_stb_o <= #1 (biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~retry & ~repeated_access | aborted & ~wb_ack_i;
`else
assign wb_stb_o = biu_cyc_i & biu_stb_i;
`endif
 
//
// WB we_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_we_o <= #1 1'b0;
        else
                wb_we_o <= #1 biu_cyc_i & biu_stb_i & biu_we_i | aborted & wb_we_o;
`else
assign wb_we_o = biu_cyc_i & biu_stb_i & biu_we_i;
`endif
 
//
// WB sel_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_sel_o <= #1 4'b0000;
        else
                wb_sel_o <= #1 biu_sel_i;
`else
assign wb_sel_o = biu_sel_i;
`endif
 
`ifdef OR1200_WB_CAB
//
// WB cab_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_cab_o <= #1 1'b0;
        else
                wb_cab_o <= #1 biu_cab_i;
`else
assign wb_cab_o = biu_cab_i;
`endif
`endif
 
`ifdef OR1200_WB_B3
//
// Count burst beats
//
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                burst_len <= #1 2'b00;
        else if (biu_cab_i && burst_len && wb_ack_i)
                burst_len <= #1 burst_len - 1'b1;
        else if (~biu_cab_i)
                burst_len <= #1 2'b11;
 
//
// WB cti_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_cti_o <= #1 3'b000;  // classic cycle
`ifdef OR1200_NO_BURSTS
        else
                wb_cti_o <= #1 3'b111;  // end-of-burst
`else
        else if (biu_cab_i && burst_len[1])
                wb_cti_o <= #1 3'b010;  // incrementing burst cycle
        else if (biu_cab_i && wb_ack_i)
                wb_cti_o <= #1 3'b111;  // end-of-burst
`endif  // OR1200_NO_BURSTS
`else
Unsupported !!!;
`endif
 
//
// WB bte_o
//
assign wb_bte_o = 2'b01;        // 4-beat wrap burst
 
`endif  // OR1200_WB_B3
 
endmodule

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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_iwb_biu.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	1211	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's WISHBONE BIU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Implements WISHBONE interface ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - if biu_cyc/stb are deasserted and wb_ack_i is asserted ////`
13			`//// and this happens even before aborted_r is asssrted, ////`
14			`//// wb_ack_i will be delivered even though transfer is ////`
15			`//// internally considered already aborted. However most ////`
16			`//// wb_ack_i are externally registered and delayed. Normally ////`
17			`//// this shouldn't cause any problems. ////`
18			`//// ////`
19			`//// Author(s): ////`
20			`//// - Damjan Lampret, lampret@opencores.org ////`
21			`//// ////`
22			`//////////////////////////////////////////////////////////////////////`
23			`//// ////`
24			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
25			`//// ////`
26			`//// This source file may be used and distributed without ////`
27			`//// restriction provided that this copyright statement is not ////`
28			`//// removed from the file and that any derivative work contains ////`
29			`//// the original copyright notice and the associated disclaimer. ////`
30			`//// ////`
31			`//// This source file is free software; you can redistribute it ////`
32			`//// and/or modify it under the terms of the GNU Lesser General ////`
33			`//// Public License as published by the Free Software Foundation; ////`
34			`//// either version 2.1 of the License, or (at your option) any ////`
35			`//// later version. ////`
36			`//// ////`
37			`//// This source is distributed in the hope that it will be ////`
38			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
39			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
40			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
41			`//// details. ////`
42			`//// ////`
43			`//// You should have received a copy of the GNU Lesser General ////`
44			`//// Public License along with this source; if not, download it ////`
45			`//// from http://www.opencores.org/lgpl.shtml ////`
46			`//// ////`
47			`//////////////////////////////////////////////////////////////////////`
48			`//`
49			`// CVS Revision History`
50			`//`
51			`// $Log: not supported by cvs2svn $`
52			`// Revision 1.6.4.1 2003/07/08 15:36:37 lampret`
53			`// Added embedded memory QMEM.`
54			`//`
55			`// Revision 1.6 2003/04/07 20:57:46 lampret`
56			`// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs.`
57			`//`
58			`// Revision 1.5 2002/12/08 08:57:56 lampret`
59			`// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.`
60			`//`
61			`// Revision 1.4 2002/09/16 03:09:16 lampret`
62			`// Fixed a combinational loop.`
63			`//`
64			`// Revision 1.3 2002/08/12 05:31:37 lampret`
65			`// Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers.`
66			`//`
67			`// Revision 1.2 2002/07/14 22:17:17 lampret`
68			`// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.`
69			`//`
70			`// Revision 1.1 2002/01/03 08:16:15 lampret`
71			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
72			`//`
73			`// Revision 1.12 2001/11/22 13:42:51 lampret`
74			`// Added wb_cyc_o assignment after it was removed by accident.`
75			`//`
76			`// Revision 1.11 2001/11/20 21:28:10 lampret`
77			`// Added optional sampling of inputs.`
78			`//`
79			`// Revision 1.10 2001/11/18 11:32:00 lampret`
80			`// OR1200_REGISTERED_OUTPUTS can now be enabled.`
81			`//`
82			`// Revision 1.9 2001/10/21 17:57:16 lampret`
83			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
84			`//`
85			`// Revision 1.8 2001/10/14 13:12:10 lampret`
86			`// MP3 version.`
87			`//`
88			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
89			`// no message`
90			`//`
91			`// Revision 1.3 2001/08/09 13:39:33 lampret`
92			`// Major clean-up.`
93			`//`
94			`// Revision 1.2 2001/07/22 03:31:54 lampret`
95			`// Fixed RAM's oen bug. Cache bypass under development.`
96			`//`
97			`// Revision 1.1 2001/07/20 00:46:23 lampret`
98			`// Development version of RTL. Libraries are missing.`
99			`//`
100			`//`
101
102			`// synopsys translate_off`
103			`include "timescale.v"
104			`// synopsys translate_on`
105			`include "or1200_defines.v"
106
107			`module or1200_iwb_biu(`
108			`// RISC clock, reset and clock control`
109			`clk, rst, clmode,`
110
111			`// WISHBONE interface`
112			`wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,`
113			`wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_dat_o,`
114			`ifdef OR1200_WB_CAB
115			`wb_cab_o,`
116			`endif
117			`ifdef OR1200_WB_B3
118			`wb_cti_o, wb_bte_o,`
119			`endif
120
121			`// Internal RISC bus`
122			`biu_dat_i, biu_adr_i, biu_cyc_i, biu_stb_i, biu_we_i, biu_sel_i, biu_cab_i,`
123			`biu_dat_o, biu_ack_o, biu_err_o`
124			`);`
125
126			parameter dw = `OR1200_OPERAND_WIDTH;
127			parameter aw = `OR1200_OPERAND_WIDTH;
128
129			`//`
130			`// RISC clock, reset and clock control`
131			`//`
132			`input clk; // RISC clock`
133			`input rst; // RISC reset`
134			`input [1:0] clmode; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4`
135
136			`//`
137			`// WISHBONE interface`
138			`//`
139			`input wb_clk_i; // clock input`
140			`input wb_rst_i; // reset input`
141			`input wb_ack_i; // normal termination`
142			`input wb_err_i; // termination w/ error`
143			`input wb_rty_i; // termination w/ retry`
144			`input [dw-1:0] wb_dat_i; // input data bus`
145			`output wb_cyc_o; // cycle valid output`
146			`output [aw-1:0] wb_adr_o; // address bus outputs`
147			`output wb_stb_o; // strobe output`
148			`output wb_we_o; // indicates write transfer`
149			`output [3:0] wb_sel_o; // byte select outputs`
150			`output [dw-1:0] wb_dat_o; // output data bus`
151			`ifdef OR1200_WB_CAB
152			`output wb_cab_o; // consecutive address burst`
153			`endif
154			`ifdef OR1200_WB_B3
155			`output [2:0] wb_cti_o; // cycle type identifier`
156			`output [1:0] wb_bte_o; // burst type extension`
157			`endif
158
159			`//`
160			`// Internal RISC interface`
161			`//`
162			`input [dw-1:0] biu_dat_i; // input data bus`
163			`input [aw-1:0] biu_adr_i; // address bus`
164			`input biu_cyc_i; // WB cycle`
165			`input biu_stb_i; // WB strobe`
166			`input biu_we_i; // WB write enable`
167			`input biu_cab_i; // CAB input`
168			`input [3:0] biu_sel_i; // byte selects`
169			`output [31:0] biu_dat_o; // output data bus`
170			`output biu_ack_o; // ack output`
171			`output biu_err_o; // err output`
172
173			`//`
174			`// Registers`
175			`//`
176			`reg [1:0] valid_div; // Used for synchronization`
177			`ifdef OR1200_REGISTERED_OUTPUTS
178			`reg [aw-1:0] wb_adr_o; // address bus outputs`
179			`reg wb_cyc_o; // cycle output`
180			`reg wb_stb_o; // strobe output`
181			`reg wb_we_o; // indicates write transfer`
182			`reg [3:0] wb_sel_o; // byte select outputs`
183			`ifdef OR1200_WB_CAB
184			`reg wb_cab_o; // CAB output`
185			`endif
186			`ifdef OR1200_WB_B3
187			`reg [1:0] burst_len; // burst counter`
188			`reg [2:0] wb_cti_o; // cycle type identifier`
189			`endif
190			`reg [dw-1:0] wb_dat_o; // output data bus`
191			`endif
192			`ifdef OR1200_REGISTERED_INPUTS
193			`reg long_ack_o; // normal termination`
194			`reg long_err_o; // error termination`
195			`reg [dw-1:0] biu_dat_o; // output data bus`
196			`else
197			`wire long_ack_o; // normal termination`
198			`wire long_err_o; // error termination`
199			`endif
200			`wire aborted; // Graceful abort`
201			`reg aborted_r; // Graceful abort`
202			`wire retry; // Retry`
203			`ifdef OR1200_WB_RETRY
204			reg [`OR1200_WB_RETRY-1:0] retry_cntr; // Retry counter
205			`endif
206			`reg previous_complete;`
207			`wire same_addr;`
208			`wire repeated_access;`
209			`reg repeated_access_ack;`
210			`reg [dw-1:0] wb_dat_r; // saved previous data read`
211
212			`//`
213			`// WISHBONE I/F <-> Internal RISC I/F conversion`
214			`//`
215
216			`//`
217			`// Address bus`
218			`//`
219			`ifdef OR1200_REGISTERED_OUTPUTS
220			`always @(posedge wb_clk_i or posedge wb_rst_i)`
221			`if (wb_rst_i)`
222			`wb_adr_o <= #1 {aw{1'b0}};`
223			`else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted & ~(wb_stb_o & ~wb_ack_i) \| biu_cab_i)`
224			`wb_adr_o <= #1 biu_adr_i;`
225			`else
226			`assign wb_adr_o = biu_adr_i;`
227			`endif
228
229			`//`
230			`// Same access as previous one, store previous read data`
231			`//`
232			`assign same_addr = wb_adr_o == biu_adr_i;`
233			`assign repeated_access = same_addr & previous_complete;`
234			`always @(posedge wb_clk_i or posedge wb_rst_i)`
235			`if (wb_rst_i)`
236			`wb_dat_r <= #1 32'h0000_0000;`
237			`else if (wb_ack_i)`
238			`wb_dat_r <= #1 wb_dat_i;`
239			`always @(posedge wb_clk_i or posedge wb_rst_i)`
240			`if (wb_rst_i)`
241			`repeated_access_ack <= #1 1'b0;`
242			`else if (repeated_access & biu_cyc_i & biu_stb_i)`
243			`repeated_access_ack <= #1 1'b1;`
244			`else`
245			`repeated_access_ack <= #1 1'b0;`
246
247			`//`
248			`// Previous access completed`
249			`//`
250			`always @(posedge wb_clk_i or posedge wb_rst_i)`
251			`if (wb_rst_i)`
252			`previous_complete <= #1 1'b0;`
253			`else if (wb_ack_i & biu_cyc_i & biu_stb_i)`
254			`previous_complete <= #1 1'b1;`
255			`else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted & ~(wb_stb_o & ~wb_ack_i))`
256			`previous_complete <= #1 1'b0;`
257
258			`//`
259			`// Input data bus`
260			`//`
261			`ifdef OR1200_REGISTERED_INPUTS
262			`always @(posedge wb_clk_i or posedge wb_rst_i)`
263			`if (wb_rst_i)`
264			`biu_dat_o <= #1 32'h0000_0000;`
265			`else if (wb_ack_i)`
266			`biu_dat_o <= #1 wb_dat_i;`
267			`else
268			`assign biu_dat_o = repeated_access_ack ? wb_dat_r : wb_dat_i;`
269			`endif
270
271			`//`
272			`// Output data bus`
273			`//`
274			`ifdef OR1200_REGISTERED_OUTPUTS
275			`always @(posedge wb_clk_i or posedge wb_rst_i)`
276			`if (wb_rst_i)`
277			`wb_dat_o <= #1 {dw{1'b0}};`
278			`else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted)`
279			`wb_dat_o <= #1 biu_dat_i;`
280			`else
281			`assign wb_dat_o = biu_dat_i;`
282			`endif
283
284			`//`
285			`// Valid_div counts RISC clock cycles by modulo 4`
286			`// and is used to synchronize external WB i/f to`
287			`// RISC clock`
288			`//`
289			`always @(posedge clk or posedge rst)`
290			`if (rst)`
291			`valid_div <= #1 2'b0;`
292			`else`
293			`valid_div <= #1 valid_div + 1'd1;`
294
295			`//`
296			`// biu_ack_o is one RISC clock cycle long long_ack_o.`
297			`// long_ack_o is one, two or four RISC clock cycles long because`
298			`// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.`
299			`//`
300			`assign biu_ack_o = (repeated_access_ack \| long_ack_o) & ~aborted_r`
301			`ifdef OR1200_CLKDIV_2_SUPPORTED
302			`& (valid_div[0] \| ~clmode[0])`
303			`ifdef OR1200_CLKDIV_4_SUPPORTED
304			`& (valid_div[1] \| ~clmode[1])`
305			`endif
306			`endif
307			`;`
308
309			`//`
310			`// Acknowledgment of the data to the RISC`
311			`//`
312			`// long_ack_o`
313			`//`
314			`ifdef OR1200_REGISTERED_INPUTS
315			`always @(posedge wb_clk_i or posedge wb_rst_i)`
316			`if (wb_rst_i)`
317			`long_ack_o <= #1 1'b0;`
318			`else`
319			`long_ack_o <= #1 wb_ack_i & ~aborted;`
320			`else
321			`assign long_ack_o = wb_ack_i;`
322			`endif
323
324			`//`
325			`// biu_err_o is one RISC clock cycle long long_err_o.`
326			`// long_err_o is one, two or four RISC clock cycles long because`
327			`// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.`
328			`//`
329			`assign biu_err_o = long_err_o`
330			`ifdef OR1200_CLKDIV_2_SUPPORTED
331			`& (valid_div[0] \| ~clmode[0])`
332			`ifdef OR1200_CLKDIV_4_SUPPORTED
333			`& (valid_div[1] \| ~clmode[1])`
334			`endif
335			`endif
336			`;`
337
338			`//`
339			`// Error termination`
340			`//`
341			`// long_err_o`
342			`//`
343			`ifdef OR1200_REGISTERED_INPUTS
344			`always @(posedge wb_clk_i or posedge wb_rst_i)`
345			`if (wb_rst_i)`
346			`long_err_o <= #1 1'b0;`
347			`else`
348			`long_err_o <= #1 wb_err_i & ~aborted;`
349			`else
350			`assign long_err_o = wb_err_i & ~aborted_r;`
351			`endif
352
353			`//`
354			`// Retry counter`
355			`//`
356			`// Assert 'retry' when 'wb_rty_i' is sampled high and keep it high`
357			`// until retry counter doesn't expire`
358			`//`
359			`ifdef OR1200_WB_RETRY
360			`assign retry = wb_rty_i \| (\|retry_cntr);`
361			`else
362			`assign retry = 1'b0;`
363			`endif
364			`ifdef OR1200_WB_RETRY
365			`always @(posedge wb_clk_i or posedge wb_rst_i)`
366			`if (wb_rst_i)`
367			`retry_cntr <= #1 1'b0;`
368			`else if (wb_rty_i)`
369			retry_cntr <= #1 {`OR1200_WB_RETRY{1'b1}};
370			`else if (retry_cntr)`
371			`retry_cntr <= #1 retry_cntr - 7'd1;`
372			`endif
373
374			`//`
375			`// Graceful completion of aborted transfers`
376			`//`
377			`// Assert 'aborted' when 1) current transfer is in progress (wb_stb_o; which`
378			`// we know is only asserted together with wb_cyc_o) 2) and in next WB clock cycle`
379			`// wb_stb_o would be deasserted (biu_cyc_i and biu_stb_i are low) 3) and`
380			`// there is no termination of current transfer in this WB clock cycle (wb_ack_i`
381			`// and wb_err_i are low).`
382			`// 'aborted_r' is registered 'aborted' and extended until this "aborted" transfer`
383			`// is properly terminated with wb_ack_i/wb_err_i.`
384			`//`
385			`assign aborted = wb_stb_o & ~(biu_cyc_i & biu_stb_i) & ~(wb_ack_i \| wb_err_i);`
386			`always @(posedge wb_clk_i or posedge wb_rst_i)`
387			`if (wb_rst_i)`
388			`aborted_r <= #1 1'b0;`
389			`else if (wb_ack_i \| wb_err_i)`
390			`aborted_r <= #1 1'b0;`
391			`else if (aborted)`
392			`aborted_r <= #1 1'b1;`
393
394			`//`
395			`// WB cyc_o`
396			`//`
397			`// Either 1) normal transfer initiated by biu_cyc_i (and biu_cab_i if`
398			`// bursts are enabled) and possibly suspended by 'retry'`
399			`// or 2) extended "aborted" transfer`
400			`//`
401			`ifdef OR1200_REGISTERED_OUTPUTS
402			`always @(posedge wb_clk_i or posedge wb_rst_i)`
403			`if (wb_rst_i)`
404			`wb_cyc_o <= #1 1'b0;`
405			`else`
406			`ifdef OR1200_NO_BURSTS
407			`wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry & ~repeated_access \| aborted & ~wb_ack_i;`
408			`else
409			`wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry & ~repeated_access \| biu_cab_i \| aborted & ~wb_ack_i;`
410			`endif
411			`else
412			`ifdef OR1200_NO_BURSTS
413			`assign wb_cyc_o = biu_cyc_i & ~retry;`
414			`else
415			`assign wb_cyc_o = biu_cyc_i \| biu_cab_i & ~retry;`
416			`endif
417			`endif
418
419			`//`
420			`// WB stb_o`
421			`//`
422			`ifdef OR1200_REGISTERED_OUTPUTS
423			`always @(posedge wb_clk_i or posedge wb_rst_i)`
424			`if (wb_rst_i)`
425			`wb_stb_o <= #1 1'b0;`
426			`else`
427			`wb_stb_o <= #1 (biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~retry & ~repeated_access \| aborted & ~wb_ack_i;`
428			`else
429			`assign wb_stb_o = biu_cyc_i & biu_stb_i;`
430			`endif
431
432			`//`
433			`// WB we_o`
434			`//`
435			`ifdef OR1200_REGISTERED_OUTPUTS
436			`always @(posedge wb_clk_i or posedge wb_rst_i)`
437			`if (wb_rst_i)`
438			`wb_we_o <= #1 1'b0;`
439			`else`
440			`wb_we_o <= #1 biu_cyc_i & biu_stb_i & biu_we_i \| aborted & wb_we_o;`
441			`else
442			`assign wb_we_o = biu_cyc_i & biu_stb_i & biu_we_i;`
443			`endif
444
445			`//`
446			`// WB sel_o`
447			`//`
448			`ifdef OR1200_REGISTERED_OUTPUTS
449			`always @(posedge wb_clk_i or posedge wb_rst_i)`
450			`if (wb_rst_i)`
451			`wb_sel_o <= #1 4'b0000;`
452			`else`
453			`wb_sel_o <= #1 biu_sel_i;`
454			`else
455			`assign wb_sel_o = biu_sel_i;`
456			`endif
457
458			`ifdef OR1200_WB_CAB
459			`//`
460			`// WB cab_o`
461			`//`
462			`ifdef OR1200_REGISTERED_OUTPUTS
463			`always @(posedge wb_clk_i or posedge wb_rst_i)`
464			`if (wb_rst_i)`
465			`wb_cab_o <= #1 1'b0;`
466			`else`
467			`wb_cab_o <= #1 biu_cab_i;`
468			`else
469			`assign wb_cab_o = biu_cab_i;`
470			`endif
471			`endif
472
473			`ifdef OR1200_WB_B3
474			`//`
475			`// Count burst beats`
476			`//`
477			`always @(posedge wb_clk_i or posedge wb_rst_i)`
478			`if (wb_rst_i)`
479			`burst_len <= #1 2'b00;`
480			`else if (biu_cab_i && burst_len && wb_ack_i)`
481			`burst_len <= #1 burst_len - 1'b1;`
482			`else if (~biu_cab_i)`
483			`burst_len <= #1 2'b11;`
484
485			`//`
486			`// WB cti_o`
487			`//`
488			`ifdef OR1200_REGISTERED_OUTPUTS
489			`always @(posedge wb_clk_i or posedge wb_rst_i)`
490			`if (wb_rst_i)`
491			`wb_cti_o <= #1 3'b000; // classic cycle`
492			`ifdef OR1200_NO_BURSTS
493			`else`
494			`wb_cti_o <= #1 3'b111; // end-of-burst`
495			`else
496			`else if (biu_cab_i && burst_len[1])`
497			`wb_cti_o <= #1 3'b010; // incrementing burst cycle`
498			`else if (biu_cab_i && wb_ack_i)`
499			`wb_cti_o <= #1 3'b111; // end-of-burst`
500			`endif // OR1200_NO_BURSTS
501			`else
502			`Unsupported !!!;`
503			`endif
504
505			`//`
506			`// WB bte_o`
507			`//`
508			`assign wb_bte_o = 2'b01; // 4-beat wrap burst`
509
510			`endif // OR1200_WB_B3
511
512			`endmodule`