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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's mem2reg alignment                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Two versions of Memory to register data alignment.          ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:46  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_mem2reg(addr, lsu_op, memdata, regdata);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
input   [1:0]                    addr;
input   [`OR1200_LSUOP_WIDTH-1:0]        lsu_op;
input   [width-1:0]              memdata;
output  [width-1:0]              regdata;
 
 
//
// Faster implementation of mem2reg
//
`ifdef OR1200_MEM2REG_FAST
 
`define OR1200_M2R_BYTE0 4'b0000
`define OR1200_M2R_BYTE1 4'b0001
`define OR1200_M2R_BYTE2 4'b0010
`define OR1200_M2R_BYTE3 4'b0011
`define OR1200_M2R_EXTB0 4'b0100
`define OR1200_M2R_EXTB1 4'b0101
`define OR1200_M2R_EXTB2 4'b0110
`define OR1200_M2R_EXTB3 4'b0111
`define OR1200_M2R_ZERO  4'b0000
 
reg     [7:0]                    regdata_hh;
reg     [7:0]                    regdata_hl;
reg     [7:0]                    regdata_lh;
reg     [7:0]                    regdata_ll;
reg     [width-1:0]              aligned;
reg     [3:0]                    sel_byte0, sel_byte1,
                                sel_byte2, sel_byte3;
 
assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};
 
//
// Byte select 0
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
                {3'b01x, 2'b00}:                        // lbz/lbs 0
                        sel_byte0 = `OR1200_M2R_BYTE3;  // take byte 3
                {3'b01x, 2'b01},                        // lbz/lbs 1
                {3'b10x, 2'b00}:                        // lhz/lhs 0
                        sel_byte0 = `OR1200_M2R_BYTE2;  // take byte 2
                {3'b01x, 2'b10}:                        // lbz/lbs 2
                        sel_byte0 = `OR1200_M2R_BYTE1;  // take byte 1
                default:                                // all other cases
                        sel_byte0 = `OR1200_M2R_BYTE0;  // take byte 0
        endcase
end
 
//
// Byte select 1
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
                {3'b010, 2'bxx}:                        // lbz
                        sel_byte1 = `OR1200_M2R_ZERO;   // zero extend
                {3'b011, 2'b00}:                        // lbs 0
                        sel_byte1 = `OR1200_M2R_EXTB3;  // sign extend from byte 3
                {3'b011, 2'b01}:                        // lbs 1
                        sel_byte1 = `OR1200_M2R_EXTB2;  // sign extend from byte 2
                {3'b011, 2'b10}:                        // lbs 2
                        sel_byte1 = `OR1200_M2R_EXTB1;  // sign extend from byte 1
                {3'b011, 2'b11}:                        // lbs 3
                        sel_byte1 = `OR1200_M2R_EXTB0;  // sign extend from byte 0
                {3'b10x, 2'b00}:                        // lhz/lhs 0
                        sel_byte1 = `OR1200_M2R_BYTE3;  // take byte 3
                default:                                // all other cases
                        sel_byte1 = `OR1200_M2R_BYTE1;  // take byte 1
        endcase
end
 
//
// Byte select 2
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
                {3'b010, 2'bxx},                        // lbz
                {3'b100, 2'bxx}:                        // lhz
                        sel_byte2 = `OR1200_M2R_ZERO;   // zero extend
                {3'b011, 2'b00},                        // lbs 0
                {3'b101, 2'b00}:                        // lhs 0
                        sel_byte2 = `OR1200_M2R_EXTB3;  // sign extend from byte 3
                {3'b011, 2'b01}:                        // lbs 1
                        sel_byte2 = `OR1200_M2R_EXTB2;  // sign extend from byte 2
                {3'b011, 2'b10},                        // lbs 2
                {3'b101, 2'b10}:                        // lhs 0
                        sel_byte2 = `OR1200_M2R_EXTB1;  // sign extend from byte 1
                {3'b011, 2'b11}:                        // lbs 3
                        sel_byte2 = `OR1200_M2R_EXTB0;  // sign extend from byte 0
                default:                                // all other cases
                        sel_byte2 = `OR1200_M2R_BYTE2;  // take byte 2
        endcase
end
 
//
// Byte select 3
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
                {3'b010, 2'bxx},                        // lbz
                {3'b100, 2'bxx}:                        // lhz
                        sel_byte3 = `OR1200_M2R_ZERO;   // zero extend
                {3'b011, 2'b00},                        // lbs 0
                {3'b101, 2'b00}:                        // lhs 0
                        sel_byte3 = `OR1200_M2R_EXTB3;  // sign extend from byte 3
                {3'b011, 2'b01}:                        // lbs 1
                        sel_byte3 = `OR1200_M2R_EXTB2;  // sign extend from byte 2
                {3'b011, 2'b10},                        // lbs 2
                {3'b101, 2'b10}:                        // lhs 0
                        sel_byte3 = `OR1200_M2R_EXTB1;  // sign extend from byte 1
                {3'b011, 2'b11}:                        // lbs 3
                        sel_byte3 = `OR1200_M2R_EXTB0;  // sign extend from byte 0
                default:                                // all other cases
                        sel_byte3 = `OR1200_M2R_BYTE3;  // take byte 3
        endcase
end
 
//
// Byte 0
//
always @(sel_byte0 or memdata) begin
        case(sel_byte0) // synopsys full_case parallel_case infer_mux
                `OR1200_M2R_BYTE0: begin
                                regdata_ll = memdata[7:0];
                        end
                `OR1200_M2R_BYTE1: begin
                                regdata_ll = memdata[15:8];
                        end
                `OR1200_M2R_BYTE2: begin
                                regdata_ll = memdata[23:16];
                        end
                `OR1200_M2R_BYTE3: begin
                                regdata_ll = memdata[31:24];
                        end
        endcase
end
 
//
// Byte 1
//
always @(sel_byte1 or memdata) begin
        case(sel_byte1) // synopsys full_case parallel_case infer_mux
                `OR1200_M2R_ZERO: begin
                                regdata_lh = 8'h00;
                        end
                `OR1200_M2R_BYTE1: begin
                                regdata_lh = memdata[15:8];
                        end
                `OR1200_M2R_BYTE3: begin
                                regdata_lh = memdata[31:24];
                        end
                `OR1200_M2R_EXTB0: begin
                                regdata_lh = {8{memdata[7]}};
                        end
                `OR1200_M2R_EXTB1: begin
                                regdata_lh = {8{memdata[15]}};
                        end
                `OR1200_M2R_EXTB2: begin
                                regdata_lh = {8{memdata[23]}};
                        end
                `OR1200_M2R_EXTB3: begin
                                regdata_lh = {8{memdata[31]}};
                        end
        endcase
end
 
//
// Byte 2
//
always @(sel_byte2 or memdata) begin
        case(sel_byte2) // synopsys full_case parallel_case infer_mux
                `OR1200_M2R_ZERO: begin
                                regdata_hl = 8'h00;
                        end
                `OR1200_M2R_BYTE2: begin
                                regdata_hl = memdata[23:16];
                        end
                `OR1200_M2R_EXTB0: begin
                                regdata_hl = {8{memdata[7]}};
                        end
                `OR1200_M2R_EXTB1: begin
                                regdata_hl = {8{memdata[15]}};
                        end
                `OR1200_M2R_EXTB2: begin
                                regdata_hl = {8{memdata[23]}};
                        end
                `OR1200_M2R_EXTB3: begin
                                regdata_hl = {8{memdata[31]}};
                        end
        endcase
end
 
//
// Byte 3
//
always @(sel_byte3 or memdata) begin
        case(sel_byte3) // synopsys full_case parallel_case infer_mux
                `OR1200_M2R_ZERO: begin
                                regdata_hh = 8'h00;
                        end
                `OR1200_M2R_BYTE3: begin
                                regdata_hh = memdata[31:24];
                        end
                `OR1200_M2R_EXTB0: begin
                                regdata_hh = {8{memdata[7]}};
                        end
                `OR1200_M2R_EXTB1: begin
                                regdata_hh = {8{memdata[15]}};
                        end
                `OR1200_M2R_EXTB2: begin
                                regdata_hh = {8{memdata[23]}};
                        end
                `OR1200_M2R_EXTB3: begin
                                regdata_hh = {8{memdata[31]}};
                        end
        endcase
end
 
`else
 
//
// Slow implementation of mem2reg
//
 
reg     [width-1:0]              regdata;
reg     [width-1:0]              aligned;
 
//
// Alignment
//
always @(addr or memdata) begin
        case(addr) // synopsys infer_mux
                2'b00:
                        aligned = memdata;
                2'b01:
                        aligned = {memdata[23:0], 8'b0};
                2'b10:
                        aligned = {memdata[15:0], 16'b0};
                2'b11:
                        aligned = {memdata[7:0], 24'b0};
        endcase
end
 
//
// Bytes
//
always @(lsu_op or aligned) begin
        case(lsu_op) // synopsys infer_mux
                `OR1200_LSUOP_LBZ: begin
                                regdata[7:0] = aligned[31:24];
                                regdata[31:8] = 24'b0;
                        end
                `OR1200_LSUOP_LBS: begin
                                regdata[7:0] = aligned[31:24];
                                regdata[31:8] = {24{aligned[31]}};
                        end
                `OR1200_LSUOP_LHZ: begin
                                regdata[15:0] = aligned[31:16];
                                regdata[31:16] = 16'b0;
                        end
                `OR1200_LSUOP_LHS: begin
                                regdata[15:0] = aligned[31:16];
                                regdata[31:16] = {16{aligned[31]}};
                        end
                default:
                                regdata = aligned;
        endcase
end
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's mem2reg alignment ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Two versions of Memory to register data alignment. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	562	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
48			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
49			`//`
50	504	lampret	`// Revision 1.9 2001/10/21 17:57:16 lampret`
51			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
52			`//`
53			`// Revision 1.8 2001/10/19 23:28:46 lampret`
54			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
55			`//`
56			`// Revision 1.7 2001/10/14 13:12:09 lampret`
57			`// MP3 version.`
58			`//`
59			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
60			`// no message`
61			`//`
62			`// Revision 1.2 2001/08/09 13:39:33 lampret`
63			`// Major clean-up.`
64			`//`
65			`// Revision 1.1 2001/07/20 00:46:03 lampret`
66			`// Development version of RTL. Libraries are missing.`
67			`//`
68			`//`
69
70			`// synopsys translate_off`
71			`include "timescale.v"
72			`// synopsys translate_on`
73			`include "or1200_defines.v"
74
75			`module or1200_mem2reg(addr, lsu_op, memdata, regdata);`
76
77			parameter width = `OR1200_OPERAND_WIDTH;
78
79			`//`
80			`// I/O`
81			`//`
82			`input [1:0] addr;`
83			input [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
84			`input [width-1:0] memdata;`
85			`output [width-1:0] regdata;`
86
87
88			`//`
89			`// Faster implementation of mem2reg`
90			`//`
91			`ifdef OR1200_MEM2REG_FAST
92
93	562	lampret	`define OR1200_M2R_BYTE0 4'b0000
94			`define OR1200_M2R_BYTE1 4'b0001
95			`define OR1200_M2R_BYTE2 4'b0010
96			`define OR1200_M2R_BYTE3 4'b0011
97			`define OR1200_M2R_EXTB0 4'b0100
98			`define OR1200_M2R_EXTB1 4'b0101
99			`define OR1200_M2R_EXTB2 4'b0110
100			`define OR1200_M2R_EXTB3 4'b0111
101			`define OR1200_M2R_ZERO 4'b0000
102	504	lampret
103			`reg [7:0] regdata_hh;`
104			`reg [7:0] regdata_hl;`
105			`reg [7:0] regdata_lh;`
106			`reg [7:0] regdata_ll;`
107			`reg [width-1:0] aligned;`
108	562	lampret	`reg [3:0] sel_byte0, sel_byte1,`
109	504	lampret	`sel_byte2, sel_byte3;`
110
111			`assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};`
112
113			`//`
114			`// Byte select 0`
115			`//`
116			`always @(addr or lsu_op) begin`
117	562	lampret	`casex({lsu_op[2:0], addr}) // synopsys parallel_case`
118			`{3'b01x, 2'b00}: // lbz/lbs 0`
119			sel_byte0 = `OR1200_M2R_BYTE3; // take byte 3
120			`{3'b01x, 2'b01}, // lbz/lbs 1`
121			`{3'b10x, 2'b00}: // lhz/lhs 0`
122			sel_byte0 = `OR1200_M2R_BYTE2; // take byte 2
123			`{3'b01x, 2'b10}: // lbz/lbs 2`
124			sel_byte0 = `OR1200_M2R_BYTE1; // take byte 1
125			`default: // all other cases`
126			sel_byte0 = `OR1200_M2R_BYTE0; // take byte 0
127	504	lampret	`endcase`
128			`end`
129
130			`//`
131			`// Byte select 1`
132			`//`
133			`always @(addr or lsu_op) begin`
134	562	lampret	`casex({lsu_op[2:0], addr}) // synopsys parallel_case`
135			`{3'b010, 2'bxx}: // lbz`
136			sel_byte1 = `OR1200_M2R_ZERO; // zero extend
137			`{3'b011, 2'b00}: // lbs 0`
138			sel_byte1 = `OR1200_M2R_EXTB3; // sign extend from byte 3
139			`{3'b011, 2'b01}: // lbs 1`
140			sel_byte1 = `OR1200_M2R_EXTB2; // sign extend from byte 2
141			`{3'b011, 2'b10}: // lbs 2`
142			sel_byte1 = `OR1200_M2R_EXTB1; // sign extend from byte 1
143			`{3'b011, 2'b11}: // lbs 3`
144			sel_byte1 = `OR1200_M2R_EXTB0; // sign extend from byte 0
145			`{3'b10x, 2'b00}: // lhz/lhs 0`
146			sel_byte1 = `OR1200_M2R_BYTE3; // take byte 3
147			`default: // all other cases`
148			sel_byte1 = `OR1200_M2R_BYTE1; // take byte 1
149	504	lampret	`endcase`
150			`end`
151
152			`//`
153			`// Byte select 2`
154			`//`
155			`always @(addr or lsu_op) begin`
156	562	lampret	`casex({lsu_op[2:0], addr}) // synopsys parallel_case`
157			`{3'b010, 2'bxx}, // lbz`
158			`{3'b100, 2'bxx}: // lhz`
159			sel_byte2 = `OR1200_M2R_ZERO; // zero extend
160			`{3'b011, 2'b00}, // lbs 0`
161			`{3'b101, 2'b00}: // lhs 0`
162			sel_byte2 = `OR1200_M2R_EXTB3; // sign extend from byte 3
163			`{3'b011, 2'b01}: // lbs 1`
164			sel_byte2 = `OR1200_M2R_EXTB2; // sign extend from byte 2
165			`{3'b011, 2'b10}, // lbs 2`
166			`{3'b101, 2'b10}: // lhs 0`
167			sel_byte2 = `OR1200_M2R_EXTB1; // sign extend from byte 1
168			`{3'b011, 2'b11}: // lbs 3`
169			sel_byte2 = `OR1200_M2R_EXTB0; // sign extend from byte 0
170			`default: // all other cases`
171			sel_byte2 = `OR1200_M2R_BYTE2; // take byte 2
172	504	lampret	`endcase`
173			`end`
174
175			`//`
176			`// Byte select 3`
177			`//`
178			`always @(addr or lsu_op) begin`
179	562	lampret	`casex({lsu_op[2:0], addr}) // synopsys parallel_case`
180			`{3'b010, 2'bxx}, // lbz`
181			`{3'b100, 2'bxx}: // lhz`
182			sel_byte3 = `OR1200_M2R_ZERO; // zero extend
183			`{3'b011, 2'b00}, // lbs 0`
184			`{3'b101, 2'b00}: // lhs 0`
185			sel_byte3 = `OR1200_M2R_EXTB3; // sign extend from byte 3
186			`{3'b011, 2'b01}: // lbs 1`
187			sel_byte3 = `OR1200_M2R_EXTB2; // sign extend from byte 2
188			`{3'b011, 2'b10}, // lbs 2`
189			`{3'b101, 2'b10}: // lhs 0`
190			sel_byte3 = `OR1200_M2R_EXTB1; // sign extend from byte 1
191			`{3'b011, 2'b11}: // lbs 3`
192			sel_byte3 = `OR1200_M2R_EXTB0; // sign extend from byte 0
193			`default: // all other cases`
194			sel_byte3 = `OR1200_M2R_BYTE3; // take byte 3
195	504	lampret	`endcase`
196			`end`
197
198			`//`
199			`// Byte 0`
200			`//`
201			`always @(sel_byte0 or memdata) begin`
202			`case(sel_byte0) // synopsys full_case parallel_case infer_mux`
203	562	lampret	`OR1200_M2R_BYTE0: begin
204	504	lampret	`regdata_ll = memdata[7:0];`
205			`end`
206	562	lampret	`OR1200_M2R_BYTE1: begin
207	504	lampret	`regdata_ll = memdata[15:8];`
208			`end`
209	562	lampret	`OR1200_M2R_BYTE2: begin
210	504	lampret	`regdata_ll = memdata[23:16];`
211			`end`
212	562	lampret	`OR1200_M2R_BYTE3: begin
213	504	lampret	`regdata_ll = memdata[31:24];`
214			`end`
215			`endcase`
216			`end`
217
218			`//`
219			`// Byte 1`
220			`//`
221			`always @(sel_byte1 or memdata) begin`
222			`case(sel_byte1) // synopsys full_case parallel_case infer_mux`
223	562	lampret	`OR1200_M2R_ZERO: begin
224			`regdata_lh = 8'h00;`
225	504	lampret	`end`
226	562	lampret	`OR1200_M2R_BYTE1: begin
227	504	lampret	`regdata_lh = memdata[15:8];`
228			`end`
229	562	lampret	`OR1200_M2R_BYTE3: begin
230			`regdata_lh = memdata[31:24];`
231			`end`
232			`OR1200_M2R_EXTB0: begin
233	504	lampret	`regdata_lh = {8{memdata[7]}};`
234			`end`
235	562	lampret	`OR1200_M2R_EXTB1: begin
236			`regdata_lh = {8{memdata[15]}};`
237	504	lampret	`end`
238	562	lampret	`OR1200_M2R_EXTB2: begin
239			`regdata_lh = {8{memdata[23]}};`
240			`end`
241			`OR1200_M2R_EXTB3: begin
242			`regdata_lh = {8{memdata[31]}};`
243			`end`
244	504	lampret	`endcase`
245			`end`
246
247			`//`
248			`// Byte 2`
249			`//`
250			`always @(sel_byte2 or memdata) begin`
251			`case(sel_byte2) // synopsys full_case parallel_case infer_mux`
252	562	lampret	`OR1200_M2R_ZERO: begin
253			`regdata_hl = 8'h00;`
254	504	lampret	`end`
255	562	lampret	`OR1200_M2R_BYTE2: begin
256			`regdata_hl = memdata[23:16];`
257			`end`
258			`OR1200_M2R_EXTB0: begin
259	504	lampret	`regdata_hl = {8{memdata[7]}};`
260			`end`
261	562	lampret	`OR1200_M2R_EXTB1: begin
262	504	lampret	`regdata_hl = {8{memdata[15]}};`
263			`end`
264	562	lampret	`OR1200_M2R_EXTB2: begin
265			`regdata_hl = {8{memdata[23]}};`
266			`end`
267			`OR1200_M2R_EXTB3: begin
268			`regdata_hl = {8{memdata[31]}};`
269			`end`
270	504	lampret	`endcase`
271			`end`
272
273			`//`
274			`// Byte 3`
275			`//`
276			`always @(sel_byte3 or memdata) begin`
277			`case(sel_byte3) // synopsys full_case parallel_case infer_mux`
278	562	lampret	`OR1200_M2R_ZERO: begin
279			`regdata_hh = 8'h00;`
280	504	lampret	`end`
281	562	lampret	`OR1200_M2R_BYTE3: begin
282			`regdata_hh = memdata[31:24];`
283			`end`
284			`OR1200_M2R_EXTB0: begin
285	504	lampret	`regdata_hh = {8{memdata[7]}};`
286			`end`
287	562	lampret	`OR1200_M2R_EXTB1: begin
288	504	lampret	`regdata_hh = {8{memdata[15]}};`
289			`end`
290	562	lampret	`OR1200_M2R_EXTB2: begin
291			`regdata_hh = {8{memdata[23]}};`
292	504	lampret	`end`
293	562	lampret	`OR1200_M2R_EXTB3: begin
294			`regdata_hh = {8{memdata[31]}};`
295			`end`
296	504	lampret	`endcase`
297			`end`
298
299			`else
300
301			`//`
302			`// Slow implementation of mem2reg`
303			`//`
304
305			`reg [width-1:0] regdata;`
306			`reg [width-1:0] aligned;`
307
308			`//`
309			`// Alignment`
310			`//`
311			`always @(addr or memdata) begin`
312			`case(addr) // synopsys infer_mux`
313			`2'b00:`
314			`aligned = memdata;`
315			`2'b01:`
316			`aligned = {memdata[23:0], 8'b0};`
317			`2'b10:`
318			`aligned = {memdata[15:0], 16'b0};`
319			`2'b11:`
320			`aligned = {memdata[7:0], 24'b0};`
321			`endcase`
322			`end`
323
324			`//`
325			`// Bytes`
326			`//`
327			`always @(lsu_op or aligned) begin`
328			`case(lsu_op) // synopsys infer_mux`
329			`OR1200_LSUOP_LBZ: begin
330			`regdata[7:0] = aligned[31:24];`
331			`regdata[31:8] = 24'b0;`
332			`end`
333			`OR1200_LSUOP_LBS: begin
334			`regdata[7:0] = aligned[31:24];`
335			`regdata[31:8] = {24{aligned[31]}};`
336			`end`
337			`OR1200_LSUOP_LHZ: begin
338			`regdata[15:0] = aligned[31:16];`
339			`regdata[31:16] = 16'b0;`
340			`end`
341			`OR1200_LSUOP_LHS: begin
342			`regdata[15:0] = aligned[31:16];`
343			`regdata[31:16] = {16{aligned[31]}};`
344			`end`
345			`default:`
346			`regdata = aligned;`
347			`endcase`
348			`end`
349
350			`endif
351
352			`endmodule`

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