URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_qmem_top.v] - Blame information for rev 1172

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Embedded Memory                                    ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Embedded Memory               .                             ////
////                                                              ////
////  To Do:                                                      ////
////   - QMEM and IC/DC muxes can be removed except for cycstb    ////
////     (now are is there for easier debugging)                  ////
////   - currently arbitration is slow and stores take 2 clocks   ////
////     (final debugged version will be faster)                  ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2003 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
`define OR1200_QMEMFSM_IDLE     3'd0
`define OR1200_QMEMFSM_STORE    3'd1
`define OR1200_QMEMFSM_LOAD     3'd2
`define OR1200_QMEMFSM_FETCH    3'd3
 
//
// Embedded memory
//
module or1200_qmem_top(
        // Rst, clk and clock control
        clk, rst,
 
`ifdef OR1200_BIST
        // RAM BIST
        scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
 
        // QMEM and CPU/IMMU
        qmemimmu_adr_i,
        qmemimmu_cycstb_i,
        qmemimmu_ci_i,
        qmemicpu_sel_i,
        qmemicpu_tag_i,
        qmemicpu_dat_o,
        qmemicpu_ack_o,
        qmemimmu_rty_o,
        qmemimmu_err_o,
        qmemimmu_tag_o,
 
        // QMEM and IC
        icqmem_adr_o,
        icqmem_cycstb_o,
        icqmem_ci_o,
        icqmem_sel_o,
        icqmem_tag_o,
        icqmem_dat_i,
        icqmem_ack_i,
        icqmem_rty_i,
        icqmem_err_i,
        icqmem_tag_i,
 
        // QMEM and CPU/DMMU
        qmemdmmu_adr_i,
        qmemdmmu_cycstb_i,
        qmemdmmu_ci_i,
        qmemdcpu_we_i,
        qmemdcpu_sel_i,
        qmemdcpu_tag_i,
        qmemdcpu_dat_i,
        qmemdcpu_dat_o,
        qmemdcpu_ack_o,
        qmemdcpu_rty_o,
        qmemdmmu_err_o,
        qmemdmmu_tag_o,
 
        // QMEM and DC
        dcqmem_adr_o, dcqmem_cycstb_o, dcqmem_ci_o,
        dcqmem_we_o, dcqmem_sel_o, dcqmem_tag_o, dcqmem_dat_o,
        dcqmem_dat_i, dcqmem_ack_i, dcqmem_rty_i, dcqmem_err_i, dcqmem_tag_i
 
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input                           scanb_rst,
                                scanb_si,
                                scanb_en,
                                scanb_clk;
output                          scanb_so;
`endif
 
//
// QMEM and CPU/IMMU
//
input   [31:0]                   qmemimmu_adr_i;
input                           qmemimmu_cycstb_i;
input                           qmemimmu_ci_i;
input   [3:0]                    qmemicpu_sel_i;
input   [3:0]                    qmemicpu_tag_i;
output  [31:0]                   qmemicpu_dat_o;
output                          qmemicpu_ack_o;
output                          qmemimmu_rty_o;
output                          qmemimmu_err_o;
output  [3:0]                    qmemimmu_tag_o;
 
//
// QMEM and IC
//
output  [31:0]                   icqmem_adr_o;
output                          icqmem_cycstb_o;
output                          icqmem_ci_o;
output  [3:0]                    icqmem_sel_o;
output  [3:0]                    icqmem_tag_o;
input   [31:0]                   icqmem_dat_i;
input                           icqmem_ack_i;
input                           icqmem_rty_i;
input                           icqmem_err_i;
input   [3:0]                    icqmem_tag_i;
 
//
// QMEM and CPU/DMMU
//
input   [31:0]                   qmemdmmu_adr_i;
input                           qmemdmmu_cycstb_i;
input                           qmemdmmu_ci_i;
input                           qmemdcpu_we_i;
input   [3:0]                    qmemdcpu_sel_i;
input   [3:0]                    qmemdcpu_tag_i;
input   [31:0]                   qmemdcpu_dat_i;
output  [31:0]                   qmemdcpu_dat_o;
output                          qmemdcpu_ack_o;
output                          qmemdcpu_rty_o;
output                          qmemdmmu_err_o;
output  [3:0]                    qmemdmmu_tag_o;
 
//
// QMEM and DC
//
output  [31:0]                   dcqmem_adr_o;
output                          dcqmem_cycstb_o;
output                          dcqmem_ci_o;
output                          dcqmem_we_o;
output  [3:0]                    dcqmem_sel_o;
output  [3:0]                    dcqmem_tag_o;
output  [dw-1:0]         dcqmem_dat_o;
input   [dw-1:0]         dcqmem_dat_i;
input                           dcqmem_ack_i;
input                           dcqmem_rty_i;
input                           dcqmem_err_i;
input   [3:0]                    dcqmem_tag_i;
 
`ifdef OR1200_QMEM_IMPLEMENTED
 
//
// Internal regs and wires
//
wire                            iaddr_qmem_hit;
wire                            daddr_qmem_hit;
reg     [2:0]                    state;
reg                             qmem_dack;
reg                             qmem_iack;
wire    [31:0]                   qmem_di;
wire    [31:0]                   qmem_do;
wire                            qmem_en;
wire                            qmem_we;
wire    [31:0]                   qmem_addr;
 
//
// QMEM and CPU/IMMU
//
assign qmemicpu_dat_o = qmem_iack ? qmem_do : icqmem_dat_i;
assign qmemicpu_ack_o = qmem_iack ? 1'b1 : icqmem_ack_i;
assign qmemimmu_rty_o = qmem_iack ? 1'b0 : icqmem_rty_i;
assign qmemimmu_err_o = qmem_iack ? 1'b0 : icqmem_err_i;
assign qmemimmu_tag_o = qmem_iack ? 4'h0 : icqmem_tag_i;
 
//
// QMEM and IC
//
assign icqmem_adr_o = iaddr_qmem_hit ? 32'h0000_0000 : qmemimmu_adr_i;
assign icqmem_cycstb_o = iaddr_qmem_hit ? 1'b0 : qmemimmu_cycstb_i;
assign icqmem_ci_o = iaddr_qmem_hit ? 1'b0 : qmemimmu_ci_i;
assign icqmem_sel_o = iaddr_qmem_hit ? 4'h0 : qmemicpu_sel_i;
assign icqmem_tag_o = iaddr_qmem_hit ? 4'h0 : qmemicpu_tag_i;
 
//
// QMEM and CPU/DMMU
//
assign qmemdcpu_dat_o = daddr_qmem_hit ? qmem_do : dcqmem_dat_i;
assign qmemdcpu_ack_o = daddr_qmem_hit ? qmem_dack : dcqmem_ack_i;
assign qmemdcpu_rty_o = daddr_qmem_hit ? 1'b0 : dcqmem_rty_i;
assign qmemdmmu_err_o = daddr_qmem_hit ? 1'b0 : dcqmem_err_i;
assign qmemdmmu_tag_o = daddr_qmem_hit ? 4'h0 : dcqmem_tag_i;
 
//
// QMEM and DC
//
assign dcqmem_adr_o = daddr_qmem_hit ? 32'h0000_0000 : qmemdmmu_adr_i;
assign dcqmem_cycstb_o = daddr_qmem_hit ? 1'b0 : qmemdmmu_cycstb_i;
assign dcqmem_ci_o = daddr_qmem_hit ? 1'b0 : qmemdmmu_ci_i;
assign dcqmem_we_o = daddr_qmem_hit ? 1'b0 : qmemdcpu_we_i;
assign dcqmem_sel_o = daddr_qmem_hit ? 4'h0 : qmemdcpu_sel_i;
assign dcqmem_tag_o = daddr_qmem_hit ? 4'h0 : qmemdcpu_tag_i;
assign dcqmem_dat_o = daddr_qmem_hit ? 32'h0000_0000 : qmemdcpu_dat_i;
 
//
// Address comparison whether QMEM was hit
//
assign iaddr_qmem_hit = (qmemimmu_adr_i & `OR1200_QMEM_MASK) == `OR1200_QMEM_ADDR;
assign daddr_qmem_hit = (qmemdmmu_adr_i & `OR1200_QMEM_MASK) == `OR1200_QMEM_ADDR;
 
//
//
//
assign qmem_en = iaddr_qmem_hit & qmemimmu_cycstb_i | daddr_qmem_hit & qmemdmmu_cycstb_i;
assign qmem_we = qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i;
assign qmem_di = qmemdcpu_dat_i;
assign qmem_addr = (qmemdmmu_cycstb_i & daddr_qmem_hit) ? qmemdmmu_adr_i : qmemimmu_adr_i;
 
//
// QMEM control FSM
//
always @(posedge rst or posedge clk)
        if (rst) begin
                state <= #1 `OR1200_QMEMFSM_IDLE;
                qmem_dack <= #1 1'b0;
                qmem_iack <= #1 1'b0;
        end
        else case (state)       // synopsys parallel_case
                `OR1200_QMEMFSM_IDLE: begin
                        if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i) begin
                                state <= #1 `OR1200_QMEMFSM_STORE;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemdmmu_cycstb_i & daddr_qmem_hit) begin
                                state <= #1 `OR1200_QMEMFSM_LOAD;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemimmu_cycstb_i & iaddr_qmem_hit) begin
                                state <= #1 `OR1200_QMEMFSM_FETCH;
                                qmem_iack <= #1 1'b1;
                                qmem_dack <= #1 1'b0;
                        end
                end
                `OR1200_QMEMFSM_STORE: begin
                        if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i) begin
                                state <= #1 `OR1200_QMEMFSM_STORE;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemdmmu_cycstb_i & daddr_qmem_hit) begin
                                state <= #1 `OR1200_QMEMFSM_LOAD;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemimmu_cycstb_i & iaddr_qmem_hit) begin
                                state <= #1 `OR1200_QMEMFSM_FETCH;
                                qmem_iack <= #1 1'b1;
                                qmem_dack <= #1 1'b0;
                        end
                        else begin
                                state <= #1 `OR1200_QMEMFSM_IDLE;
                                qmem_dack <= #1 1'b0;
                                qmem_iack <= #1 1'b0;
                        end
                end
                `OR1200_QMEMFSM_LOAD: begin
                        if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i) begin
                                state <= #1 `OR1200_QMEMFSM_STORE;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemdmmu_cycstb_i & daddr_qmem_hit) begin
                                state <= #1 `OR1200_QMEMFSM_LOAD;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemimmu_cycstb_i & iaddr_qmem_hit) begin
                                state <= #1 `OR1200_QMEMFSM_FETCH;
                                qmem_iack <= #1 1'b1;
                                qmem_dack <= #1 1'b0;
                        end
                        else begin
                                state <= #1 `OR1200_QMEMFSM_IDLE;
                                qmem_dack <= #1 1'b0;
                                qmem_iack <= #1 1'b0;
                        end
                end
                `OR1200_QMEMFSM_FETCH: begin
                        if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i) begin
                                state <= #1 `OR1200_QMEMFSM_STORE;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemdmmu_cycstb_i & daddr_qmem_hit) begin
                                state <= #1 `OR1200_QMEMFSM_LOAD;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemimmu_cycstb_i & iaddr_qmem_hit) begin
                                state <= #1 `OR1200_QMEMFSM_FETCH;
                                qmem_iack <= #1 1'b1;
                                qmem_dack <= #1 1'b0;
                        end
                        else begin
                                state <= #1 `OR1200_QMEMFSM_IDLE;
                                qmem_dack <= #1 1'b0;
                                qmem_iack <= #1 1'b0;
                        end
                end
        endcase
 
//
// Instantiation of embedded memory
//
or1200_spram_2048x32 or1200_qmem_ram(
        .clk(clk),
        .rst(rst),
`ifdef OR1200_BIST
        // RAM BIST
        .scanb_rst(scanb_rst),
        .scanb_si(scanb_si),
        .scanb_so(scanb_so),
        .scanb_en(scanb_en),
        .scanb_clk(scanb_clk),
`endif
        .addr(qmem_addr[12:2]),
        .ce(qmem_en),
        .we(qmem_we),
        .oe(1'b1),
        .di(qmem_di),
        .do(qmem_do)
);
 
`else  // OR1200_QMEM_IMPLEMENTED
 
//
// QMEM and CPU/IMMU
//
assign qmemicpu_dat_o = icqmem_dat_i;
assign qmemicpu_ack_o = icqmem_ack_i;
assign qmemimmu_rty_o = icqmem_rty_i;
assign qmemimmu_err_o = icqmem_err_i;
assign qmemimmu_tag_o = icqmem_tag_i;
 
//
// QMEM and IC
//
assign icqmem_adr_o = qmemimmu_adr_i;
assign icqmem_cycstb_o = qmemimmu_cycstb_i;
assign icqmem_ci_o = qmemimmu_ci_i;
assign icqmem_sel_o = qmemicpu_sel_i;
assign icqmem_tag_o = qmemicpu_tag_i;
 
//
// QMEM and CPU/DMMU
//
assign qmemdcpu_dat_o = dcqmem_dat_i;
assign qmemdcpu_ack_o = dcqmem_ack_i;
assign qmemdcpu_rty_o = dcqmem_rty_i;
assign qmemdmmu_err_o = dcqmem_err_i;
assign qmemdmmu_tag_o = dcqmem_tag_i;
 
//
// QMEM and DC
//
assign dcqmem_adr_o = qmemdmmu_adr_i;
assign dcqmem_cycstb_o = qmemdmmu_cycstb_i;
assign dcqmem_ci_o = qmemdmmu_ci_i;
assign dcqmem_we_o = qmemdcpu_we_i;
assign dcqmem_sel_o = qmemdcpu_sel_i;
assign dcqmem_tag_o = qmemdcpu_tag_i;
assign dcqmem_dat_o = qmemdcpu_dat_i;
 
`endif
 
endmodule

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_qmem_top.v] - Blame information for rev 1172

Line No.	Rev	Author	Line
1	1172	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Embedded Memory ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Embedded Memory . ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - QMEM and IC/DC muxes can be removed except for cycstb ////`
13			`//// (now are is there for easier debugging) ////`
14			`//// - currently arbitration is slow and stores take 2 clocks ////`
15			`//// (final debugged version will be faster) ////`
16			`//// ////`
17			`//// Author(s): ////`
18			`//// - Damjan Lampret, lampret@opencores.org ////`
19			`//// ////`
20			`//////////////////////////////////////////////////////////////////////`
21			`//// ////`
22			`//// Copyright (C) 2003 Authors and OPENCORES.ORG ////`
23			`//// ////`
24			`//// This source file may be used and distributed without ////`
25			`//// restriction provided that this copyright statement is not ////`
26			`//// removed from the file and that any derivative work contains ////`
27			`//// the original copyright notice and the associated disclaimer. ////`
28			`//// ////`
29			`//// This source file is free software; you can redistribute it ////`
30			`//// and/or modify it under the terms of the GNU Lesser General ////`
31			`//// Public License as published by the Free Software Foundation; ////`
32			`//// either version 2.1 of the License, or (at your option) any ////`
33			`//// later version. ////`
34			`//// ////`
35			`//// This source is distributed in the hope that it will be ////`
36			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
37			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
38			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
39			`//// details. ////`
40			`//// ////`
41			`//// You should have received a copy of the GNU Lesser General ////`
42			`//// Public License along with this source; if not, download it ////`
43			`//// from http://www.opencores.org/lgpl.shtml ////`
44			`//// ////`
45			`//////////////////////////////////////////////////////////////////////`
46			`//`
47			`// CVS Revision History`
48			`//`
49			`// $Log: not supported by cvs2svn $`
50			`//`
51
52			`// synopsys translate_off`
53			`include "timescale.v"
54			`// synopsys translate_on`
55			`include "or1200_defines.v"
56
57			`define OR1200_QMEMFSM_IDLE 3'd0
58			`define OR1200_QMEMFSM_STORE 3'd1
59			`define OR1200_QMEMFSM_LOAD 3'd2
60			`define OR1200_QMEMFSM_FETCH 3'd3
61
62			`//`
63			`// Embedded memory`
64			`//`
65			`module or1200_qmem_top(`
66			`// Rst, clk and clock control`
67			`clk, rst,`
68
69			`ifdef OR1200_BIST
70			`// RAM BIST`
71			`scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,`
72			`endif
73
74			`// QMEM and CPU/IMMU`
75			`qmemimmu_adr_i,`
76			`qmemimmu_cycstb_i,`
77			`qmemimmu_ci_i,`
78			`qmemicpu_sel_i,`
79			`qmemicpu_tag_i,`
80			`qmemicpu_dat_o,`
81			`qmemicpu_ack_o,`
82			`qmemimmu_rty_o,`
83			`qmemimmu_err_o,`
84			`qmemimmu_tag_o,`
85
86			`// QMEM and IC`
87			`icqmem_adr_o,`
88			`icqmem_cycstb_o,`
89			`icqmem_ci_o,`
90			`icqmem_sel_o,`
91			`icqmem_tag_o,`
92			`icqmem_dat_i,`
93			`icqmem_ack_i,`
94			`icqmem_rty_i,`
95			`icqmem_err_i,`
96			`icqmem_tag_i,`
97
98			`// QMEM and CPU/DMMU`
99			`qmemdmmu_adr_i,`
100			`qmemdmmu_cycstb_i,`
101			`qmemdmmu_ci_i,`
102			`qmemdcpu_we_i,`
103			`qmemdcpu_sel_i,`
104			`qmemdcpu_tag_i,`
105			`qmemdcpu_dat_i,`
106			`qmemdcpu_dat_o,`
107			`qmemdcpu_ack_o,`
108			`qmemdcpu_rty_o,`
109			`qmemdmmu_err_o,`
110			`qmemdmmu_tag_o,`
111
112			`// QMEM and DC`
113			`dcqmem_adr_o, dcqmem_cycstb_o, dcqmem_ci_o,`
114			`dcqmem_we_o, dcqmem_sel_o, dcqmem_tag_o, dcqmem_dat_o,`
115			`dcqmem_dat_i, dcqmem_ack_i, dcqmem_rty_i, dcqmem_err_i, dcqmem_tag_i`
116
117			`);`
118
119			parameter dw = `OR1200_OPERAND_WIDTH;
120
121			`//`
122			`// I/O`
123			`//`
124
125			`//`
126			`// Clock and reset`
127			`//`
128			`input clk;`
129			`input rst;`
130
131			`ifdef OR1200_BIST
132			`//`
133			`// RAM BIST`
134			`//`
135			`input scanb_rst,`
136			`scanb_si,`
137			`scanb_en,`
138			`scanb_clk;`
139			`output scanb_so;`
140			`endif
141
142			`//`
143			`// QMEM and CPU/IMMU`
144			`//`
145			`input [31:0] qmemimmu_adr_i;`
146			`input qmemimmu_cycstb_i;`
147			`input qmemimmu_ci_i;`
148			`input [3:0] qmemicpu_sel_i;`
149			`input [3:0] qmemicpu_tag_i;`
150			`output [31:0] qmemicpu_dat_o;`
151			`output qmemicpu_ack_o;`
152			`output qmemimmu_rty_o;`
153			`output qmemimmu_err_o;`
154			`output [3:0] qmemimmu_tag_o;`
155
156			`//`
157			`// QMEM and IC`
158			`//`
159			`output [31:0] icqmem_adr_o;`
160			`output icqmem_cycstb_o;`
161			`output icqmem_ci_o;`
162			`output [3:0] icqmem_sel_o;`
163			`output [3:0] icqmem_tag_o;`
164			`input [31:0] icqmem_dat_i;`
165			`input icqmem_ack_i;`
166			`input icqmem_rty_i;`
167			`input icqmem_err_i;`
168			`input [3:0] icqmem_tag_i;`
169
170			`//`
171			`// QMEM and CPU/DMMU`
172			`//`
173			`input [31:0] qmemdmmu_adr_i;`
174			`input qmemdmmu_cycstb_i;`
175			`input qmemdmmu_ci_i;`
176			`input qmemdcpu_we_i;`
177			`input [3:0] qmemdcpu_sel_i;`
178			`input [3:0] qmemdcpu_tag_i;`
179			`input [31:0] qmemdcpu_dat_i;`
180			`output [31:0] qmemdcpu_dat_o;`
181			`output qmemdcpu_ack_o;`
182			`output qmemdcpu_rty_o;`
183			`output qmemdmmu_err_o;`
184			`output [3:0] qmemdmmu_tag_o;`
185
186			`//`
187			`// QMEM and DC`
188			`//`
189			`output [31:0] dcqmem_adr_o;`
190			`output dcqmem_cycstb_o;`
191			`output dcqmem_ci_o;`
192			`output dcqmem_we_o;`
193			`output [3:0] dcqmem_sel_o;`
194			`output [3:0] dcqmem_tag_o;`
195			`output [dw-1:0] dcqmem_dat_o;`
196			`input [dw-1:0] dcqmem_dat_i;`
197			`input dcqmem_ack_i;`
198			`input dcqmem_rty_i;`
199			`input dcqmem_err_i;`
200			`input [3:0] dcqmem_tag_i;`
201
202			`ifdef OR1200_QMEM_IMPLEMENTED
203
204			`//`
205			`// Internal regs and wires`
206			`//`
207			`wire iaddr_qmem_hit;`
208			`wire daddr_qmem_hit;`
209			`reg [2:0] state;`
210			`reg qmem_dack;`
211			`reg qmem_iack;`
212			`wire [31:0] qmem_di;`
213			`wire [31:0] qmem_do;`
214			`wire qmem_en;`
215			`wire qmem_we;`
216			`wire [31:0] qmem_addr;`
217
218			`//`
219			`// QMEM and CPU/IMMU`
220			`//`
221			`assign qmemicpu_dat_o = qmem_iack ? qmem_do : icqmem_dat_i;`
222			`assign qmemicpu_ack_o = qmem_iack ? 1'b1 : icqmem_ack_i;`
223			`assign qmemimmu_rty_o = qmem_iack ? 1'b0 : icqmem_rty_i;`
224			`assign qmemimmu_err_o = qmem_iack ? 1'b0 : icqmem_err_i;`
225			`assign qmemimmu_tag_o = qmem_iack ? 4'h0 : icqmem_tag_i;`
226
227			`//`
228			`// QMEM and IC`
229			`//`
230			`assign icqmem_adr_o = iaddr_qmem_hit ? 32'h0000_0000 : qmemimmu_adr_i;`
231			`assign icqmem_cycstb_o = iaddr_qmem_hit ? 1'b0 : qmemimmu_cycstb_i;`
232			`assign icqmem_ci_o = iaddr_qmem_hit ? 1'b0 : qmemimmu_ci_i;`
233			`assign icqmem_sel_o = iaddr_qmem_hit ? 4'h0 : qmemicpu_sel_i;`
234			`assign icqmem_tag_o = iaddr_qmem_hit ? 4'h0 : qmemicpu_tag_i;`
235
236			`//`
237			`// QMEM and CPU/DMMU`
238			`//`
239			`assign qmemdcpu_dat_o = daddr_qmem_hit ? qmem_do : dcqmem_dat_i;`
240			`assign qmemdcpu_ack_o = daddr_qmem_hit ? qmem_dack : dcqmem_ack_i;`
241			`assign qmemdcpu_rty_o = daddr_qmem_hit ? 1'b0 : dcqmem_rty_i;`
242			`assign qmemdmmu_err_o = daddr_qmem_hit ? 1'b0 : dcqmem_err_i;`
243			`assign qmemdmmu_tag_o = daddr_qmem_hit ? 4'h0 : dcqmem_tag_i;`
244
245			`//`
246			`// QMEM and DC`
247			`//`
248			`assign dcqmem_adr_o = daddr_qmem_hit ? 32'h0000_0000 : qmemdmmu_adr_i;`
249			`assign dcqmem_cycstb_o = daddr_qmem_hit ? 1'b0 : qmemdmmu_cycstb_i;`
250			`assign dcqmem_ci_o = daddr_qmem_hit ? 1'b0 : qmemdmmu_ci_i;`
251			`assign dcqmem_we_o = daddr_qmem_hit ? 1'b0 : qmemdcpu_we_i;`
252			`assign dcqmem_sel_o = daddr_qmem_hit ? 4'h0 : qmemdcpu_sel_i;`
253			`assign dcqmem_tag_o = daddr_qmem_hit ? 4'h0 : qmemdcpu_tag_i;`
254			`assign dcqmem_dat_o = daddr_qmem_hit ? 32'h0000_0000 : qmemdcpu_dat_i;`
255
256			`//`
257			`// Address comparison whether QMEM was hit`
258			`//`
259			assign iaddr_qmem_hit = (qmemimmu_adr_i & `OR1200_QMEM_MASK) == `OR1200_QMEM_ADDR;
260			assign daddr_qmem_hit = (qmemdmmu_adr_i & `OR1200_QMEM_MASK) == `OR1200_QMEM_ADDR;
261
262			`//`
263			`//`
264			`//`
265			`assign qmem_en = iaddr_qmem_hit & qmemimmu_cycstb_i \| daddr_qmem_hit & qmemdmmu_cycstb_i;`
266			`assign qmem_we = qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i;`
267			`assign qmem_di = qmemdcpu_dat_i;`
268			`assign qmem_addr = (qmemdmmu_cycstb_i & daddr_qmem_hit) ? qmemdmmu_adr_i : qmemimmu_adr_i;`
269
270			`//`
271			`// QMEM control FSM`
272			`//`
273			`always @(posedge rst or posedge clk)`
274			`if (rst) begin`
275			state <= #1 `OR1200_QMEMFSM_IDLE;
276			`qmem_dack <= #1 1'b0;`
277			`qmem_iack <= #1 1'b0;`
278			`end`
279			`else case (state) // synopsys parallel_case`
280			`OR1200_QMEMFSM_IDLE: begin
281			`if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i) begin`
282			state <= #1 `OR1200_QMEMFSM_STORE;
283			`qmem_dack <= #1 1'b1;`
284			`qmem_iack <= #1 1'b0;`
285			`end`
286			`else if (qmemdmmu_cycstb_i & daddr_qmem_hit) begin`
287			state <= #1 `OR1200_QMEMFSM_LOAD;
288			`qmem_dack <= #1 1'b1;`
289			`qmem_iack <= #1 1'b0;`
290			`end`
291			`else if (qmemimmu_cycstb_i & iaddr_qmem_hit) begin`
292			state <= #1 `OR1200_QMEMFSM_FETCH;
293			`qmem_iack <= #1 1'b1;`
294			`qmem_dack <= #1 1'b0;`
295			`end`
296			`end`
297			`OR1200_QMEMFSM_STORE: begin
298			`if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i) begin`
299			state <= #1 `OR1200_QMEMFSM_STORE;
300			`qmem_dack <= #1 1'b1;`
301			`qmem_iack <= #1 1'b0;`
302			`end`
303			`else if (qmemdmmu_cycstb_i & daddr_qmem_hit) begin`
304			state <= #1 `OR1200_QMEMFSM_LOAD;
305			`qmem_dack <= #1 1'b1;`
306			`qmem_iack <= #1 1'b0;`
307			`end`
308			`else if (qmemimmu_cycstb_i & iaddr_qmem_hit) begin`
309			state <= #1 `OR1200_QMEMFSM_FETCH;
310			`qmem_iack <= #1 1'b1;`
311			`qmem_dack <= #1 1'b0;`
312			`end`
313			`else begin`
314			state <= #1 `OR1200_QMEMFSM_IDLE;
315			`qmem_dack <= #1 1'b0;`
316			`qmem_iack <= #1 1'b0;`
317			`end`
318			`end`
319			`OR1200_QMEMFSM_LOAD: begin
320			`if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i) begin`
321			state <= #1 `OR1200_QMEMFSM_STORE;
322			`qmem_dack <= #1 1'b1;`
323			`qmem_iack <= #1 1'b0;`
324			`end`
325			`else if (qmemdmmu_cycstb_i & daddr_qmem_hit) begin`
326			state <= #1 `OR1200_QMEMFSM_LOAD;
327			`qmem_dack <= #1 1'b1;`
328			`qmem_iack <= #1 1'b0;`
329			`end`
330			`else if (qmemimmu_cycstb_i & iaddr_qmem_hit) begin`
331			state <= #1 `OR1200_QMEMFSM_FETCH;
332			`qmem_iack <= #1 1'b1;`
333			`qmem_dack <= #1 1'b0;`
334			`end`
335			`else begin`
336			state <= #1 `OR1200_QMEMFSM_IDLE;
337			`qmem_dack <= #1 1'b0;`
338			`qmem_iack <= #1 1'b0;`
339			`end`
340			`end`
341			`OR1200_QMEMFSM_FETCH: begin
342			`if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i) begin`
343			state <= #1 `OR1200_QMEMFSM_STORE;
344			`qmem_dack <= #1 1'b1;`
345			`qmem_iack <= #1 1'b0;`
346			`end`
347			`else if (qmemdmmu_cycstb_i & daddr_qmem_hit) begin`
348			state <= #1 `OR1200_QMEMFSM_LOAD;
349			`qmem_dack <= #1 1'b1;`
350			`qmem_iack <= #1 1'b0;`
351			`end`
352			`else if (qmemimmu_cycstb_i & iaddr_qmem_hit) begin`
353			state <= #1 `OR1200_QMEMFSM_FETCH;
354			`qmem_iack <= #1 1'b1;`
355			`qmem_dack <= #1 1'b0;`
356			`end`
357			`else begin`
358			state <= #1 `OR1200_QMEMFSM_IDLE;
359			`qmem_dack <= #1 1'b0;`
360			`qmem_iack <= #1 1'b0;`
361			`end`
362			`end`
363			`endcase`
364
365			`//`
366			`// Instantiation of embedded memory`
367			`//`
368			`or1200_spram_2048x32 or1200_qmem_ram(`
369			`.clk(clk),`
370			`.rst(rst),`
371			`ifdef OR1200_BIST
372			`// RAM BIST`
373			`.scanb_rst(scanb_rst),`
374			`.scanb_si(scanb_si),`
375			`.scanb_so(scanb_so),`
376			`.scanb_en(scanb_en),`
377			`.scanb_clk(scanb_clk),`
378			`endif
379			`.addr(qmem_addr[12:2]),`
380			`.ce(qmem_en),`
381			`.we(qmem_we),`
382			`.oe(1'b1),`
383			`.di(qmem_di),`
384			`.do(qmem_do)`
385			`);`
386
387			`else // OR1200_QMEM_IMPLEMENTED
388
389			`//`
390			`// QMEM and CPU/IMMU`
391			`//`
392			`assign qmemicpu_dat_o = icqmem_dat_i;`
393			`assign qmemicpu_ack_o = icqmem_ack_i;`
394			`assign qmemimmu_rty_o = icqmem_rty_i;`
395			`assign qmemimmu_err_o = icqmem_err_i;`
396			`assign qmemimmu_tag_o = icqmem_tag_i;`
397
398			`//`
399			`// QMEM and IC`
400			`//`
401			`assign icqmem_adr_o = qmemimmu_adr_i;`
402			`assign icqmem_cycstb_o = qmemimmu_cycstb_i;`
403			`assign icqmem_ci_o = qmemimmu_ci_i;`
404			`assign icqmem_sel_o = qmemicpu_sel_i;`
405			`assign icqmem_tag_o = qmemicpu_tag_i;`
406
407			`//`
408			`// QMEM and CPU/DMMU`
409			`//`
410			`assign qmemdcpu_dat_o = dcqmem_dat_i;`
411			`assign qmemdcpu_ack_o = dcqmem_ack_i;`
412			`assign qmemdcpu_rty_o = dcqmem_rty_i;`
413			`assign qmemdmmu_err_o = dcqmem_err_i;`
414			`assign qmemdmmu_tag_o = dcqmem_tag_i;`
415
416			`//`
417			`// QMEM and DC`
418			`//`
419			`assign dcqmem_adr_o = qmemdmmu_adr_i;`
420			`assign dcqmem_cycstb_o = qmemdmmu_cycstb_i;`
421			`assign dcqmem_ci_o = qmemdmmu_ci_i;`
422			`assign dcqmem_we_o = qmemdcpu_we_i;`
423			`assign dcqmem_sel_o = qmemdcpu_sel_i;`
424			`assign dcqmem_tag_o = qmemdcpu_tag_i;`
425			`assign dcqmem_dat_o = qmemdcpu_dat_i;`
426
427			`endif
428
429			`endmodule`