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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_qmem_top.v] - Blame information for rev 1219

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Embedded Memory                                    ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Embedded Memory               .                             ////
////                                                              ////
////  To Do:                                                      ////
////   - QMEM and IC/DC muxes can be removed except for cycstb    ////
////     (now are is there for easier debugging)                  ////
////   - currently arbitration is slow and stores take 2 clocks   ////
////     (final debugged version will be faster)                  ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2003 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.2.2  2003/12/09 11:46:48  simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.1.2.1  2003/07/08 15:45:26  lampret
// Added embedded memory QMEM.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
`define OR1200_QMEMFSM_IDLE     3'd0
`define OR1200_QMEMFSM_STORE    3'd1
`define OR1200_QMEMFSM_LOAD     3'd2
`define OR1200_QMEMFSM_FETCH    3'd3
 
//
// Embedded memory
//
module or1200_qmem_top(
        // Rst, clk and clock control
        clk, rst,
 
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
        // QMEM and CPU/IMMU
        qmemimmu_adr_i,
        qmemimmu_cycstb_i,
        qmemimmu_ci_i,
        qmemicpu_sel_i,
        qmemicpu_tag_i,
        qmemicpu_dat_o,
        qmemicpu_ack_o,
        qmemimmu_rty_o,
        qmemimmu_err_o,
        qmemimmu_tag_o,
 
        // QMEM and IC
        icqmem_adr_o,
        icqmem_cycstb_o,
        icqmem_ci_o,
        icqmem_sel_o,
        icqmem_tag_o,
        icqmem_dat_i,
        icqmem_ack_i,
        icqmem_rty_i,
        icqmem_err_i,
        icqmem_tag_i,
 
        // QMEM and CPU/DMMU
        qmemdmmu_adr_i,
        qmemdmmu_cycstb_i,
        qmemdmmu_ci_i,
        qmemdcpu_we_i,
        qmemdcpu_sel_i,
        qmemdcpu_tag_i,
        qmemdcpu_dat_i,
        qmemdcpu_dat_o,
        qmemdcpu_ack_o,
        qmemdcpu_rty_o,
        qmemdmmu_err_o,
        qmemdmmu_tag_o,
 
        // QMEM and DC
        dcqmem_adr_o, dcqmem_cycstb_o, dcqmem_ci_o,
        dcqmem_we_o, dcqmem_sel_o, dcqmem_tag_o, dcqmem_dat_o,
        dcqmem_dat_i, dcqmem_ack_i, dcqmem_rty_i, dcqmem_err_i, dcqmem_tag_i
 
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// QMEM and CPU/IMMU
//
input   [31:0]                   qmemimmu_adr_i;
input                           qmemimmu_cycstb_i;
input                           qmemimmu_ci_i;
input   [3:0]                    qmemicpu_sel_i;
input   [3:0]                    qmemicpu_tag_i;
output  [31:0]                   qmemicpu_dat_o;
output                          qmemicpu_ack_o;
output                          qmemimmu_rty_o;
output                          qmemimmu_err_o;
output  [3:0]                    qmemimmu_tag_o;
 
//
// QMEM and IC
//
output  [31:0]                   icqmem_adr_o;
output                          icqmem_cycstb_o;
output                          icqmem_ci_o;
output  [3:0]                    icqmem_sel_o;
output  [3:0]                    icqmem_tag_o;
input   [31:0]                   icqmem_dat_i;
input                           icqmem_ack_i;
input                           icqmem_rty_i;
input                           icqmem_err_i;
input   [3:0]                    icqmem_tag_i;
 
//
// QMEM and CPU/DMMU
//
input   [31:0]                   qmemdmmu_adr_i;
input                           qmemdmmu_cycstb_i;
input                           qmemdmmu_ci_i;
input                           qmemdcpu_we_i;
input   [3:0]                    qmemdcpu_sel_i;
input   [3:0]                    qmemdcpu_tag_i;
input   [31:0]                   qmemdcpu_dat_i;
output  [31:0]                   qmemdcpu_dat_o;
output                          qmemdcpu_ack_o;
output                          qmemdcpu_rty_o;
output                          qmemdmmu_err_o;
output  [3:0]                    qmemdmmu_tag_o;
 
//
// QMEM and DC
//
output  [31:0]                   dcqmem_adr_o;
output                          dcqmem_cycstb_o;
output                          dcqmem_ci_o;
output                          dcqmem_we_o;
output  [3:0]                    dcqmem_sel_o;
output  [3:0]                    dcqmem_tag_o;
output  [dw-1:0]         dcqmem_dat_o;
input   [dw-1:0]         dcqmem_dat_i;
input                           dcqmem_ack_i;
input                           dcqmem_rty_i;
input                           dcqmem_err_i;
input   [3:0]                    dcqmem_tag_i;
 
`ifdef OR1200_QMEM_IMPLEMENTED
 
//
// Internal regs and wires
//
wire                            iaddr_qmem_hit;
wire                            daddr_qmem_hit;
reg     [2:0]                    state;
reg                             qmem_dack;
reg                             qmem_iack;
wire    [31:0]                   qmem_di;
wire    [31:0]                   qmem_do;
wire                            qmem_en;
wire                            qmem_we;
wire    [31:0]                   qmem_addr;
 
//
// QMEM and CPU/IMMU
//
assign qmemicpu_dat_o = qmem_iack ? qmem_do : icqmem_dat_i;
assign qmemicpu_ack_o = qmem_iack ? 1'b1 : icqmem_ack_i;
assign qmemimmu_rty_o = qmem_iack ? 1'b0 : icqmem_rty_i;
assign qmemimmu_err_o = qmem_iack ? 1'b0 : icqmem_err_i;
assign qmemimmu_tag_o = qmem_iack ? 4'h0 : icqmem_tag_i;
 
//
// QMEM and IC
//
assign icqmem_adr_o = iaddr_qmem_hit ? 32'h0000_0000 : qmemimmu_adr_i;
assign icqmem_cycstb_o = iaddr_qmem_hit ? 1'b0 : qmemimmu_cycstb_i;
assign icqmem_ci_o = iaddr_qmem_hit ? 1'b0 : qmemimmu_ci_i;
assign icqmem_sel_o = iaddr_qmem_hit ? 4'h0 : qmemicpu_sel_i;
assign icqmem_tag_o = iaddr_qmem_hit ? 4'h0 : qmemicpu_tag_i;
 
//
// QMEM and CPU/DMMU
//
assign qmemdcpu_dat_o = daddr_qmem_hit ? qmem_do : dcqmem_dat_i;
assign qmemdcpu_ack_o = daddr_qmem_hit ? qmem_dack : dcqmem_ack_i;
assign qmemdcpu_rty_o = daddr_qmem_hit ? 1'b0 : dcqmem_rty_i;
assign qmemdmmu_err_o = daddr_qmem_hit ? 1'b0 : dcqmem_err_i;
assign qmemdmmu_tag_o = daddr_qmem_hit ? 4'h0 : dcqmem_tag_i;
 
//
// QMEM and DC
//
assign dcqmem_adr_o = daddr_qmem_hit ? 32'h0000_0000 : qmemdmmu_adr_i;
assign dcqmem_cycstb_o = daddr_qmem_hit ? 1'b0 : qmemdmmu_cycstb_i;
assign dcqmem_ci_o = daddr_qmem_hit ? 1'b0 : qmemdmmu_ci_i;
assign dcqmem_we_o = daddr_qmem_hit ? 1'b0 : qmemdcpu_we_i;
assign dcqmem_sel_o = daddr_qmem_hit ? 4'h0 : qmemdcpu_sel_i;
assign dcqmem_tag_o = daddr_qmem_hit ? 4'h0 : qmemdcpu_tag_i;
assign dcqmem_dat_o = daddr_qmem_hit ? 32'h0000_0000 : qmemdcpu_dat_i;
 
//
// Address comparison whether QMEM was hit
//
assign iaddr_qmem_hit = (qmemimmu_adr_i & `OR1200_QMEM_MASK) == `OR1200_QMEM_ADDR;
assign daddr_qmem_hit = (qmemdmmu_adr_i & `OR1200_QMEM_MASK) == `OR1200_QMEM_ADDR;
 
//
//
//
assign qmem_en = iaddr_qmem_hit & qmemimmu_cycstb_i | daddr_qmem_hit & qmemdmmu_cycstb_i;
assign qmem_we = qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i;
assign qmem_di = qmemdcpu_dat_i;
assign qmem_addr = (qmemdmmu_cycstb_i & daddr_qmem_hit) ? qmemdmmu_adr_i : qmemimmu_adr_i;
 
//
// QMEM control FSM
//
always @(posedge rst or posedge clk)
        if (rst) begin
                state <= #1 `OR1200_QMEMFSM_IDLE;
                qmem_dack <= #1 1'b0;
                qmem_iack <= #1 1'b0;
        end
        else case (state)       // synopsys parallel_case
                `OR1200_QMEMFSM_IDLE: begin
                        if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i) begin
                                state <= #1 `OR1200_QMEMFSM_STORE;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemdmmu_cycstb_i & daddr_qmem_hit) begin
                                state <= #1 `OR1200_QMEMFSM_LOAD;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemimmu_cycstb_i & iaddr_qmem_hit) begin
                                state <= #1 `OR1200_QMEMFSM_FETCH;
                                qmem_iack <= #1 1'b1;
                                qmem_dack <= #1 1'b0;
                        end
                end
                `OR1200_QMEMFSM_STORE: begin
                        if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i) begin
                                state <= #1 `OR1200_QMEMFSM_STORE;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemdmmu_cycstb_i & daddr_qmem_hit) begin
                                state <= #1 `OR1200_QMEMFSM_LOAD;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemimmu_cycstb_i & iaddr_qmem_hit) begin
                                state <= #1 `OR1200_QMEMFSM_FETCH;
                                qmem_iack <= #1 1'b1;
                                qmem_dack <= #1 1'b0;
                        end
                        else begin
                                state <= #1 `OR1200_QMEMFSM_IDLE;
                                qmem_dack <= #1 1'b0;
                                qmem_iack <= #1 1'b0;
                        end
                end
                `OR1200_QMEMFSM_LOAD: begin
                        if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i) begin
                                state <= #1 `OR1200_QMEMFSM_STORE;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemdmmu_cycstb_i & daddr_qmem_hit) begin
                                state <= #1 `OR1200_QMEMFSM_LOAD;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemimmu_cycstb_i & iaddr_qmem_hit) begin
                                state <= #1 `OR1200_QMEMFSM_FETCH;
                                qmem_iack <= #1 1'b1;
                                qmem_dack <= #1 1'b0;
                        end
                        else begin
                                state <= #1 `OR1200_QMEMFSM_IDLE;
                                qmem_dack <= #1 1'b0;
                                qmem_iack <= #1 1'b0;
                        end
                end
                `OR1200_QMEMFSM_FETCH: begin
                        if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i) begin
                                state <= #1 `OR1200_QMEMFSM_STORE;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemdmmu_cycstb_i & daddr_qmem_hit) begin
                                state <= #1 `OR1200_QMEMFSM_LOAD;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemimmu_cycstb_i & iaddr_qmem_hit) begin
                                state <= #1 `OR1200_QMEMFSM_FETCH;
                                qmem_iack <= #1 1'b1;
                                qmem_dack <= #1 1'b0;
                        end
                        else begin
                                state <= #1 `OR1200_QMEMFSM_IDLE;
                                qmem_dack <= #1 1'b0;
                                qmem_iack <= #1 1'b0;
                        end
                end
        endcase
 
//
// Instantiation of embedded memory
//
or1200_spram_2048x32 or1200_qmem_ram(
        .clk(clk),
        .rst(rst),
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .addr(qmem_addr[12:2]),
        .ce(qmem_en),
        .we(qmem_we),
        .oe(1'b1),
        .di(qmem_di),
        .do(qmem_do)
);
 
`else  // OR1200_QMEM_IMPLEMENTED
 
//
// QMEM and CPU/IMMU
//
assign qmemicpu_dat_o = icqmem_dat_i;
assign qmemicpu_ack_o = icqmem_ack_i;
assign qmemimmu_rty_o = icqmem_rty_i;
assign qmemimmu_err_o = icqmem_err_i;
assign qmemimmu_tag_o = icqmem_tag_i;
 
//
// QMEM and IC
//
assign icqmem_adr_o = qmemimmu_adr_i;
assign icqmem_cycstb_o = qmemimmu_cycstb_i;
assign icqmem_ci_o = qmemimmu_ci_i;
assign icqmem_sel_o = qmemicpu_sel_i;
assign icqmem_tag_o = qmemicpu_tag_i;
 
//
// QMEM and CPU/DMMU
//
assign qmemdcpu_dat_o = dcqmem_dat_i;
assign qmemdcpu_ack_o = dcqmem_ack_i;
assign qmemdcpu_rty_o = dcqmem_rty_i;
assign qmemdmmu_err_o = dcqmem_err_i;
assign qmemdmmu_tag_o = dcqmem_tag_i;
 
//
// QMEM and DC
//
assign dcqmem_adr_o = qmemdmmu_adr_i;
assign dcqmem_cycstb_o = qmemdmmu_cycstb_i;
assign dcqmem_ci_o = qmemdmmu_ci_i;
assign dcqmem_we_o = qmemdcpu_we_i;
assign dcqmem_sel_o = qmemdcpu_sel_i;
assign dcqmem_tag_o = qmemdcpu_tag_i;
assign dcqmem_dat_o = qmemdcpu_dat_i;
 
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
 
`endif
 
endmodule

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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_qmem_top.v] - Blame information for rev 1219

Line No.	Rev	Author	Line
1	1172	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Embedded Memory ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Embedded Memory . ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - QMEM and IC/DC muxes can be removed except for cycstb ////`
13			`//// (now are is there for easier debugging) ////`
14			`//// - currently arbitration is slow and stores take 2 clocks ////`
15			`//// (final debugged version will be faster) ////`
16			`//// ////`
17			`//// Author(s): ////`
18			`//// - Damjan Lampret, lampret@opencores.org ////`
19			`//// ////`
20			`//////////////////////////////////////////////////////////////////////`
21			`//// ////`
22			`//// Copyright (C) 2003 Authors and OPENCORES.ORG ////`
23			`//// ////`
24			`//// This source file may be used and distributed without ////`
25			`//// restriction provided that this copyright statement is not ////`
26			`//// removed from the file and that any derivative work contains ////`
27			`//// the original copyright notice and the associated disclaimer. ////`
28			`//// ////`
29			`//// This source file is free software; you can redistribute it ////`
30			`//// and/or modify it under the terms of the GNU Lesser General ////`
31			`//// Public License as published by the Free Software Foundation; ////`
32			`//// either version 2.1 of the License, or (at your option) any ////`
33			`//// later version. ////`
34			`//// ////`
35			`//// This source is distributed in the hope that it will be ////`
36			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
37			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
38			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
39			`//// details. ////`
40			`//// ////`
41			`//// You should have received a copy of the GNU Lesser General ////`
42			`//// Public License along with this source; if not, download it ////`
43			`//// from http://www.opencores.org/lgpl.shtml ////`
44			`//// ////`
45			`//////////////////////////////////////////////////////////////////////`
46			`//`
47			`// CVS Revision History`
48			`//`
49			`// $Log: not supported by cvs2svn $`
50	1219	simons	`// Revision 1.1.2.2 2003/12/09 11:46:48 simons`
51			`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`
52			`//`
53	1214	simons	`// Revision 1.1.2.1 2003/07/08 15:45:26 lampret`
54			`// Added embedded memory QMEM.`
55	1172	lampret	`//`
56	1214	simons	`//`
57	1172	lampret
58			`// synopsys translate_off`
59			`include "timescale.v"
60			`// synopsys translate_on`
61			`include "or1200_defines.v"
62
63			`define OR1200_QMEMFSM_IDLE 3'd0
64			`define OR1200_QMEMFSM_STORE 3'd1
65			`define OR1200_QMEMFSM_LOAD 3'd2
66			`define OR1200_QMEMFSM_FETCH 3'd3
67
68			`//`
69			`// Embedded memory`
70			`//`
71			`module or1200_qmem_top(`
72			`// Rst, clk and clock control`
73			`clk, rst,`
74
75			`ifdef OR1200_BIST
76			`// RAM BIST`
77	1214	simons	`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
78	1172	lampret	`endif
79
80			`// QMEM and CPU/IMMU`
81			`qmemimmu_adr_i,`
82			`qmemimmu_cycstb_i,`
83			`qmemimmu_ci_i,`
84			`qmemicpu_sel_i,`
85			`qmemicpu_tag_i,`
86			`qmemicpu_dat_o,`
87			`qmemicpu_ack_o,`
88			`qmemimmu_rty_o,`
89			`qmemimmu_err_o,`
90			`qmemimmu_tag_o,`
91
92			`// QMEM and IC`
93			`icqmem_adr_o,`
94			`icqmem_cycstb_o,`
95			`icqmem_ci_o,`
96			`icqmem_sel_o,`
97			`icqmem_tag_o,`
98			`icqmem_dat_i,`
99			`icqmem_ack_i,`
100			`icqmem_rty_i,`
101			`icqmem_err_i,`
102			`icqmem_tag_i,`
103
104			`// QMEM and CPU/DMMU`
105			`qmemdmmu_adr_i,`
106			`qmemdmmu_cycstb_i,`
107			`qmemdmmu_ci_i,`
108			`qmemdcpu_we_i,`
109			`qmemdcpu_sel_i,`
110			`qmemdcpu_tag_i,`
111			`qmemdcpu_dat_i,`
112			`qmemdcpu_dat_o,`
113			`qmemdcpu_ack_o,`
114			`qmemdcpu_rty_o,`
115			`qmemdmmu_err_o,`
116			`qmemdmmu_tag_o,`
117
118			`// QMEM and DC`
119			`dcqmem_adr_o, dcqmem_cycstb_o, dcqmem_ci_o,`
120			`dcqmem_we_o, dcqmem_sel_o, dcqmem_tag_o, dcqmem_dat_o,`
121			`dcqmem_dat_i, dcqmem_ack_i, dcqmem_rty_i, dcqmem_err_i, dcqmem_tag_i`
122
123			`);`
124
125			parameter dw = `OR1200_OPERAND_WIDTH;
126
127			`//`
128			`// I/O`
129			`//`
130
131			`//`
132			`// Clock and reset`
133			`//`
134			`input clk;`
135			`input rst;`
136
137			`ifdef OR1200_BIST
138			`//`
139			`// RAM BIST`
140			`//`
141	1214	simons	`input mbist_si_i;`
142			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
143			`output mbist_so_o;`
144	1172	lampret	`endif
145
146			`//`
147			`// QMEM and CPU/IMMU`
148			`//`
149			`input [31:0] qmemimmu_adr_i;`
150			`input qmemimmu_cycstb_i;`
151			`input qmemimmu_ci_i;`
152			`input [3:0] qmemicpu_sel_i;`
153			`input [3:0] qmemicpu_tag_i;`
154			`output [31:0] qmemicpu_dat_o;`
155			`output qmemicpu_ack_o;`
156			`output qmemimmu_rty_o;`
157			`output qmemimmu_err_o;`
158			`output [3:0] qmemimmu_tag_o;`
159
160			`//`
161			`// QMEM and IC`
162			`//`
163			`output [31:0] icqmem_adr_o;`
164			`output icqmem_cycstb_o;`
165			`output icqmem_ci_o;`
166			`output [3:0] icqmem_sel_o;`
167			`output [3:0] icqmem_tag_o;`
168			`input [31:0] icqmem_dat_i;`
169			`input icqmem_ack_i;`
170			`input icqmem_rty_i;`
171			`input icqmem_err_i;`
172			`input [3:0] icqmem_tag_i;`
173
174			`//`
175			`// QMEM and CPU/DMMU`
176			`//`
177			`input [31:0] qmemdmmu_adr_i;`
178			`input qmemdmmu_cycstb_i;`
179			`input qmemdmmu_ci_i;`
180			`input qmemdcpu_we_i;`
181			`input [3:0] qmemdcpu_sel_i;`
182			`input [3:0] qmemdcpu_tag_i;`
183			`input [31:0] qmemdcpu_dat_i;`
184			`output [31:0] qmemdcpu_dat_o;`
185			`output qmemdcpu_ack_o;`
186			`output qmemdcpu_rty_o;`
187			`output qmemdmmu_err_o;`
188			`output [3:0] qmemdmmu_tag_o;`
189
190			`//`
191			`// QMEM and DC`
192			`//`
193			`output [31:0] dcqmem_adr_o;`
194			`output dcqmem_cycstb_o;`
195			`output dcqmem_ci_o;`
196			`output dcqmem_we_o;`
197			`output [3:0] dcqmem_sel_o;`
198			`output [3:0] dcqmem_tag_o;`
199			`output [dw-1:0] dcqmem_dat_o;`
200			`input [dw-1:0] dcqmem_dat_i;`
201			`input dcqmem_ack_i;`
202			`input dcqmem_rty_i;`
203			`input dcqmem_err_i;`
204			`input [3:0] dcqmem_tag_i;`
205
206			`ifdef OR1200_QMEM_IMPLEMENTED
207
208			`//`
209			`// Internal regs and wires`
210			`//`
211			`wire iaddr_qmem_hit;`
212			`wire daddr_qmem_hit;`
213			`reg [2:0] state;`
214			`reg qmem_dack;`
215			`reg qmem_iack;`
216			`wire [31:0] qmem_di;`
217			`wire [31:0] qmem_do;`
218			`wire qmem_en;`
219			`wire qmem_we;`
220			`wire [31:0] qmem_addr;`
221
222			`//`
223			`// QMEM and CPU/IMMU`
224			`//`
225			`assign qmemicpu_dat_o = qmem_iack ? qmem_do : icqmem_dat_i;`
226			`assign qmemicpu_ack_o = qmem_iack ? 1'b1 : icqmem_ack_i;`
227			`assign qmemimmu_rty_o = qmem_iack ? 1'b0 : icqmem_rty_i;`
228			`assign qmemimmu_err_o = qmem_iack ? 1'b0 : icqmem_err_i;`
229			`assign qmemimmu_tag_o = qmem_iack ? 4'h0 : icqmem_tag_i;`
230
231			`//`
232			`// QMEM and IC`
233			`//`
234			`assign icqmem_adr_o = iaddr_qmem_hit ? 32'h0000_0000 : qmemimmu_adr_i;`
235			`assign icqmem_cycstb_o = iaddr_qmem_hit ? 1'b0 : qmemimmu_cycstb_i;`
236			`assign icqmem_ci_o = iaddr_qmem_hit ? 1'b0 : qmemimmu_ci_i;`
237			`assign icqmem_sel_o = iaddr_qmem_hit ? 4'h0 : qmemicpu_sel_i;`
238			`assign icqmem_tag_o = iaddr_qmem_hit ? 4'h0 : qmemicpu_tag_i;`
239
240			`//`
241			`// QMEM and CPU/DMMU`
242			`//`
243			`assign qmemdcpu_dat_o = daddr_qmem_hit ? qmem_do : dcqmem_dat_i;`
244			`assign qmemdcpu_ack_o = daddr_qmem_hit ? qmem_dack : dcqmem_ack_i;`
245			`assign qmemdcpu_rty_o = daddr_qmem_hit ? 1'b0 : dcqmem_rty_i;`
246			`assign qmemdmmu_err_o = daddr_qmem_hit ? 1'b0 : dcqmem_err_i;`
247			`assign qmemdmmu_tag_o = daddr_qmem_hit ? 4'h0 : dcqmem_tag_i;`
248
249			`//`
250			`// QMEM and DC`
251			`//`
252			`assign dcqmem_adr_o = daddr_qmem_hit ? 32'h0000_0000 : qmemdmmu_adr_i;`
253			`assign dcqmem_cycstb_o = daddr_qmem_hit ? 1'b0 : qmemdmmu_cycstb_i;`
254			`assign dcqmem_ci_o = daddr_qmem_hit ? 1'b0 : qmemdmmu_ci_i;`
255			`assign dcqmem_we_o = daddr_qmem_hit ? 1'b0 : qmemdcpu_we_i;`
256			`assign dcqmem_sel_o = daddr_qmem_hit ? 4'h0 : qmemdcpu_sel_i;`
257			`assign dcqmem_tag_o = daddr_qmem_hit ? 4'h0 : qmemdcpu_tag_i;`
258			`assign dcqmem_dat_o = daddr_qmem_hit ? 32'h0000_0000 : qmemdcpu_dat_i;`
259
260			`//`
261			`// Address comparison whether QMEM was hit`
262			`//`
263			assign iaddr_qmem_hit = (qmemimmu_adr_i & `OR1200_QMEM_MASK) == `OR1200_QMEM_ADDR;
264			assign daddr_qmem_hit = (qmemdmmu_adr_i & `OR1200_QMEM_MASK) == `OR1200_QMEM_ADDR;
265
266			`//`
267			`//`
268			`//`
269			`assign qmem_en = iaddr_qmem_hit & qmemimmu_cycstb_i \| daddr_qmem_hit & qmemdmmu_cycstb_i;`
270			`assign qmem_we = qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i;`
271			`assign qmem_di = qmemdcpu_dat_i;`
272			`assign qmem_addr = (qmemdmmu_cycstb_i & daddr_qmem_hit) ? qmemdmmu_adr_i : qmemimmu_adr_i;`
273
274			`//`
275			`// QMEM control FSM`
276			`//`
277			`always @(posedge rst or posedge clk)`
278			`if (rst) begin`
279			state <= #1 `OR1200_QMEMFSM_IDLE;
280			`qmem_dack <= #1 1'b0;`
281			`qmem_iack <= #1 1'b0;`
282			`end`
283			`else case (state) // synopsys parallel_case`
284			`OR1200_QMEMFSM_IDLE: begin
285			`if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i) begin`
286			state <= #1 `OR1200_QMEMFSM_STORE;
287			`qmem_dack <= #1 1'b1;`
288			`qmem_iack <= #1 1'b0;`
289			`end`
290			`else if (qmemdmmu_cycstb_i & daddr_qmem_hit) begin`
291			state <= #1 `OR1200_QMEMFSM_LOAD;
292			`qmem_dack <= #1 1'b1;`
293			`qmem_iack <= #1 1'b0;`
294			`end`
295			`else if (qmemimmu_cycstb_i & iaddr_qmem_hit) begin`
296			state <= #1 `OR1200_QMEMFSM_FETCH;
297			`qmem_iack <= #1 1'b1;`
298			`qmem_dack <= #1 1'b0;`
299			`end`
300			`end`
301			`OR1200_QMEMFSM_STORE: begin
302			`if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i) begin`
303			state <= #1 `OR1200_QMEMFSM_STORE;
304			`qmem_dack <= #1 1'b1;`
305			`qmem_iack <= #1 1'b0;`
306			`end`
307			`else if (qmemdmmu_cycstb_i & daddr_qmem_hit) begin`
308			state <= #1 `OR1200_QMEMFSM_LOAD;
309			`qmem_dack <= #1 1'b1;`
310			`qmem_iack <= #1 1'b0;`
311			`end`
312			`else if (qmemimmu_cycstb_i & iaddr_qmem_hit) begin`
313			state <= #1 `OR1200_QMEMFSM_FETCH;
314			`qmem_iack <= #1 1'b1;`
315			`qmem_dack <= #1 1'b0;`
316			`end`
317			`else begin`
318			state <= #1 `OR1200_QMEMFSM_IDLE;
319			`qmem_dack <= #1 1'b0;`
320			`qmem_iack <= #1 1'b0;`
321			`end`
322			`end`
323			`OR1200_QMEMFSM_LOAD: begin
324			`if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i) begin`
325			state <= #1 `OR1200_QMEMFSM_STORE;
326			`qmem_dack <= #1 1'b1;`
327			`qmem_iack <= #1 1'b0;`
328			`end`
329			`else if (qmemdmmu_cycstb_i & daddr_qmem_hit) begin`
330			state <= #1 `OR1200_QMEMFSM_LOAD;
331			`qmem_dack <= #1 1'b1;`
332			`qmem_iack <= #1 1'b0;`
333			`end`
334			`else if (qmemimmu_cycstb_i & iaddr_qmem_hit) begin`
335			state <= #1 `OR1200_QMEMFSM_FETCH;
336			`qmem_iack <= #1 1'b1;`
337			`qmem_dack <= #1 1'b0;`
338			`end`
339			`else begin`
340			state <= #1 `OR1200_QMEMFSM_IDLE;
341			`qmem_dack <= #1 1'b0;`
342			`qmem_iack <= #1 1'b0;`
343			`end`
344			`end`
345			`OR1200_QMEMFSM_FETCH: begin
346			`if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i) begin`
347			state <= #1 `OR1200_QMEMFSM_STORE;
348			`qmem_dack <= #1 1'b1;`
349			`qmem_iack <= #1 1'b0;`
350			`end`
351			`else if (qmemdmmu_cycstb_i & daddr_qmem_hit) begin`
352			state <= #1 `OR1200_QMEMFSM_LOAD;
353			`qmem_dack <= #1 1'b1;`
354			`qmem_iack <= #1 1'b0;`
355			`end`
356			`else if (qmemimmu_cycstb_i & iaddr_qmem_hit) begin`
357			state <= #1 `OR1200_QMEMFSM_FETCH;
358			`qmem_iack <= #1 1'b1;`
359			`qmem_dack <= #1 1'b0;`
360			`end`
361			`else begin`
362			state <= #1 `OR1200_QMEMFSM_IDLE;
363			`qmem_dack <= #1 1'b0;`
364			`qmem_iack <= #1 1'b0;`
365			`end`
366			`end`
367			`endcase`
368
369			`//`
370			`// Instantiation of embedded memory`
371			`//`
372			`or1200_spram_2048x32 or1200_qmem_ram(`
373			`.clk(clk),`
374			`.rst(rst),`
375			`ifdef OR1200_BIST
376			`// RAM BIST`
377	1214	simons	`.mbist_si_i(mbist_si_i),`
378			`.mbist_so_o(mbist_so_o),`
379			`.mbist_ctrl_i(mbist_ctrl_i),`
380	1172	lampret	`endif
381			`.addr(qmem_addr[12:2]),`
382			`.ce(qmem_en),`
383			`.we(qmem_we),`
384			`.oe(1'b1),`
385			`.di(qmem_di),`
386			`.do(qmem_do)`
387			`);`
388
389			`else // OR1200_QMEM_IMPLEMENTED
390
391			`//`
392			`// QMEM and CPU/IMMU`
393			`//`
394			`assign qmemicpu_dat_o = icqmem_dat_i;`
395			`assign qmemicpu_ack_o = icqmem_ack_i;`
396			`assign qmemimmu_rty_o = icqmem_rty_i;`
397			`assign qmemimmu_err_o = icqmem_err_i;`
398			`assign qmemimmu_tag_o = icqmem_tag_i;`
399
400			`//`
401			`// QMEM and IC`
402			`//`
403			`assign icqmem_adr_o = qmemimmu_adr_i;`
404			`assign icqmem_cycstb_o = qmemimmu_cycstb_i;`
405			`assign icqmem_ci_o = qmemimmu_ci_i;`
406			`assign icqmem_sel_o = qmemicpu_sel_i;`
407			`assign icqmem_tag_o = qmemicpu_tag_i;`
408
409			`//`
410			`// QMEM and CPU/DMMU`
411			`//`
412			`assign qmemdcpu_dat_o = dcqmem_dat_i;`
413			`assign qmemdcpu_ack_o = dcqmem_ack_i;`
414			`assign qmemdcpu_rty_o = dcqmem_rty_i;`
415			`assign qmemdmmu_err_o = dcqmem_err_i;`
416			`assign qmemdmmu_tag_o = dcqmem_tag_i;`
417
418			`//`
419			`// QMEM and DC`
420			`//`
421			`assign dcqmem_adr_o = qmemdmmu_adr_i;`
422			`assign dcqmem_cycstb_o = qmemdmmu_cycstb_i;`
423			`assign dcqmem_ci_o = qmemdmmu_ci_i;`
424			`assign dcqmem_we_o = qmemdcpu_we_i;`
425			`assign dcqmem_sel_o = qmemdcpu_sel_i;`
426			`assign dcqmem_tag_o = qmemdcpu_tag_i;`
427			`assign dcqmem_dat_o = qmemdcpu_dat_i;`
428
429	1219	simons	`ifdef OR1200_BIST
430			`assign mbist_so_o = mbist_si_i;`
431	1172	lampret	`endif
432
433	1219	simons	`endif
434
435	1172	lampret	`endmodule`