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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Embedded Memory                                    ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Embedded Memory               .                             ////
////                                                              ////
////  To Do:                                                      ////
////   - QMEM and IC/DC muxes can be removed except for cycstb    ////
////     (now are is there for easier debugging)                  ////
////   - currently arbitration is slow and stores take 2 clocks   ////
////     (final debugged version will be faster)                  ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2003 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.2.3  2003/12/17 13:36:58  simons
// Qmem mbist signals fixed.
//
// Revision 1.1.2.2  2003/12/09 11:46:48  simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.1.2.1  2003/07/08 15:45:26  lampret
// Added embedded memory QMEM.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
`define OR1200_QMEMFSM_IDLE     3'd0
`define OR1200_QMEMFSM_STORE    3'd1
`define OR1200_QMEMFSM_LOAD     3'd2
`define OR1200_QMEMFSM_FETCH    3'd3
 
//
// Embedded memory
//
module or1200_qmem_top(
        // Rst, clk and clock control
        clk, rst,
 
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
        // QMEM and CPU/IMMU
        qmemimmu_adr_i,
        qmemimmu_cycstb_i,
        qmemimmu_ci_i,
        qmemicpu_sel_i,
        qmemicpu_tag_i,
        qmemicpu_dat_o,
        qmemicpu_ack_o,
        qmemimmu_rty_o,
        qmemimmu_err_o,
        qmemimmu_tag_o,
 
        // QMEM and IC
        icqmem_adr_o,
        icqmem_cycstb_o,
        icqmem_ci_o,
        icqmem_sel_o,
        icqmem_tag_o,
        icqmem_dat_i,
        icqmem_ack_i,
        icqmem_rty_i,
        icqmem_err_i,
        icqmem_tag_i,
 
        // QMEM and CPU/DMMU
        qmemdmmu_adr_i,
        qmemdmmu_cycstb_i,
        qmemdmmu_ci_i,
        qmemdcpu_we_i,
        qmemdcpu_sel_i,
        qmemdcpu_tag_i,
        qmemdcpu_dat_i,
        qmemdcpu_dat_o,
        qmemdcpu_ack_o,
        qmemdcpu_rty_o,
        qmemdmmu_err_o,
        qmemdmmu_tag_o,
 
        // QMEM and DC
        dcqmem_adr_o, dcqmem_cycstb_o, dcqmem_ci_o,
        dcqmem_we_o, dcqmem_sel_o, dcqmem_tag_o, dcqmem_dat_o,
        dcqmem_dat_i, dcqmem_ack_i, dcqmem_rty_i, dcqmem_err_i, dcqmem_tag_i
 
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// QMEM and CPU/IMMU
//
input   [31:0]                   qmemimmu_adr_i;
input                           qmemimmu_cycstb_i;
input                           qmemimmu_ci_i;
input   [3:0]                    qmemicpu_sel_i;
input   [3:0]                    qmemicpu_tag_i;
output  [31:0]                   qmemicpu_dat_o;
output                          qmemicpu_ack_o;
output                          qmemimmu_rty_o;
output                          qmemimmu_err_o;
output  [3:0]                    qmemimmu_tag_o;
 
//
// QMEM and IC
//
output  [31:0]                   icqmem_adr_o;
output                          icqmem_cycstb_o;
output                          icqmem_ci_o;
output  [3:0]                    icqmem_sel_o;
output  [3:0]                    icqmem_tag_o;
input   [31:0]                   icqmem_dat_i;
input                           icqmem_ack_i;
input                           icqmem_rty_i;
input                           icqmem_err_i;
input   [3:0]                    icqmem_tag_i;
 
//
// QMEM and CPU/DMMU
//
input   [31:0]                   qmemdmmu_adr_i;
input                           qmemdmmu_cycstb_i;
input                           qmemdmmu_ci_i;
input                           qmemdcpu_we_i;
input   [3:0]                    qmemdcpu_sel_i;
input   [3:0]                    qmemdcpu_tag_i;
input   [31:0]                   qmemdcpu_dat_i;
output  [31:0]                   qmemdcpu_dat_o;
output                          qmemdcpu_ack_o;
output                          qmemdcpu_rty_o;
output                          qmemdmmu_err_o;
output  [3:0]                    qmemdmmu_tag_o;
 
//
// QMEM and DC
//
output  [31:0]                   dcqmem_adr_o;
output                          dcqmem_cycstb_o;
output                          dcqmem_ci_o;
output                          dcqmem_we_o;
output  [3:0]                    dcqmem_sel_o;
output  [3:0]                    dcqmem_tag_o;
output  [dw-1:0]         dcqmem_dat_o;
input   [dw-1:0]         dcqmem_dat_i;
input                           dcqmem_ack_i;
input                           dcqmem_rty_i;
input                           dcqmem_err_i;
input   [3:0]                    dcqmem_tag_i;
 
`ifdef OR1200_QMEM_IMPLEMENTED
 
//
// Internal regs and wires
//
wire                            iaddr_qmem_hit;
wire                            daddr_qmem_hit;
reg     [2:0]                    state;
reg                             qmem_dack;
reg                             qmem_iack;
wire    [31:0]                   qmem_di;
wire    [31:0]                   qmem_do;
wire                            qmem_en;
wire                            qmem_we;
`ifdef OR1200_QMEM_BSEL
wire  [3:0]       qmem_sel;
`endif
wire    [31:0]                   qmem_addr;
`ifdef OR1200_QMEM_ACK
wire              qmem_ack;
`else
wire              qmem_ack = 1'b1;
`endif
 
//
// QMEM and CPU/IMMU
//
assign qmemicpu_dat_o = qmem_iack ? qmem_do : icqmem_dat_i;
assign qmemicpu_ack_o = qmem_iack ? 1'b1 : icqmem_ack_i;
assign qmemimmu_rty_o = qmem_iack ? 1'b0 : icqmem_rty_i;
assign qmemimmu_err_o = qmem_iack ? 1'b0 : icqmem_err_i;
assign qmemimmu_tag_o = qmem_iack ? 4'h0 : icqmem_tag_i;
 
//
// QMEM and IC
//
assign icqmem_adr_o = iaddr_qmem_hit ? 32'h0000_0000 : qmemimmu_adr_i;
assign icqmem_cycstb_o = iaddr_qmem_hit ? 1'b0 : qmemimmu_cycstb_i;
assign icqmem_ci_o = iaddr_qmem_hit ? 1'b0 : qmemimmu_ci_i;
assign icqmem_sel_o = iaddr_qmem_hit ? 4'h0 : qmemicpu_sel_i;
assign icqmem_tag_o = iaddr_qmem_hit ? 4'h0 : qmemicpu_tag_i;
 
//
// QMEM and CPU/DMMU
//
assign qmemdcpu_dat_o = daddr_qmem_hit ? qmem_do : dcqmem_dat_i;
assign qmemdcpu_ack_o = daddr_qmem_hit ? qmem_dack : dcqmem_ack_i;
assign qmemdcpu_rty_o = daddr_qmem_hit ? ~qmem_dack : dcqmem_rty_i;
assign qmemdmmu_err_o = daddr_qmem_hit ? 1'b0 : dcqmem_err_i;
assign qmemdmmu_tag_o = daddr_qmem_hit ? 4'h0 : dcqmem_tag_i;
 
//
// QMEM and DC
//
assign dcqmem_adr_o = daddr_qmem_hit ? 32'h0000_0000 : qmemdmmu_adr_i;
assign dcqmem_cycstb_o = daddr_qmem_hit ? 1'b0 : qmemdmmu_cycstb_i;
assign dcqmem_ci_o = daddr_qmem_hit ? 1'b0 : qmemdmmu_ci_i;
assign dcqmem_we_o = daddr_qmem_hit ? 1'b0 : qmemdcpu_we_i;
assign dcqmem_sel_o = daddr_qmem_hit ? 4'h0 : qmemdcpu_sel_i;
assign dcqmem_tag_o = daddr_qmem_hit ? 4'h0 : qmemdcpu_tag_i;
assign dcqmem_dat_o = daddr_qmem_hit ? 32'h0000_0000 : qmemdcpu_dat_i;
 
//
// Address comparison whether QMEM was hit
//
`ifdef OR1200_QMEM_IADDR
assign iaddr_qmem_hit = (qmemimmu_adr_i & `OR1200_QMEM_IMASK) == `OR1200_QMEM_IADDR;
`else
assign iaddr_qmem_hit = 1'b0;
`endif
 
`ifdef OR1200_QMEM_DADDR
assign daddr_qmem_hit = (qmemdmmu_adr_i & `OR1200_QMEM_DMASK) == `OR1200_QMEM_DADDR;
`else
assign daddr_qmem_hit = 1'b0;
`endif
 
//
//
//
assign qmem_en = iaddr_qmem_hit & qmemimmu_cycstb_i | daddr_qmem_hit & qmemdmmu_cycstb_i;
assign qmem_we = qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i;
`ifdef OR1200_QMEM_BSEL
assign qmem_sel = (qmemdmmu_cycstb_i & daddr_qmem_hit) ? qmemdcpu_sel_i : qmemicpu_sel_i;
`endif
assign qmem_di = qmemdcpu_dat_i;
assign qmem_addr = (qmemdmmu_cycstb_i & daddr_qmem_hit) ? qmemdmmu_adr_i : qmemimmu_adr_i;
 
//
// QMEM control FSM
//
always @(posedge rst or posedge clk)
        if (rst) begin
                state <= #1 `OR1200_QMEMFSM_IDLE;
                qmem_dack <= #1 1'b0;
                qmem_iack <= #1 1'b0;
        end
        else case (state)       // synopsys parallel_case
                `OR1200_QMEMFSM_IDLE: begin
                        if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_STORE;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_LOAD;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_FETCH;
                                qmem_iack <= #1 1'b1;
                                qmem_dack <= #1 1'b0;
                        end
                end
                `OR1200_QMEMFSM_STORE: begin
                        if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_STORE;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_LOAD;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_FETCH;
                                qmem_iack <= #1 1'b1;
                                qmem_dack <= #1 1'b0;
                        end
                        else begin
                                state <= #1 `OR1200_QMEMFSM_IDLE;
                                qmem_dack <= #1 1'b0;
                                qmem_iack <= #1 1'b0;
                        end
                end
                `OR1200_QMEMFSM_LOAD: begin
                        if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_STORE;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_LOAD;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_FETCH;
                                qmem_iack <= #1 1'b1;
                                qmem_dack <= #1 1'b0;
                        end
                        else begin
                                state <= #1 `OR1200_QMEMFSM_IDLE;
                                qmem_dack <= #1 1'b0;
                                qmem_iack <= #1 1'b0;
                        end
                end
                `OR1200_QMEMFSM_FETCH: begin
                        if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_STORE;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_LOAD;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_FETCH;
                                qmem_iack <= #1 1'b1;
                                qmem_dack <= #1 1'b0;
                        end
                        else begin
                                state <= #1 `OR1200_QMEMFSM_IDLE;
                                qmem_dack <= #1 1'b0;
                                qmem_iack <= #1 1'b0;
                        end
                end
        endcase
 
//
// Instantiation of embedded memory
//
or1200_spram_2048x32 or1200_qmem_ram(
        .clk(clk),
        .rst(rst),
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .addr(qmem_addr[12:2]),
`ifdef OR1200_QMEM_BSEL
        .sel(qmem_sel),
`endif
`ifdef OR1200_QMEM_ACK
  .ack(qmem_ack),
`endif
  .ce(qmem_en),
        .we(qmem_we),
        .oe(1'b1),
        .di(qmem_di),
        .do(qmem_do)
);
 
`else  // OR1200_QMEM_IMPLEMENTED
 
//
// QMEM and CPU/IMMU
//
assign qmemicpu_dat_o = icqmem_dat_i;
assign qmemicpu_ack_o = icqmem_ack_i;
assign qmemimmu_rty_o = icqmem_rty_i;
assign qmemimmu_err_o = icqmem_err_i;
assign qmemimmu_tag_o = icqmem_tag_i;
 
//
// QMEM and IC
//
assign icqmem_adr_o = qmemimmu_adr_i;
assign icqmem_cycstb_o = qmemimmu_cycstb_i;
assign icqmem_ci_o = qmemimmu_ci_i;
assign icqmem_sel_o = qmemicpu_sel_i;
assign icqmem_tag_o = qmemicpu_tag_i;
 
//
// QMEM and CPU/DMMU
//
assign qmemdcpu_dat_o = dcqmem_dat_i;
assign qmemdcpu_ack_o = dcqmem_ack_i;
assign qmemdcpu_rty_o = dcqmem_rty_i;
assign qmemdmmu_err_o = dcqmem_err_i;
assign qmemdmmu_tag_o = dcqmem_tag_i;
 
//
// QMEM and DC
//
assign dcqmem_adr_o = qmemdmmu_adr_i;
assign dcqmem_cycstb_o = qmemdmmu_cycstb_i;
assign dcqmem_ci_o = qmemdmmu_ci_i;
assign dcqmem_we_o = qmemdcpu_we_i;
assign dcqmem_sel_o = qmemdcpu_sel_i;
assign dcqmem_tag_o = qmemdcpu_tag_i;
assign dcqmem_dat_o = qmemdcpu_dat_i;
 
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	1172	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Embedded Memory ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Embedded Memory . ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - QMEM and IC/DC muxes can be removed except for cycstb ////`
13			`//// (now are is there for easier debugging) ////`
14			`//// - currently arbitration is slow and stores take 2 clocks ////`
15			`//// (final debugged version will be faster) ////`
16			`//// ////`
17			`//// Author(s): ////`
18			`//// - Damjan Lampret, lampret@opencores.org ////`
19			`//// ////`
20			`//////////////////////////////////////////////////////////////////////`
21			`//// ////`
22			`//// Copyright (C) 2003 Authors and OPENCORES.ORG ////`
23			`//// ////`
24			`//// This source file may be used and distributed without ////`
25			`//// restriction provided that this copyright statement is not ////`
26			`//// removed from the file and that any derivative work contains ////`
27			`//// the original copyright notice and the associated disclaimer. ////`
28			`//// ////`
29			`//// This source file is free software; you can redistribute it ////`
30			`//// and/or modify it under the terms of the GNU Lesser General ////`
31			`//// Public License as published by the Free Software Foundation; ////`
32			`//// either version 2.1 of the License, or (at your option) any ////`
33			`//// later version. ////`
34			`//// ////`
35			`//// This source is distributed in the hope that it will be ////`
36			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
37			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
38			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
39			`//// details. ////`
40			`//// ////`
41			`//// You should have received a copy of the GNU Lesser General ////`
42			`//// Public License along with this source; if not, download it ////`
43			`//// from http://www.opencores.org/lgpl.shtml ////`
44			`//// ////`
45			`//////////////////////////////////////////////////////////////////////`
46			`//`
47			`// CVS Revision History`
48			`//`
49			`// $Log: not supported by cvs2svn $`
50	1225	andreje	`// Revision 1.1.2.3 2003/12/17 13:36:58 simons`
51			`// Qmem mbist signals fixed.`
52			`//`
53	1219	simons	`// Revision 1.1.2.2 2003/12/09 11:46:48 simons`
54			`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`
55			`//`
56	1214	simons	`// Revision 1.1.2.1 2003/07/08 15:45:26 lampret`
57			`// Added embedded memory QMEM.`
58	1172	lampret	`//`
59	1214	simons	`//`
60	1172	lampret
61			`// synopsys translate_off`
62			`include "timescale.v"
63			`// synopsys translate_on`
64			`include "or1200_defines.v"
65
66			`define OR1200_QMEMFSM_IDLE 3'd0
67			`define OR1200_QMEMFSM_STORE 3'd1
68			`define OR1200_QMEMFSM_LOAD 3'd2
69			`define OR1200_QMEMFSM_FETCH 3'd3
70
71			`//`
72			`// Embedded memory`
73			`//`
74			`module or1200_qmem_top(`
75			`// Rst, clk and clock control`
76			`clk, rst,`
77
78			`ifdef OR1200_BIST
79			`// RAM BIST`
80	1214	simons	`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
81	1172	lampret	`endif
82
83			`// QMEM and CPU/IMMU`
84			`qmemimmu_adr_i,`
85			`qmemimmu_cycstb_i,`
86			`qmemimmu_ci_i,`
87			`qmemicpu_sel_i,`
88			`qmemicpu_tag_i,`
89			`qmemicpu_dat_o,`
90			`qmemicpu_ack_o,`
91			`qmemimmu_rty_o,`
92			`qmemimmu_err_o,`
93			`qmemimmu_tag_o,`
94
95			`// QMEM and IC`
96			`icqmem_adr_o,`
97			`icqmem_cycstb_o,`
98			`icqmem_ci_o,`
99			`icqmem_sel_o,`
100			`icqmem_tag_o,`
101			`icqmem_dat_i,`
102			`icqmem_ack_i,`
103			`icqmem_rty_i,`
104			`icqmem_err_i,`
105			`icqmem_tag_i,`
106
107			`// QMEM and CPU/DMMU`
108			`qmemdmmu_adr_i,`
109			`qmemdmmu_cycstb_i,`
110			`qmemdmmu_ci_i,`
111			`qmemdcpu_we_i,`
112			`qmemdcpu_sel_i,`
113			`qmemdcpu_tag_i,`
114			`qmemdcpu_dat_i,`
115			`qmemdcpu_dat_o,`
116			`qmemdcpu_ack_o,`
117			`qmemdcpu_rty_o,`
118			`qmemdmmu_err_o,`
119			`qmemdmmu_tag_o,`
120
121			`// QMEM and DC`
122			`dcqmem_adr_o, dcqmem_cycstb_o, dcqmem_ci_o,`
123			`dcqmem_we_o, dcqmem_sel_o, dcqmem_tag_o, dcqmem_dat_o,`
124			`dcqmem_dat_i, dcqmem_ack_i, dcqmem_rty_i, dcqmem_err_i, dcqmem_tag_i`
125
126			`);`
127
128			parameter dw = `OR1200_OPERAND_WIDTH;
129
130			`//`
131			`// I/O`
132			`//`
133
134			`//`
135			`// Clock and reset`
136			`//`
137			`input clk;`
138			`input rst;`
139
140			`ifdef OR1200_BIST
141			`//`
142			`// RAM BIST`
143			`//`
144	1214	simons	`input mbist_si_i;`
145			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
146			`output mbist_so_o;`
147	1172	lampret	`endif
148
149			`//`
150			`// QMEM and CPU/IMMU`
151			`//`
152			`input [31:0] qmemimmu_adr_i;`
153			`input qmemimmu_cycstb_i;`
154			`input qmemimmu_ci_i;`
155			`input [3:0] qmemicpu_sel_i;`
156			`input [3:0] qmemicpu_tag_i;`
157			`output [31:0] qmemicpu_dat_o;`
158			`output qmemicpu_ack_o;`
159			`output qmemimmu_rty_o;`
160			`output qmemimmu_err_o;`
161			`output [3:0] qmemimmu_tag_o;`
162
163			`//`
164			`// QMEM and IC`
165			`//`
166			`output [31:0] icqmem_adr_o;`
167			`output icqmem_cycstb_o;`
168			`output icqmem_ci_o;`
169			`output [3:0] icqmem_sel_o;`
170			`output [3:0] icqmem_tag_o;`
171			`input [31:0] icqmem_dat_i;`
172			`input icqmem_ack_i;`
173			`input icqmem_rty_i;`
174			`input icqmem_err_i;`
175			`input [3:0] icqmem_tag_i;`
176
177			`//`
178			`// QMEM and CPU/DMMU`
179			`//`
180			`input [31:0] qmemdmmu_adr_i;`
181			`input qmemdmmu_cycstb_i;`
182			`input qmemdmmu_ci_i;`
183			`input qmemdcpu_we_i;`
184			`input [3:0] qmemdcpu_sel_i;`
185			`input [3:0] qmemdcpu_tag_i;`
186			`input [31:0] qmemdcpu_dat_i;`
187			`output [31:0] qmemdcpu_dat_o;`
188			`output qmemdcpu_ack_o;`
189			`output qmemdcpu_rty_o;`
190			`output qmemdmmu_err_o;`
191			`output [3:0] qmemdmmu_tag_o;`
192
193			`//`
194			`// QMEM and DC`
195			`//`
196			`output [31:0] dcqmem_adr_o;`
197			`output dcqmem_cycstb_o;`
198			`output dcqmem_ci_o;`
199			`output dcqmem_we_o;`
200			`output [3:0] dcqmem_sel_o;`
201			`output [3:0] dcqmem_tag_o;`
202			`output [dw-1:0] dcqmem_dat_o;`
203			`input [dw-1:0] dcqmem_dat_i;`
204			`input dcqmem_ack_i;`
205			`input dcqmem_rty_i;`
206			`input dcqmem_err_i;`
207			`input [3:0] dcqmem_tag_i;`
208
209			`ifdef OR1200_QMEM_IMPLEMENTED
210
211			`//`
212			`// Internal regs and wires`
213			`//`
214			`wire iaddr_qmem_hit;`
215			`wire daddr_qmem_hit;`
216			`reg [2:0] state;`
217			`reg qmem_dack;`
218			`reg qmem_iack;`
219			`wire [31:0] qmem_di;`
220			`wire [31:0] qmem_do;`
221			`wire qmem_en;`
222			`wire qmem_we;`
223	1225	andreje	`ifdef OR1200_QMEM_BSEL
224			`wire [3:0] qmem_sel;`
225			`endif
226	1172	lampret	`wire [31:0] qmem_addr;`
227	1225	andreje	`ifdef OR1200_QMEM_ACK
228			`wire qmem_ack;`
229			`else
230			`wire qmem_ack = 1'b1;`
231			`endif
232	1172	lampret
233			`//`
234			`// QMEM and CPU/IMMU`
235			`//`
236			`assign qmemicpu_dat_o = qmem_iack ? qmem_do : icqmem_dat_i;`
237			`assign qmemicpu_ack_o = qmem_iack ? 1'b1 : icqmem_ack_i;`
238			`assign qmemimmu_rty_o = qmem_iack ? 1'b0 : icqmem_rty_i;`
239			`assign qmemimmu_err_o = qmem_iack ? 1'b0 : icqmem_err_i;`
240			`assign qmemimmu_tag_o = qmem_iack ? 4'h0 : icqmem_tag_i;`
241
242			`//`
243			`// QMEM and IC`
244			`//`
245			`assign icqmem_adr_o = iaddr_qmem_hit ? 32'h0000_0000 : qmemimmu_adr_i;`
246			`assign icqmem_cycstb_o = iaddr_qmem_hit ? 1'b0 : qmemimmu_cycstb_i;`
247			`assign icqmem_ci_o = iaddr_qmem_hit ? 1'b0 : qmemimmu_ci_i;`
248			`assign icqmem_sel_o = iaddr_qmem_hit ? 4'h0 : qmemicpu_sel_i;`
249			`assign icqmem_tag_o = iaddr_qmem_hit ? 4'h0 : qmemicpu_tag_i;`
250
251			`//`
252			`// QMEM and CPU/DMMU`
253			`//`
254			`assign qmemdcpu_dat_o = daddr_qmem_hit ? qmem_do : dcqmem_dat_i;`
255			`assign qmemdcpu_ack_o = daddr_qmem_hit ? qmem_dack : dcqmem_ack_i;`
256	1225	andreje	`assign qmemdcpu_rty_o = daddr_qmem_hit ? ~qmem_dack : dcqmem_rty_i;`
257	1172	lampret	`assign qmemdmmu_err_o = daddr_qmem_hit ? 1'b0 : dcqmem_err_i;`
258			`assign qmemdmmu_tag_o = daddr_qmem_hit ? 4'h0 : dcqmem_tag_i;`
259
260			`//`
261			`// QMEM and DC`
262			`//`
263			`assign dcqmem_adr_o = daddr_qmem_hit ? 32'h0000_0000 : qmemdmmu_adr_i;`
264			`assign dcqmem_cycstb_o = daddr_qmem_hit ? 1'b0 : qmemdmmu_cycstb_i;`
265			`assign dcqmem_ci_o = daddr_qmem_hit ? 1'b0 : qmemdmmu_ci_i;`
266			`assign dcqmem_we_o = daddr_qmem_hit ? 1'b0 : qmemdcpu_we_i;`
267			`assign dcqmem_sel_o = daddr_qmem_hit ? 4'h0 : qmemdcpu_sel_i;`
268			`assign dcqmem_tag_o = daddr_qmem_hit ? 4'h0 : qmemdcpu_tag_i;`
269			`assign dcqmem_dat_o = daddr_qmem_hit ? 32'h0000_0000 : qmemdcpu_dat_i;`
270
271			`//`
272			`// Address comparison whether QMEM was hit`
273			`//`
274	1225	andreje	`ifdef OR1200_QMEM_IADDR
275			assign iaddr_qmem_hit = (qmemimmu_adr_i & `OR1200_QMEM_IMASK) == `OR1200_QMEM_IADDR;
276			`else
277			`assign iaddr_qmem_hit = 1'b0;`
278			`endif
279	1172	lampret
280	1225	andreje	`ifdef OR1200_QMEM_DADDR
281			assign daddr_qmem_hit = (qmemdmmu_adr_i & `OR1200_QMEM_DMASK) == `OR1200_QMEM_DADDR;
282			`else
283			`assign daddr_qmem_hit = 1'b0;`
284			`endif
285
286	1172	lampret	`//`
287			`//`
288			`//`
289			`assign qmem_en = iaddr_qmem_hit & qmemimmu_cycstb_i \| daddr_qmem_hit & qmemdmmu_cycstb_i;`
290			`assign qmem_we = qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i;`
291	1225	andreje	`ifdef OR1200_QMEM_BSEL
292			`assign qmem_sel = (qmemdmmu_cycstb_i & daddr_qmem_hit) ? qmemdcpu_sel_i : qmemicpu_sel_i;`
293			`endif
294	1172	lampret	`assign qmem_di = qmemdcpu_dat_i;`
295			`assign qmem_addr = (qmemdmmu_cycstb_i & daddr_qmem_hit) ? qmemdmmu_adr_i : qmemimmu_adr_i;`
296
297			`//`
298			`// QMEM control FSM`
299			`//`
300			`always @(posedge rst or posedge clk)`
301			`if (rst) begin`
302			state <= #1 `OR1200_QMEMFSM_IDLE;
303			`qmem_dack <= #1 1'b0;`
304			`qmem_iack <= #1 1'b0;`
305			`end`
306			`else case (state) // synopsys parallel_case`
307			`OR1200_QMEMFSM_IDLE: begin
308	1225	andreje	`if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin`
309	1172	lampret	state <= #1 `OR1200_QMEMFSM_STORE;
310			`qmem_dack <= #1 1'b1;`
311			`qmem_iack <= #1 1'b0;`
312			`end`
313	1225	andreje	`else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin`
314	1172	lampret	state <= #1 `OR1200_QMEMFSM_LOAD;
315			`qmem_dack <= #1 1'b1;`
316			`qmem_iack <= #1 1'b0;`
317			`end`
318	1225	andreje	`else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin`
319	1172	lampret	state <= #1 `OR1200_QMEMFSM_FETCH;
320			`qmem_iack <= #1 1'b1;`
321			`qmem_dack <= #1 1'b0;`
322			`end`
323			`end`
324			`OR1200_QMEMFSM_STORE: begin
325	1225	andreje	`if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin`
326	1172	lampret	state <= #1 `OR1200_QMEMFSM_STORE;
327			`qmem_dack <= #1 1'b1;`
328			`qmem_iack <= #1 1'b0;`
329			`end`
330	1225	andreje	`else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin`
331	1172	lampret	state <= #1 `OR1200_QMEMFSM_LOAD;
332			`qmem_dack <= #1 1'b1;`
333			`qmem_iack <= #1 1'b0;`
334			`end`
335	1225	andreje	`else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin`
336	1172	lampret	state <= #1 `OR1200_QMEMFSM_FETCH;
337			`qmem_iack <= #1 1'b1;`
338			`qmem_dack <= #1 1'b0;`
339			`end`
340			`else begin`
341			state <= #1 `OR1200_QMEMFSM_IDLE;
342			`qmem_dack <= #1 1'b0;`
343			`qmem_iack <= #1 1'b0;`
344			`end`
345			`end`
346			`OR1200_QMEMFSM_LOAD: begin
347	1225	andreje	`if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin`
348	1172	lampret	state <= #1 `OR1200_QMEMFSM_STORE;
349			`qmem_dack <= #1 1'b1;`
350			`qmem_iack <= #1 1'b0;`
351			`end`
352	1225	andreje	`else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin`
353	1172	lampret	state <= #1 `OR1200_QMEMFSM_LOAD;
354			`qmem_dack <= #1 1'b1;`
355			`qmem_iack <= #1 1'b0;`
356			`end`
357	1225	andreje	`else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin`
358	1172	lampret	state <= #1 `OR1200_QMEMFSM_FETCH;
359			`qmem_iack <= #1 1'b1;`
360			`qmem_dack <= #1 1'b0;`
361			`end`
362			`else begin`
363			state <= #1 `OR1200_QMEMFSM_IDLE;
364			`qmem_dack <= #1 1'b0;`
365			`qmem_iack <= #1 1'b0;`
366			`end`
367			`end`
368			`OR1200_QMEMFSM_FETCH: begin
369	1225	andreje	`if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin`
370	1172	lampret	state <= #1 `OR1200_QMEMFSM_STORE;
371			`qmem_dack <= #1 1'b1;`
372			`qmem_iack <= #1 1'b0;`
373			`end`
374	1225	andreje	`else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin`
375	1172	lampret	state <= #1 `OR1200_QMEMFSM_LOAD;
376			`qmem_dack <= #1 1'b1;`
377			`qmem_iack <= #1 1'b0;`
378			`end`
379	1225	andreje	`else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin`
380	1172	lampret	state <= #1 `OR1200_QMEMFSM_FETCH;
381			`qmem_iack <= #1 1'b1;`
382			`qmem_dack <= #1 1'b0;`
383			`end`
384			`else begin`
385			state <= #1 `OR1200_QMEMFSM_IDLE;
386			`qmem_dack <= #1 1'b0;`
387			`qmem_iack <= #1 1'b0;`
388			`end`
389			`end`
390			`endcase`
391
392			`//`
393			`// Instantiation of embedded memory`
394			`//`
395			`or1200_spram_2048x32 or1200_qmem_ram(`
396			`.clk(clk),`
397			`.rst(rst),`
398			`ifdef OR1200_BIST
399			`// RAM BIST`
400	1214	simons	`.mbist_si_i(mbist_si_i),`
401			`.mbist_so_o(mbist_so_o),`
402			`.mbist_ctrl_i(mbist_ctrl_i),`
403	1172	lampret	`endif
404			`.addr(qmem_addr[12:2]),`
405	1225	andreje	`ifdef OR1200_QMEM_BSEL
406			`.sel(qmem_sel),`
407			`endif
408			`ifdef OR1200_QMEM_ACK
409			`.ack(qmem_ack),`
410			`endif
411			`.ce(qmem_en),`
412	1172	lampret	`.we(qmem_we),`
413			`.oe(1'b1),`
414			`.di(qmem_di),`
415			`.do(qmem_do)`
416			`);`
417
418			`else // OR1200_QMEM_IMPLEMENTED
419
420			`//`
421			`// QMEM and CPU/IMMU`
422			`//`
423			`assign qmemicpu_dat_o = icqmem_dat_i;`
424			`assign qmemicpu_ack_o = icqmem_ack_i;`
425			`assign qmemimmu_rty_o = icqmem_rty_i;`
426			`assign qmemimmu_err_o = icqmem_err_i;`
427			`assign qmemimmu_tag_o = icqmem_tag_i;`
428
429			`//`
430			`// QMEM and IC`
431			`//`
432			`assign icqmem_adr_o = qmemimmu_adr_i;`
433			`assign icqmem_cycstb_o = qmemimmu_cycstb_i;`
434			`assign icqmem_ci_o = qmemimmu_ci_i;`
435			`assign icqmem_sel_o = qmemicpu_sel_i;`
436			`assign icqmem_tag_o = qmemicpu_tag_i;`
437
438			`//`
439			`// QMEM and CPU/DMMU`
440			`//`
441			`assign qmemdcpu_dat_o = dcqmem_dat_i;`
442			`assign qmemdcpu_ack_o = dcqmem_ack_i;`
443			`assign qmemdcpu_rty_o = dcqmem_rty_i;`
444			`assign qmemdmmu_err_o = dcqmem_err_i;`
445			`assign qmemdmmu_tag_o = dcqmem_tag_i;`
446
447			`//`
448			`// QMEM and DC`
449			`//`
450			`assign dcqmem_adr_o = qmemdmmu_adr_i;`
451			`assign dcqmem_cycstb_o = qmemdmmu_cycstb_i;`
452			`assign dcqmem_ci_o = qmemdmmu_ci_i;`
453			`assign dcqmem_we_o = qmemdcpu_we_i;`
454			`assign dcqmem_sel_o = qmemdcpu_sel_i;`
455			`assign dcqmem_tag_o = qmemdcpu_tag_i;`
456			`assign dcqmem_dat_o = qmemdcpu_dat_i;`
457
458	1219	simons	`ifdef OR1200_BIST
459			`assign mbist_so_o = mbist_si_i;`
460	1172	lampret	`endif
461
462	1219	simons	`endif
463
464	1172	lampret	`endmodule`

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