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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM with byte write signals ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16                                   ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2003/08/27 08:38:36  simons
// Added support for rams with byte write access.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_1024x32_bw(
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
);
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input                   mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
output                  mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input   [3:0]           we;     // Write enable input
input                   oe;     // Output enable input
input   [9:0]           addr;   // address bus inputs
input   [31:0]          di;     // input data bus
output  [31:0]          do;     // output data bus
 
//
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_1024x32_bw artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_1024x32_bw_bist artisan_ssp(
`else
art_hssp_1024x32_bw artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CLK(clk),
        .CEN(~ce),
        .WEN(~we),
        .A(addr),
        .D(di),
        .OEN(~oe),
        .Q(do)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(do)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef OR1200_BIST
wire mbist_si_i_ram_0;
wire mbist_si_i_ram_1;
wire mbist_si_i_ram_2;
wire mbist_si_i_ram_3;
wire mbist_so_o_ram_0;
wire mbist_so_o_ram_1;
wire mbist_so_o_ram_2;
wire mbist_so_o_ram_3;
assign mbist_si_i_ram_0 = mbist_si_i;
assign mbist_si_i_ram_1 = mbist_so_o_ram_0;
assign mbist_si_i_ram_2 = mbist_so_o_ram_1;
assign mbist_si_i_ram_3 = mbist_so_o_ram_2;
assign mbist_so_o = mbist_so_o_ram_3;
`endif
 
`ifdef UNUSED
vs_hdsp_1024x8 vs_ssp_0(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x8_bist vs_ssp_0(
`else
vs_hdsp_1024x8 vs_ssp_0(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i_ram_0),
        .mbist_so_o(mbist_so_o_ram_0),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[7:0]),
        .WEN(~we[0]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do[7:0])
);
 
`ifdef UNUSED
vs_hdsp_1024x8 vs_ssp_1(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x8_bist vs_ssp_1(
`else
vs_hdsp_1024x8 vs_ssp_1(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i_ram_1),
        .mbist_so_o(mbist_so_o_ram_1),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[15:8]),
        .WEN(~we[1]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do[15:8])
);
 
`ifdef UNUSED
vs_hdsp_1024x8 vs_ssp_2(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x8_bist vs_ssp_2(
`else
vs_hdsp_1024x8 vs_ssp_2(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i_ram_2),
        .mbist_so_o(mbist_so_o_ram_2),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[23:16]),
        .WEN(~we[2]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do[23:16])
);
 
`ifdef UNUSED
vs_hdsp_1024x8 vs_ssp_3(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x8_bist vs_ssp_3(
`else
vs_hdsp_1024x8 vs_ssp_3(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i_ram_3),
        .mbist_so_o(mbist_so_o_ram_3),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[31:24]),
        .WEN(~we[3]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do[31:24])
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S4 ramb4_s4_0(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[3:0]),
        .EN(ce),
        .WE(we[0]),
        .DO(do[3:0])
);
 
//
// Block 1
//
RAMB4_S4 ramb4_s4_1(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[7:4]),
        .EN(ce),
        .WE(we[0]),
        .DO(do[7:4])
);
 
//
// Block 2
//
RAMB4_S4 ramb4_s4_2(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[11:8]),
        .EN(ce),
        .WE(we[1]),
        .DO(do[11:8])
);
 
//
// Block 3
//
RAMB4_S4 ramb4_s4_3(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[15:12]),
        .EN(ce),
        .WE(we[1]),
        .DO(do[15:12])
);
 
//
// Block 4
//
RAMB4_S4 ramb4_s4_4(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[19:16]),
        .EN(ce),
        .WE(we[2]),
        .DO(do[19:16])
);
 
//
// Block 5
//
RAMB4_S4 ramb4_s4_5(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[23:20]),
        .EN(ce),
        .WE(we[2]),
        .DO(do[23:20])
);
 
//
// Block 6
//
RAMB4_S4 ramb4_s4_6(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[27:24]),
        .EN(ce),
        .WE(we[3]),
        .DO(do[27:24])
);
 
//
// Block 7
//
RAMB4_S4 ramb4_s4_7(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[31:28]),
        .EN(ce),
        .WE(we[3]),
        .DO(do[31:28])
);
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [31:0]        mem_0 [9:0];              // RAM content
reg     [31:0]        mem_1 [9:0];              // RAM content
reg     [31:0]        mem_2 [9:0];              // RAM content
reg     [31:0]        mem_3 [9:0];              // RAM content
reg     [31:0]        do_reg;                 // RAM data output register
 
//
// Data output drivers
//
assign do = (oe) ? do_reg : {32{1'b0}};
 
//
// RAM read and write
//
always @(posedge clk)
        if (ce && !we) begin
                do_reg[7:0]   <= #1 mem_0[addr];
                do_reg[15:8]  <= #1 mem_1[addr];
                do_reg[23:16] <= #1 mem_2[addr];
                do_reg[31:24] <= #1 mem_3[addr];
        end
        else if (ce && we[0])
                mem_0[addr] <= #1 di[7:0];
        else if (ce && we[1])
                mem_1[addr] <= #1 di[15:8];
        else if (ce && we[2])
                mem_2[addr] <= #1 di[23:16];
        else if (ce && we[3])
                mem_3[addr] <= #1 di[31:24];
 
`endif  // !OR1200_XILINX_RAMB4_S16
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

Line No.	Rev	Author	Line
1	1188	simons	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM with byte write signals ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB4_S16 ////`
26			`//// - Altera LPM ////`
27			`//// ////`
28			`//// To Do: ////`
29			`//// - xilinx rams need external tri-state logic ////`
30			`//// - fix avant! two-port ram ////`
31			`//// - add additional RAMs ////`
32			`//// ////`
33			`//// Author(s): ////`
34			`//// - Damjan Lampret, lampret@opencores.org ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//// ////`
38			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
39			`//// ////`
40			`//// This source file may be used and distributed without ////`
41			`//// restriction provided that this copyright statement is not ////`
42			`//// removed from the file and that any derivative work contains ////`
43			`//// the original copyright notice and the associated disclaimer. ////`
44			`//// ////`
45			`//// This source file is free software; you can redistribute it ////`
46			`//// and/or modify it under the terms of the GNU Lesser General ////`
47			`//// Public License as published by the Free Software Foundation; ////`
48			`//// either version 2.1 of the License, or (at your option) any ////`
49			`//// later version. ////`
50			`//// ////`
51			`//// This source is distributed in the hope that it will be ////`
52			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
53			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
54			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
55			`//// details. ////`
56			`//// ////`
57			`//// You should have received a copy of the GNU Lesser General ////`
58			`//// Public License along with this source; if not, download it ////`
59			`//// from http://www.opencores.org/lgpl.shtml ////`
60			`//// ////`
61			`//////////////////////////////////////////////////////////////////////`
62			`//`
63			`// CVS Revision History`
64			`//`
65			`// $Log: not supported by cvs2svn $`
66	1200	markom	`// Revision 1.1 2003/08/27 08:38:36 simons`
67			`// Added support for rams with byte write access.`
68	1188	simons	`//`
69	1200	markom	`//`
70	1188	simons
71			`// synopsys translate_off`
72			`include "timescale.v"
73			`// synopsys translate_on`
74			`include "or1200_defines.v"
75
76			`module or1200_spram_1024x32_bw(`
77			`ifdef OR1200_BIST
78			`// RAM BIST`
79	1200	markom	`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
80	1188	simons	`endif
81			`// Generic synchronous single-port RAM interface`
82			`clk, rst, ce, we, oe, addr, di, do`
83			`);`
84
85			`ifdef OR1200_BIST
86			`//`
87			`// RAM BIST`
88			`//`
89	1200	markom	`input mbist_si_i;`
90			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
91			`output mbist_so_o;`
92	1188	simons	`endif
93
94			`//`
95			`// Generic synchronous single-port RAM interface`
96			`//`
97			`input clk; // Clock`
98			`input rst; // Reset`
99			`input ce; // Chip enable input`
100			`input [3:0] we; // Write enable input`
101			`input oe; // Output enable input`
102			`input [9:0] addr; // address bus inputs`
103			`input [31:0] di; // input data bus`
104			`output [31:0] do; // output data bus`
105
106			`//`
107			`// Internal wires and registers`
108			`//`
109
110			`ifdef OR1200_ARTISAN_SSP
111			`else
112			`ifdef OR1200_VIRTUALSILICON_SSP
113			`else
114			`ifdef OR1200_BIST
115	1200	markom	`assign mbist_so_o = mbist_si_i;`
116	1188	simons	`endif
117			`endif
118			`endif
119
120
121			`ifdef OR1200_ARTISAN_SSP
122
123			`//`
124			`// Instantiation of ASIC memory:`
125			`//`
126			`// Artisan Synchronous Single-Port RAM (ra1sh)`
127			`//`
128			`ifdef UNUSED
129			`art_hssp_1024x32_bw artisan_ssp(`
130			`else
131			`ifdef OR1200_BIST
132			`art_hssp_1024x32_bw_bist artisan_ssp(`
133			`else
134			`art_hssp_1024x32_bw artisan_ssp(`
135			`endif
136			`endif
137			`ifdef OR1200_BIST
138			`// RAM BIST`
139	1200	markom	`.mbist_si_i(mbist_si_i),`
140			`.mbist_so_o(mbist_so_o),`
141			`.mbist_ctrl_i(mbist_ctrl_i),`
142	1188	simons	`endif
143			`.CLK(clk),`
144			`.CEN(~ce),`
145			`.WEN(~we),`
146			`.A(addr),`
147			`.D(di),`
148			`.OEN(~oe),`
149			`.Q(do)`
150			`);`
151
152			`else
153
154			`ifdef OR1200_AVANT_ATP
155
156			`//`
157			`// Instantiation of ASIC memory:`
158			`//`
159			`// Avant! Asynchronous Two-Port RAM`
160			`//`
161			`avant_atp avant_atp(`
162			`.web(~we),`
163			`.reb(),`
164			`.oeb(~oe),`
165			`.rcsb(),`
166			`.wcsb(),`
167			`.ra(addr),`
168			`.wa(addr),`
169			`.di(di),`
170			`.do(do)`
171			`);`
172
173			`else
174
175			`ifdef OR1200_VIRAGE_SSP
176
177			`//`
178			`// Instantiation of ASIC memory:`
179			`//`
180			`// Virage Synchronous 1-port R/W RAM`
181			`//`
182			`virage_ssp virage_ssp(`
183			`.clk(clk),`
184			`.adr(addr),`
185			`.d(di),`
186			`.we(we),`
187			`.oe(oe),`
188			`.me(ce),`
189			`.q(do)`
190			`);`
191
192			`else
193
194			`ifdef OR1200_VIRTUALSILICON_SSP
195
196			`//`
197			`// Instantiation of ASIC memory:`
198			`//`
199			`// Virtual Silicon Single-Port Synchronous SRAM`
200			`//`
201			`ifdef OR1200_BIST
202	1200	markom	`wire mbist_si_i_ram_0;`
203			`wire mbist_si_i_ram_1;`
204			`wire mbist_si_i_ram_2;`
205			`wire mbist_si_i_ram_3;`
206			`wire mbist_so_o_ram_0;`
207			`wire mbist_so_o_ram_1;`
208			`wire mbist_so_o_ram_2;`
209			`wire mbist_so_o_ram_3;`
210			`assign mbist_si_i_ram_0 = mbist_si_i;`
211			`assign mbist_si_i_ram_1 = mbist_so_o_ram_0;`
212			`assign mbist_si_i_ram_2 = mbist_so_o_ram_1;`
213			`assign mbist_si_i_ram_3 = mbist_so_o_ram_2;`
214			`assign mbist_so_o = mbist_so_o_ram_3;`
215	1188	simons	`endif
216
217			`ifdef UNUSED
218			`vs_hdsp_1024x8 vs_ssp_0(`
219			`else
220			`ifdef OR1200_BIST
221			`vs_hdsp_1024x8_bist vs_ssp_0(`
222			`else
223			`vs_hdsp_1024x8 vs_ssp_0(`
224			`endif
225			`endif
226			`ifdef OR1200_BIST
227			`// RAM BIST`
228	1200	markom	`.mbist_si_i(mbist_si_i_ram_0),`
229			`.mbist_so_o(mbist_so_o_ram_0),`
230			`.mbist_ctrl_i(mbist_ctrl_i),`
231	1188	simons	`endif
232			`.CK(clk),`
233			`.ADR(addr),`
234			`.DI(di[7:0]),`
235			`.WEN(~we[0]),`
236			`.CEN(~ce),`
237			`.OEN(~oe),`
238			`.DOUT(do[7:0])`
239			`);`
240
241			`ifdef UNUSED
242			`vs_hdsp_1024x8 vs_ssp_1(`
243			`else
244			`ifdef OR1200_BIST
245			`vs_hdsp_1024x8_bist vs_ssp_1(`
246			`else
247			`vs_hdsp_1024x8 vs_ssp_1(`
248			`endif
249			`endif
250			`ifdef OR1200_BIST
251			`// RAM BIST`
252	1200	markom	`.mbist_si_i(mbist_si_i_ram_1),`
253			`.mbist_so_o(mbist_so_o_ram_1),`
254			`.mbist_ctrl_i(mbist_ctrl_i),`
255	1188	simons	`endif
256			`.CK(clk),`
257			`.ADR(addr),`
258			`.DI(di[15:8]),`
259			`.WEN(~we[1]),`
260			`.CEN(~ce),`
261			`.OEN(~oe),`
262			`.DOUT(do[15:8])`
263			`);`
264
265			`ifdef UNUSED
266			`vs_hdsp_1024x8 vs_ssp_2(`
267			`else
268			`ifdef OR1200_BIST
269			`vs_hdsp_1024x8_bist vs_ssp_2(`
270			`else
271			`vs_hdsp_1024x8 vs_ssp_2(`
272			`endif
273			`endif
274			`ifdef OR1200_BIST
275			`// RAM BIST`
276	1200	markom	`.mbist_si_i(mbist_si_i_ram_2),`
277			`.mbist_so_o(mbist_so_o_ram_2),`
278			`.mbist_ctrl_i(mbist_ctrl_i),`
279	1188	simons	`endif
280			`.CK(clk),`
281			`.ADR(addr),`
282			`.DI(di[23:16]),`
283			`.WEN(~we[2]),`
284			`.CEN(~ce),`
285			`.OEN(~oe),`
286			`.DOUT(do[23:16])`
287			`);`
288
289			`ifdef UNUSED
290			`vs_hdsp_1024x8 vs_ssp_3(`
291			`else
292			`ifdef OR1200_BIST
293			`vs_hdsp_1024x8_bist vs_ssp_3(`
294			`else
295			`vs_hdsp_1024x8 vs_ssp_3(`
296			`endif
297			`endif
298			`ifdef OR1200_BIST
299			`// RAM BIST`
300	1200	markom	`.mbist_si_i(mbist_si_i_ram_3),`
301			`.mbist_so_o(mbist_so_o_ram_3),`
302			`.mbist_ctrl_i(mbist_ctrl_i),`
303	1188	simons	`endif
304			`.CK(clk),`
305			`.ADR(addr),`
306			`.DI(di[31:24]),`
307			`.WEN(~we[3]),`
308			`.CEN(~ce),`
309			`.OEN(~oe),`
310			`.DOUT(do[31:24])`
311			`);`
312
313			`else
314
315			`ifdef OR1200_XILINX_RAMB4
316
317			`//`
318			`// Instantiation of FPGA memory:`
319			`//`
320			`// Virtex/Spartan2`
321			`//`
322
323			`//`
324			`// Block 0`
325			`//`
326			`RAMB4_S4 ramb4_s4_0(`
327			`.CLK(clk),`
328			`.RST(rst),`
329			`.ADDR(addr),`
330			`.DI(di[3:0]),`
331			`.EN(ce),`
332			`.WE(we[0]),`
333			`.DO(do[3:0])`
334			`);`
335
336			`//`
337			`// Block 1`
338			`//`
339			`RAMB4_S4 ramb4_s4_1(`
340			`.CLK(clk),`
341			`.RST(rst),`
342			`.ADDR(addr),`
343			`.DI(di[7:4]),`
344			`.EN(ce),`
345			`.WE(we[0]),`
346			`.DO(do[7:4])`
347			`);`
348
349			`//`
350			`// Block 2`
351			`//`
352			`RAMB4_S4 ramb4_s4_2(`
353			`.CLK(clk),`
354			`.RST(rst),`
355			`.ADDR(addr),`
356			`.DI(di[11:8]),`
357			`.EN(ce),`
358			`.WE(we[1]),`
359			`.DO(do[11:8])`
360			`);`
361
362			`//`
363			`// Block 3`
364			`//`
365			`RAMB4_S4 ramb4_s4_3(`
366			`.CLK(clk),`
367			`.RST(rst),`
368			`.ADDR(addr),`
369			`.DI(di[15:12]),`
370			`.EN(ce),`
371			`.WE(we[1]),`
372			`.DO(do[15:12])`
373			`);`
374
375			`//`
376			`// Block 4`
377			`//`
378			`RAMB4_S4 ramb4_s4_4(`
379			`.CLK(clk),`
380			`.RST(rst),`
381			`.ADDR(addr),`
382			`.DI(di[19:16]),`
383			`.EN(ce),`
384			`.WE(we[2]),`
385			`.DO(do[19:16])`
386			`);`
387
388			`//`
389			`// Block 5`
390			`//`
391			`RAMB4_S4 ramb4_s4_5(`
392			`.CLK(clk),`
393			`.RST(rst),`
394			`.ADDR(addr),`
395			`.DI(di[23:20]),`
396			`.EN(ce),`
397			`.WE(we[2]),`
398			`.DO(do[23:20])`
399			`);`
400
401			`//`
402			`// Block 6`
403			`//`
404			`RAMB4_S4 ramb4_s4_6(`
405			`.CLK(clk),`
406			`.RST(rst),`
407			`.ADDR(addr),`
408			`.DI(di[27:24]),`
409			`.EN(ce),`
410			`.WE(we[3]),`
411			`.DO(do[27:24])`
412			`);`
413
414			`//`
415			`// Block 7`
416			`//`
417			`RAMB4_S4 ramb4_s4_7(`
418			`.CLK(clk),`
419			`.RST(rst),`
420			`.ADDR(addr),`
421			`.DI(di[31:28]),`
422			`.EN(ce),`
423			`.WE(we[3]),`
424			`.DO(do[31:28])`
425			`);`
426
427			`else
428
429			`//`
430			`// Generic single-port synchronous RAM model`
431			`//`
432
433			`//`
434			`// Generic RAM's registers and wires`
435			`//`
436			`reg [31:0] mem_0 [9:0]; // RAM content`
437			`reg [31:0] mem_1 [9:0]; // RAM content`
438			`reg [31:0] mem_2 [9:0]; // RAM content`
439			`reg [31:0] mem_3 [9:0]; // RAM content`
440			`reg [31:0] do_reg; // RAM data output register`
441
442			`//`
443			`// Data output drivers`
444			`//`
445			`assign do = (oe) ? do_reg : {32{1'b0}};`
446
447			`//`
448			`// RAM read and write`
449			`//`
450			`always @(posedge clk)`
451			`if (ce && !we) begin`
452			`do_reg[7:0] <= #1 mem_0[addr];`
453			`do_reg[15:8] <= #1 mem_1[addr];`
454			`do_reg[23:16] <= #1 mem_2[addr];`
455			`do_reg[31:24] <= #1 mem_3[addr];`
456			`end`
457			`else if (ce && we[0])`
458			`mem_0[addr] <= #1 di[7:0];`
459			`else if (ce && we[1])`
460			`mem_1[addr] <= #1 di[15:8];`
461			`else if (ce && we[2])`
462			`mem_2[addr] <= #1 di[23:16];`
463			`else if (ce && we[3])`
464			`mem_3[addr] <= #1 di[31:24];`
465
466			`endif // !OR1200_XILINX_RAMB4_S16
467			`endif // !OR1200_VIRTUALSILICON_SSP
468			`endif // !OR1200_VIRAGE_SSP
469			`endif // !OR1200_AVANT_ATP
470			`endif // !OR1200_ARTISAN_SSP
471
472			`endmodule`

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