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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x32.v] - Blame information for rev 1765

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1 504 lampret
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Generic Single-Port Synchronous RAM                         ////
4
////                                                              ////
5
////  This file is part of memory library available from          ////
6
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  This block is a wrapper with common single-port             ////
10
////  synchronous memory interface for different                  ////
11
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
12
////  interface it also provides behavioral model of generic      ////
13
////  single-port synchronous RAM.                                ////
14
////  It should be used in all OPENCORES designs that want to be  ////
15
////  portable accross different target technologies and          ////
16
////  independent of target memory.                               ////
17
////                                                              ////
18
////  Supported ASIC RAMs are:                                    ////
19
////  - Artisan Single-Port Sync RAM                              ////
20
////  - Avant! Two-Port Sync RAM (*)                              ////
21
////  - Virage Single-Port Sync RAM                               ////
22
////  - Virtual Silicon Single-Port Sync RAM                      ////
23
////                                                              ////
24
////  Supported FPGA RAMs are:                                    ////
25
////  - Xilinx Virtex RAMB4_S16                                   ////
26 1129 lampret
////  - Altera LPM                                                ////
27 504 lampret
////                                                              ////
28
////  To Do:                                                      ////
29
////   - xilinx rams need external tri-state logic                ////
30
////   - fix avant! two-port ram                                  ////
31 1129 lampret
////   - add additional RAMs                                      ////
32 504 lampret
////                                                              ////
33
////  Author(s):                                                  ////
34
////      - Damjan Lampret, lampret@opencores.org                 ////
35
////                                                              ////
36
//////////////////////////////////////////////////////////////////////
37
////                                                              ////
38
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
39
////                                                              ////
40
//// This source file may be used and distributed without         ////
41
//// restriction provided that this copyright statement is not    ////
42
//// removed from the file and that any derivative work contains  ////
43
//// the original copyright notice and the associated disclaimer. ////
44
////                                                              ////
45
//// This source file is free software; you can redistribute it   ////
46
//// and/or modify it under the terms of the GNU Lesser General   ////
47
//// Public License as published by the Free Software Foundation; ////
48
//// either version 2.1 of the License, or (at your option) any   ////
49
//// later version.                                               ////
50
////                                                              ////
51
//// This source is distributed in the hope that it will be       ////
52
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
53
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
54
//// PURPOSE.  See the GNU Lesser General Public License for more ////
55
//// details.                                                     ////
56
////                                                              ////
57
//// You should have received a copy of the GNU Lesser General    ////
58
//// Public License along with this source; if not, download it   ////
59
//// from http://www.opencores.org/lgpl.shtml                     ////
60
////                                                              ////
61
//////////////////////////////////////////////////////////////////////
62
//
63
// CVS Revision History
64
//
65
// $Log: not supported by cvs2svn $
66 1214 simons
// Revision 1.4  2003/04/07 01:19:07  lampret
67
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
68
//
69 1129 lampret
// Revision 1.3  2002/10/28 15:03:50  mohor
70
// Signal scanb_sen renamed to scanb_en.
71
//
72 1077 mohor
// Revision 1.2  2002/10/17 20:04:40  lampret
73
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
74
//
75 1063 lampret
// Revision 1.1  2002/01/03 08:16:15  lampret
76
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
77
//
78 504 lampret
// Revision 1.8  2001/11/02 18:57:14  lampret
79
// Modified virtual silicon instantiations.
80
//
81
// Revision 1.7  2001/10/21 17:57:16  lampret
82
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
83
//
84
// Revision 1.6  2001/10/14 13:12:09  lampret
85
// MP3 version.
86
//
87
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
88
// no message
89
//
90
// Revision 1.1  2001/08/09 13:39:33  lampret
91
// Major clean-up.
92
//
93
// Revision 1.2  2001/07/30 05:38:02  lampret
94
// Adding empty directories required by HDL coding guidelines
95
//
96
//
97
 
98
// synopsys translate_off
99
`include "timescale.v"
100
// synopsys translate_on
101
`include "or1200_defines.v"
102
 
103
module or1200_spram_2048x32(
104 1063 lampret
`ifdef OR1200_BIST
105
        // RAM BIST
106 1214 simons
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
107 1063 lampret
`endif
108 504 lampret
        // Generic synchronous single-port RAM interface
109
        clk, rst, ce, we, oe, addr, di, do
110
);
111
 
112
//
113
// Default address and data buses width
114
//
115
parameter aw = 11;
116
parameter dw = 32;
117
 
118 1063 lampret
`ifdef OR1200_BIST
119 504 lampret
//
120 1063 lampret
// RAM BIST
121
//
122 1214 simons
input mbist_si_i;
123
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
124
output mbist_so_o;
125 1063 lampret
`endif
126
 
127
//
128 504 lampret
// Generic synchronous single-port RAM interface
129
//
130
input                   clk;    // Clock
131
input                   rst;    // Reset
132
input                   ce;     // Chip enable input
133
input                   we;     // Write enable input
134
input                   oe;     // Output enable input
135
input   [aw-1:0] addr;   // address bus inputs
136
input   [dw-1:0] di;     // input data bus
137
output  [dw-1:0] do;     // output data bus
138
 
139
//
140
// Internal wires and registers
141
//
142
 
143 1214 simons
`ifdef OR1200_ARTISAN_SSP
144
`else
145 1063 lampret
`ifdef OR1200_VIRTUALSILICON_SSP
146
`else
147
`ifdef OR1200_BIST
148 1214 simons
assign mbist_so_o = mbist_si_i;
149 1063 lampret
`endif
150
`endif
151 1214 simons
`endif
152 504 lampret
 
153
`ifdef OR1200_ARTISAN_SSP
154
 
155
//
156
// Instantiation of ASIC memory:
157
//
158
// Artisan Synchronous Single-Port RAM (ra1sh)
159
//
160
`ifdef UNUSED
161
art_hdsp_2048x32 #(dw, 1<<aw, aw) artisan_ssp(
162
`else
163 1214 simons
`ifdef OR1200_BIST
164
art_hssp_2048x32_bist artisan_ssp(
165
`else
166
art_hssp_2048x32 artisan_ssp(
167 504 lampret
`endif
168 1214 simons
`endif
169
`ifdef OR1200_BIST
170
        // RAM BIST
171
        .mbist_si_i(mbist_si_i),
172
        .mbist_so_o(mbist_so_o),
173
        .mbist_ctrl_i(mbist_ctrl_i),
174
`endif
175
        .CLK(clk),
176
        .CEN(~ce),
177
        .WEN(~we),
178
        .A(addr),
179
        .D(di),
180
        .OEN(~oe),
181
        .Q(do)
182 504 lampret
);
183
 
184
`else
185
 
186
`ifdef OR1200_AVANT_ATP
187
 
188
//
189
// Instantiation of ASIC memory:
190
//
191
// Avant! Asynchronous Two-Port RAM
192
//
193
avant_atp avant_atp(
194
        .web(~we),
195
        .reb(),
196
        .oeb(~oe),
197
        .rcsb(),
198
        .wcsb(),
199
        .ra(addr),
200
        .wa(addr),
201
        .di(di),
202
        .do(do)
203
);
204
 
205
`else
206
 
207
`ifdef OR1200_VIRAGE_SSP
208
 
209
//
210
// Instantiation of ASIC memory:
211
//
212
// Virage Synchronous 1-port R/W RAM
213
//
214
virage_ssp virage_ssp(
215
        .clk(clk),
216
        .adr(addr),
217
        .d(di),
218
        .we(we),
219
        .oe(oe),
220
        .me(ce),
221
        .q(do)
222
);
223
 
224
`else
225
 
226
`ifdef OR1200_VIRTUALSILICON_SSP
227
 
228
//
229
// Instantiation of ASIC memory:
230
//
231
// Virtual Silicon Single-Port Synchronous SRAM
232
//
233
`ifdef UNUSED
234
vs_hdsp_2048x32 #(1<<aw, aw-1, dw-1) vs_ssp(
235
`else
236 1063 lampret
`ifdef OR1200_BIST
237
vs_hdsp_2048x32_bist vs_ssp(
238
`else
239 504 lampret
vs_hdsp_2048x32 vs_ssp(
240
`endif
241 1063 lampret
`endif
242
`ifdef OR1200_BIST
243
        // RAM BIST
244 1214 simons
        .mbist_si_i(mbist_si_i),
245
        .mbist_so_o(mbist_so_o),
246
        .mbist_ctrl_i(mbist_ctrl_i),
247 1063 lampret
`endif
248 504 lampret
        .CK(clk),
249
        .ADR(addr),
250
        .DI(di),
251
        .WEN(~we),
252
        .CEN(~ce),
253
        .OEN(~oe),
254
        .DOUT(do)
255
);
256
 
257
`else
258
 
259
`ifdef OR1200_XILINX_RAMB4
260
 
261
//
262
// Instantiation of FPGA memory:
263
//
264
// Virtex/Spartan2
265
//
266
 
267
//
268
// Block 0
269
//
270
RAMB4_S2 ramb4_s2_0(
271
        .CLK(clk),
272
        .RST(rst),
273
        .ADDR(addr),
274
        .DI(di[1:0]),
275
        .EN(ce),
276
        .WE(we),
277
        .DO(do[1:0])
278
);
279
 
280
//
281
// Block 1
282
//
283
RAMB4_S2 ramb4_s2_1(
284
        .CLK(clk),
285
        .RST(rst),
286
        .ADDR(addr),
287
        .DI(di[3:2]),
288
        .EN(ce),
289
        .WE(we),
290
        .DO(do[3:2])
291
);
292
 
293
//
294
// Block 2
295
//
296
RAMB4_S2 ramb4_s2_2(
297
        .CLK(clk),
298
        .RST(rst),
299
        .ADDR(addr),
300
        .DI(di[5:4]),
301
        .EN(ce),
302
        .WE(we),
303
        .DO(do[5:4])
304
);
305
 
306
//
307
// Block 3
308
//
309
RAMB4_S2 ramb4_s2_3(
310
        .CLK(clk),
311
        .RST(rst),
312
        .ADDR(addr),
313
        .DI(di[7:6]),
314
        .EN(ce),
315
        .WE(we),
316
        .DO(do[7:6])
317
);
318
 
319
//
320
// Block 4
321
//
322
RAMB4_S2 ramb4_s2_4(
323
        .CLK(clk),
324
        .RST(rst),
325
        .ADDR(addr),
326
        .DI(di[9:8]),
327
        .EN(ce),
328
        .WE(we),
329
        .DO(do[9:8])
330
);
331
 
332
//
333
// Block 5
334
//
335
RAMB4_S2 ramb4_s2_5(
336
        .CLK(clk),
337
        .RST(rst),
338
        .ADDR(addr),
339
        .DI(di[11:10]),
340
        .EN(ce),
341
        .WE(we),
342
        .DO(do[11:10])
343
);
344
 
345
//
346
// Block 6
347
//
348
RAMB4_S2 ramb4_s2_6(
349
        .CLK(clk),
350
        .RST(rst),
351
        .ADDR(addr),
352
        .DI(di[13:12]),
353
        .EN(ce),
354
        .WE(we),
355
        .DO(do[13:12])
356
);
357
 
358
//
359
// Block 7
360
//
361
RAMB4_S2 ramb4_s2_7(
362
        .CLK(clk),
363
        .RST(rst),
364
        .ADDR(addr),
365
        .DI(di[15:14]),
366
        .EN(ce),
367
        .WE(we),
368
        .DO(do[15:14])
369
);
370
 
371
//
372
// Block 8
373
//
374
RAMB4_S2 ramb4_s2_8(
375
        .CLK(clk),
376
        .RST(rst),
377
        .ADDR(addr),
378
        .DI(di[17:16]),
379
        .EN(ce),
380
        .WE(we),
381
        .DO(do[17:16])
382
);
383
 
384
//
385
// Block 9
386
//
387
RAMB4_S2 ramb4_s2_9(
388
        .CLK(clk),
389
        .RST(rst),
390
        .ADDR(addr),
391
        .DI(di[19:18]),
392
        .EN(ce),
393
        .WE(we),
394
        .DO(do[19:18])
395
);
396
 
397
//
398
// Block 10
399
//
400
RAMB4_S2 ramb4_s2_10(
401
        .CLK(clk),
402
        .RST(rst),
403
        .ADDR(addr),
404
        .DI(di[21:20]),
405
        .EN(ce),
406
        .WE(we),
407
        .DO(do[21:20])
408
);
409
 
410
//
411
// Block 11
412
//
413
RAMB4_S2 ramb4_s2_11(
414
        .CLK(clk),
415
        .RST(rst),
416
        .ADDR(addr),
417
        .DI(di[23:22]),
418
        .EN(ce),
419
        .WE(we),
420
        .DO(do[23:22])
421
);
422
 
423
//
424
// Block 12
425
//
426
RAMB4_S2 ramb4_s2_12(
427
        .CLK(clk),
428
        .RST(rst),
429
        .ADDR(addr),
430
        .DI(di[25:24]),
431
        .EN(ce),
432
        .WE(we),
433
        .DO(do[25:24])
434
);
435
 
436
//
437
// Block 13
438
//
439
RAMB4_S2 ramb4_s2_13(
440
        .CLK(clk),
441
        .RST(rst),
442
        .ADDR(addr),
443
        .DI(di[27:26]),
444
        .EN(ce),
445
        .WE(we),
446
        .DO(do[27:26])
447
);
448
 
449
//
450
// Block 14
451
//
452
RAMB4_S2 ramb4_s2_14(
453
        .CLK(clk),
454
        .RST(rst),
455
        .ADDR(addr),
456
        .DI(di[29:28]),
457
        .EN(ce),
458
        .WE(we),
459
        .DO(do[29:28])
460
);
461
 
462
//
463
// Block 15
464
//
465
RAMB4_S2 ramb4_s2_15(
466
        .CLK(clk),
467
        .RST(rst),
468
        .ADDR(addr),
469
        .DI(di[31:30]),
470
        .EN(ce),
471
        .WE(we),
472
        .DO(do[31:30])
473
);
474
 
475
`else
476
 
477 1129 lampret
`ifdef OR1200_ALTERA_LPM
478
 
479 504 lampret
//
480 1129 lampret
// Instantiation of FPGA memory:
481
//
482
// Altera LPM
483
//
484
// Added By Jamil Khatib
485
//
486
 
487
wire    wr;
488
 
489
assign  wr = ce & we;
490
 
491
initial $display("Using Altera LPM.");
492
 
493
lpm_ram_dq lpm_ram_dq_component (
494
        .address(addr),
495
        .inclock(clk),
496
        .outclock(clk),
497
        .data(di),
498
        .we(wr),
499
        .q(do)
500
);
501
 
502
defparam lpm_ram_dq_component.lpm_width = dw,
503
        lpm_ram_dq_component.lpm_widthad = aw,
504
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
505
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
506
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
507
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
508
        // examplar attribute lpm_ram_dq_component NOOPT TRUE
509
 
510
`else
511
 
512
//
513 504 lampret
// Generic single-port synchronous RAM model
514
//
515
 
516
//
517
// Generic RAM's registers and wires
518
//
519
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
520
reg     [dw-1:0] do_reg;                 // RAM data output register
521
 
522
//
523
// Data output drivers
524
//
525 1129 lampret
assign do = (oe) ? do_reg : {dw{1'b0}};
526 504 lampret
 
527
//
528
// RAM read and write
529
//
530
always @(posedge clk)
531
        if (ce && !we)
532
                do_reg <= #1 mem[addr];
533
        else if (ce && we)
534
                mem[addr] <= #1 di;
535
 
536 1129 lampret
`endif  // !OR1200_ALTERA_LPM
537 504 lampret
`endif  // !OR1200_XILINX_RAMB4_S16
538
`endif  // !OR1200_VIRTUALSILICON_SSP
539
`endif  // !OR1200_VIRAGE_SSP
540
`endif  // !OR1200_AVANT_ATP
541
`endif  // !OR1200_ARTISAN_SSP
542
 
543
endmodule

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