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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM with byte write signals ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16                                   ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_2048x32_bw(
`ifdef OR1200_BIST
        // RAM BIST
        scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
);
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input                   scanb_rst,
                        scanb_si,
                        scanb_en,
                        scanb_clk;
output                  scanb_so;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input   [3:0]           we;     // Write enable input
input                   oe;     // Output enable input
input   [10:0]          addr;   // address bus inputs
input   [31:0]          di;     // input data bus
output  [31:0]          do;     // output data bus
 
//
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
`endif
`endif
`endif
 
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_2048x32_bw artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_2048x32_bw_bist artisan_ssp(
`else
art_hssp_2048x32_bw artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .scanb_rst(scanb_rst),
        .scanb_si(scanb_si),
        .scanb_so(scanb_so),
        .scanb_en(scanb_en),
        .scanb_clk(scanb_clk),
`endif
        .CLK(clk),
        .CEN(~ce),
        .WEN(~we),
        .A(addr),
        .D(di),
        .OEN(~oe),
        .Q(do)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(do)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef OR1200_BIST
wire scanb_si_ram_0;
wire scanb_si_ram_1;
wire scanb_si_ram_2;
wire scanb_si_ram_3;
wire scanb_so_ram_0;
wire scanb_so_ram_1;
wire scanb_so_ram_2;
wire scanb_so_ram_3;
assign scanb_si_ram_0 = scanb_si;
assign scanb_si_ram_1 = scanb_so_ram_0;
assign scanb_si_ram_2 = scanb_so_ram_1;
assign scanb_si_ram_3 = scanb_so_ram_2;
assign scanb_so = scanb_so_ram_3;
`endif
 
`ifdef UNUSED
vs_hdsp_2048x8 vs_ssp_0(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x8_bist vs_ssp_0(
`else
vs_hdsp_2048x8 vs_ssp_0(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .scanb_rst(scanb_rst),
        .scanb_si(scanb_si_ram_0),
        .scanb_so(scanb_so_ram_0),
        .scanb_en(scanb_en),
        .scanb_clk(scanb_clk),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[7:0]),
        .WEN(~we[0]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do[7:0])
);
 
`ifdef UNUSED
vs_hdsp_2048x8 vs_ssp_1(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x8_bist vs_ssp_1(
`else
vs_hdsp_2048x8 vs_ssp_1(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .scanb_rst(scanb_rst),
        .scanb_si(scanb_si_ram_1),
        .scanb_so(scanb_so_ram_1),
        .scanb_en(scanb_en),
        .scanb_clk(scanb_clk),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[15:8]),
        .WEN(~we[1]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do[15:8])
);
 
`ifdef UNUSED
vs_hdsp_2048x8 vs_ssp_2(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x8_bist vs_ssp_2(
`else
vs_hdsp_2048x8 vs_ssp_2(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .scanb_rst(scanb_rst),
        .scanb_si(scanb_si_ram_2),
        .scanb_so(scanb_so_ram_2),
        .scanb_en(scanb_en),
        .scanb_clk(scanb_clk),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[23:16]),
        .WEN(~we[2]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do[23:16])
);
 
`ifdef UNUSED
vs_hdsp_2048x8 vs_ssp_3(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x8_bist vs_ssp_3(
`else
vs_hdsp_2048x8 vs_ssp_3(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .scanb_rst(scanb_rst),
        .scanb_si(scanb_si_ram_3),
        .scanb_so(scanb_so_ram_3),
        .scanb_en(scanb_en),
        .scanb_clk(scanb_clk),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[31:24]),
        .WEN(~we[3]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do[31:24])
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S2 ramb4_s2_0(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[1:0]),
        .EN(ce),
        .WE(we[0]),
        .DO(do[1:0])
);
 
//
// Block 1
//
RAMB4_S2 ramb4_s2_1(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[3:2]),
        .EN(ce),
        .WE(we[0]),
        .DO(do[3:2])
);
 
//
// Block 2
//
RAMB4_S2 ramb4_s2_2(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[5:4]),
        .EN(ce),
        .WE(we[0]),
        .DO(do[5:4])
);
 
//
// Block 3
//
RAMB4_S2 ramb4_s2_3(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[7:6]),
        .EN(ce),
        .WE(we[0]),
        .DO(do[7:6])
//
// Block 4
//
RAMB4_S2 ramb4_s2_4(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[9:8]),
        .EN(ce),
        .WE(we[1]),
        .DO(do[9:8])
);
 
//
// Block 5
//
RAMB4_S2 ramb4_s2_5(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[11:10]),
        .EN(ce),
        .WE(we[1]),
        .DO(do[11:10])
);
 
//
// Block 6
//
RAMB4_S2 ramb4_s2_6(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[13:12]),
        .EN(ce),
        .WE(we[1]),
        .DO(do[13:12])
);
 
//
// Block 7
//
RAMB4_S2 ramb4_s2_7(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[15:14]),
        .EN(ce),
        .WE(we[1]),
        .DO(do[15:14])
 
//
// Block 8
//
RAMB4_S2 ramb4_s2_8(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[17:16]),
        .EN(ce),
        .WE(we[2]),
        .DO(do[17:16])
);
 
//
// Block 9
//
RAMB4_S2 ramb4_s2_9(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[19:18]),
        .EN(ce),
        .WE(we[2]),
        .DO(do[19:18])
);
 
//
// Block 10
//
RAMB4_S2 ramb4_s2_10(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[21:20]),
        .EN(ce),
        .WE(we[2]),
        .DO(do[21:20])
);
 
//
// Block 11
//
RAMB4_S2 ramb4_s2_11(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[23:22]),
        .EN(ce),
        .WE(we[2]),
        .DO(do[23:22])
//
// Block 12
//
RAMB4_S2 ramb4_s2_12(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[25:24]),
        .EN(ce),
        .WE(we[3]),
        .DO(do[25:24])
);
 
//
// Block 13
//
RAMB4_S2 ramb4_s2_13(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[27:26]),
        .EN(ce),
        .WE(we[3]),
        .DO(do[27:26])
);
 
//
// Block 14
//
RAMB4_S2 ramb4_s2_14(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[29:28]),
        .EN(ce),
        .WE(we[3]),
        .DO(do[29:28])
);
 
//
// Block 15
//
RAMB4_S2 ramb4_s2_15(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[31:30]),
        .EN(ce),
        .WE(we[3]),
        .DO(do[31:30])
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [31:0]        mem_0 [10:0];              // RAM content
reg     [31:0]        mem_1 [10:0];              // RAM content
reg     [31:0]        mem_2 [10:0];              // RAM content
reg     [31:0]        mem_3 [10:0];              // RAM content
reg     [31:0]        do_reg;                 // RAM data output register
 
//
// Data output drivers
//
assign do = (oe) ? do_reg : {32{1'b0}};
 
//
// RAM read and write
//
always @(posedge clk)
        if (ce && !we) begin
                do_reg[7:0]   <= #1 mem_0[addr];
                do_reg[15:8]  <= #1 mem_1[addr];
                do_reg[23:16] <= #1 mem_2[addr];
                do_reg[31:24] <= #1 mem_3[addr];
        end
        else if (ce && we[0])
                mem_0[addr] <= #1 di[7:0];
        else if (ce && we[1])
                mem_1[addr] <= #1 di[15:8];
        else if (ce && we[2])
                mem_2[addr] <= #1 di[23:16];
        else if (ce && we[3])
                mem_3[addr] <= #1 di[31:24];
 
`endif  // !OR1200_XILINX_RAMB4_S16
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x32_bw.v] - Blame information for rev 1186

Line No.	Rev	Author	Line
1	1186	simons	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM with byte write signals ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB4_S16 ////`
26			`//// - Altera LPM ////`
27			`//// ////`
28			`//// To Do: ////`
29			`//// - xilinx rams need external tri-state logic ////`
30			`//// - fix avant! two-port ram ////`
31			`//// - add additional RAMs ////`
32			`//// ////`
33			`//// Author(s): ////`
34			`//// - Damjan Lampret, lampret@opencores.org ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//// ////`
38			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
39			`//// ////`
40			`//// This source file may be used and distributed without ////`
41			`//// restriction provided that this copyright statement is not ////`
42			`//// removed from the file and that any derivative work contains ////`
43			`//// the original copyright notice and the associated disclaimer. ////`
44			`//// ////`
45			`//// This source file is free software; you can redistribute it ////`
46			`//// and/or modify it under the terms of the GNU Lesser General ////`
47			`//// Public License as published by the Free Software Foundation; ////`
48			`//// either version 2.1 of the License, or (at your option) any ////`
49			`//// later version. ////`
50			`//// ////`
51			`//// This source is distributed in the hope that it will be ////`
52			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
53			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
54			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
55			`//// details. ////`
56			`//// ////`
57			`//// You should have received a copy of the GNU Lesser General ////`
58			`//// Public License along with this source; if not, download it ////`
59			`//// from http://www.opencores.org/lgpl.shtml ////`
60			`//// ////`
61			`//////////////////////////////////////////////////////////////////////`
62			`//`
63			`// CVS Revision History`
64			`//`
65			`// $Log: not supported by cvs2svn $`
66			`//`
67
68			`// synopsys translate_off`
69			`include "timescale.v"
70			`// synopsys translate_on`
71			`include "or1200_defines.v"
72
73			`module or1200_spram_2048x32_bw(`
74			`ifdef OR1200_BIST
75			`// RAM BIST`
76			`scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,`
77			`endif
78			`// Generic synchronous single-port RAM interface`
79			`clk, rst, ce, we, oe, addr, di, do`
80			`);`
81
82			`ifdef OR1200_BIST
83			`//`
84			`// RAM BIST`
85			`//`
86			`input scanb_rst,`
87			`scanb_si,`
88			`scanb_en,`
89			`scanb_clk;`
90			`output scanb_so;`
91			`endif
92
93			`//`
94			`// Generic synchronous single-port RAM interface`
95			`//`
96			`input clk; // Clock`
97			`input rst; // Reset`
98			`input ce; // Chip enable input`
99			`input [3:0] we; // Write enable input`
100			`input oe; // Output enable input`
101			`input [10:0] addr; // address bus inputs`
102			`input [31:0] di; // input data bus`
103			`output [31:0] do; // output data bus`
104
105			`//`
106			`// Internal wires and registers`
107			`//`
108
109			`ifdef OR1200_ARTISAN_SSP
110			`else
111			`ifdef OR1200_VIRTUALSILICON_SSP
112			`else
113			`ifdef OR1200_BIST
114			`assign scanb_so = scanb_si;`
115			`endif
116			`endif
117			`endif
118
119
120			`ifdef OR1200_ARTISAN_SSP
121
122			`//`
123			`// Instantiation of ASIC memory:`
124			`//`
125			`// Artisan Synchronous Single-Port RAM (ra1sh)`
126			`//`
127			`ifdef UNUSED
128			`art_hssp_2048x32_bw artisan_ssp(`
129			`else
130			`ifdef OR1200_BIST
131			`art_hssp_2048x32_bw_bist artisan_ssp(`
132			`else
133			`art_hssp_2048x32_bw artisan_ssp(`
134			`endif
135			`endif
136			`ifdef OR1200_BIST
137			`// RAM BIST`
138			`.scanb_rst(scanb_rst),`
139			`.scanb_si(scanb_si),`
140			`.scanb_so(scanb_so),`
141			`.scanb_en(scanb_en),`
142			`.scanb_clk(scanb_clk),`
143			`endif
144			`.CLK(clk),`
145			`.CEN(~ce),`
146			`.WEN(~we),`
147			`.A(addr),`
148			`.D(di),`
149			`.OEN(~oe),`
150			`.Q(do)`
151			`);`
152
153			`else
154
155			`ifdef OR1200_AVANT_ATP
156
157			`//`
158			`// Instantiation of ASIC memory:`
159			`//`
160			`// Avant! Asynchronous Two-Port RAM`
161			`//`
162			`avant_atp avant_atp(`
163			`.web(~we),`
164			`.reb(),`
165			`.oeb(~oe),`
166			`.rcsb(),`
167			`.wcsb(),`
168			`.ra(addr),`
169			`.wa(addr),`
170			`.di(di),`
171			`.do(do)`
172			`);`
173
174			`else
175
176			`ifdef OR1200_VIRAGE_SSP
177
178			`//`
179			`// Instantiation of ASIC memory:`
180			`//`
181			`// Virage Synchronous 1-port R/W RAM`
182			`//`
183			`virage_ssp virage_ssp(`
184			`.clk(clk),`
185			`.adr(addr),`
186			`.d(di),`
187			`.we(we),`
188			`.oe(oe),`
189			`.me(ce),`
190			`.q(do)`
191			`);`
192
193			`else
194
195			`ifdef OR1200_VIRTUALSILICON_SSP
196
197			`//`
198			`// Instantiation of ASIC memory:`
199			`//`
200			`// Virtual Silicon Single-Port Synchronous SRAM`
201			`//`
202			`ifdef OR1200_BIST
203			`wire scanb_si_ram_0;`
204			`wire scanb_si_ram_1;`
205			`wire scanb_si_ram_2;`
206			`wire scanb_si_ram_3;`
207			`wire scanb_so_ram_0;`
208			`wire scanb_so_ram_1;`
209			`wire scanb_so_ram_2;`
210			`wire scanb_so_ram_3;`
211			`assign scanb_si_ram_0 = scanb_si;`
212			`assign scanb_si_ram_1 = scanb_so_ram_0;`
213			`assign scanb_si_ram_2 = scanb_so_ram_1;`
214			`assign scanb_si_ram_3 = scanb_so_ram_2;`
215			`assign scanb_so = scanb_so_ram_3;`
216			`endif
217
218			`ifdef UNUSED
219			`vs_hdsp_2048x8 vs_ssp_0(`
220			`else
221			`ifdef OR1200_BIST
222			`vs_hdsp_2048x8_bist vs_ssp_0(`
223			`else
224			`vs_hdsp_2048x8 vs_ssp_0(`
225			`endif
226			`endif
227			`ifdef OR1200_BIST
228			`// RAM BIST`
229			`.scanb_rst(scanb_rst),`
230			`.scanb_si(scanb_si_ram_0),`
231			`.scanb_so(scanb_so_ram_0),`
232			`.scanb_en(scanb_en),`
233			`.scanb_clk(scanb_clk),`
234			`endif
235			`.CK(clk),`
236			`.ADR(addr),`
237			`.DI(di[7:0]),`
238			`.WEN(~we[0]),`
239			`.CEN(~ce),`
240			`.OEN(~oe),`
241			`.DOUT(do[7:0])`
242			`);`
243
244			`ifdef UNUSED
245			`vs_hdsp_2048x8 vs_ssp_1(`
246			`else
247			`ifdef OR1200_BIST
248			`vs_hdsp_2048x8_bist vs_ssp_1(`
249			`else
250			`vs_hdsp_2048x8 vs_ssp_1(`
251			`endif
252			`endif
253			`ifdef OR1200_BIST
254			`// RAM BIST`
255			`.scanb_rst(scanb_rst),`
256			`.scanb_si(scanb_si_ram_1),`
257			`.scanb_so(scanb_so_ram_1),`
258			`.scanb_en(scanb_en),`
259			`.scanb_clk(scanb_clk),`
260			`endif
261			`.CK(clk),`
262			`.ADR(addr),`
263			`.DI(di[15:8]),`
264			`.WEN(~we[1]),`
265			`.CEN(~ce),`
266			`.OEN(~oe),`
267			`.DOUT(do[15:8])`
268			`);`
269
270			`ifdef UNUSED
271			`vs_hdsp_2048x8 vs_ssp_2(`
272			`else
273			`ifdef OR1200_BIST
274			`vs_hdsp_2048x8_bist vs_ssp_2(`
275			`else
276			`vs_hdsp_2048x8 vs_ssp_2(`
277			`endif
278			`endif
279			`ifdef OR1200_BIST
280			`// RAM BIST`
281			`.scanb_rst(scanb_rst),`
282			`.scanb_si(scanb_si_ram_2),`
283			`.scanb_so(scanb_so_ram_2),`
284			`.scanb_en(scanb_en),`
285			`.scanb_clk(scanb_clk),`
286			`endif
287			`.CK(clk),`
288			`.ADR(addr),`
289			`.DI(di[23:16]),`
290			`.WEN(~we[2]),`
291			`.CEN(~ce),`
292			`.OEN(~oe),`
293			`.DOUT(do[23:16])`
294			`);`
295
296			`ifdef UNUSED
297			`vs_hdsp_2048x8 vs_ssp_3(`
298			`else
299			`ifdef OR1200_BIST
300			`vs_hdsp_2048x8_bist vs_ssp_3(`
301			`else
302			`vs_hdsp_2048x8 vs_ssp_3(`
303			`endif
304			`endif
305			`ifdef OR1200_BIST
306			`// RAM BIST`
307			`.scanb_rst(scanb_rst),`
308			`.scanb_si(scanb_si_ram_3),`
309			`.scanb_so(scanb_so_ram_3),`
310			`.scanb_en(scanb_en),`
311			`.scanb_clk(scanb_clk),`
312			`endif
313			`.CK(clk),`
314			`.ADR(addr),`
315			`.DI(di[31:24]),`
316			`.WEN(~we[3]),`
317			`.CEN(~ce),`
318			`.OEN(~oe),`
319			`.DOUT(do[31:24])`
320			`);`
321
322			`else
323
324			`ifdef OR1200_XILINX_RAMB4
325
326			`//`
327			`// Instantiation of FPGA memory:`
328			`//`
329			`// Virtex/Spartan2`
330			`//`
331
332			`//`
333			`// Block 0`
334			`//`
335			`RAMB4_S2 ramb4_s2_0(`
336			`.CLK(clk),`
337			`.RST(rst),`
338			`.ADDR(addr),`
339			`.DI(di[1:0]),`
340			`.EN(ce),`
341			`.WE(we[0]),`
342			`.DO(do[1:0])`
343			`);`
344
345			`//`
346			`// Block 1`
347			`//`
348			`RAMB4_S2 ramb4_s2_1(`
349			`.CLK(clk),`
350			`.RST(rst),`
351			`.ADDR(addr),`
352			`.DI(di[3:2]),`
353			`.EN(ce),`
354			`.WE(we[0]),`
355			`.DO(do[3:2])`
356			`);`
357
358			`//`
359			`// Block 2`
360			`//`
361			`RAMB4_S2 ramb4_s2_2(`
362			`.CLK(clk),`
363			`.RST(rst),`
364			`.ADDR(addr),`
365			`.DI(di[5:4]),`
366			`.EN(ce),`
367			`.WE(we[0]),`
368			`.DO(do[5:4])`
369			`);`
370
371			`//`
372			`// Block 3`
373			`//`
374			`RAMB4_S2 ramb4_s2_3(`
375			`.CLK(clk),`
376			`.RST(rst),`
377			`.ADDR(addr),`
378			`.DI(di[7:6]),`
379			`.EN(ce),`
380			`.WE(we[0]),`
381			`.DO(do[7:6])`
382			`//`
383			`// Block 4`
384			`//`
385			`RAMB4_S2 ramb4_s2_4(`
386			`.CLK(clk),`
387			`.RST(rst),`
388			`.ADDR(addr),`
389			`.DI(di[9:8]),`
390			`.EN(ce),`
391			`.WE(we[1]),`
392			`.DO(do[9:8])`
393			`);`
394
395			`//`
396			`// Block 5`
397			`//`
398			`RAMB4_S2 ramb4_s2_5(`
399			`.CLK(clk),`
400			`.RST(rst),`
401			`.ADDR(addr),`
402			`.DI(di[11:10]),`
403			`.EN(ce),`
404			`.WE(we[1]),`
405			`.DO(do[11:10])`
406			`);`
407
408			`//`
409			`// Block 6`
410			`//`
411			`RAMB4_S2 ramb4_s2_6(`
412			`.CLK(clk),`
413			`.RST(rst),`
414			`.ADDR(addr),`
415			`.DI(di[13:12]),`
416			`.EN(ce),`
417			`.WE(we[1]),`
418			`.DO(do[13:12])`
419			`);`
420
421			`//`
422			`// Block 7`
423			`//`
424			`RAMB4_S2 ramb4_s2_7(`
425			`.CLK(clk),`
426			`.RST(rst),`
427			`.ADDR(addr),`
428			`.DI(di[15:14]),`
429			`.EN(ce),`
430			`.WE(we[1]),`
431			`.DO(do[15:14])`
432
433			`//`
434			`// Block 8`
435			`//`
436			`RAMB4_S2 ramb4_s2_8(`
437			`.CLK(clk),`
438			`.RST(rst),`
439			`.ADDR(addr),`
440			`.DI(di[17:16]),`
441			`.EN(ce),`
442			`.WE(we[2]),`
443			`.DO(do[17:16])`
444			`);`
445
446			`//`
447			`// Block 9`
448			`//`
449			`RAMB4_S2 ramb4_s2_9(`
450			`.CLK(clk),`
451			`.RST(rst),`
452			`.ADDR(addr),`
453			`.DI(di[19:18]),`
454			`.EN(ce),`
455			`.WE(we[2]),`
456			`.DO(do[19:18])`
457			`);`
458
459			`//`
460			`// Block 10`
461			`//`
462			`RAMB4_S2 ramb4_s2_10(`
463			`.CLK(clk),`
464			`.RST(rst),`
465			`.ADDR(addr),`
466			`.DI(di[21:20]),`
467			`.EN(ce),`
468			`.WE(we[2]),`
469			`.DO(do[21:20])`
470			`);`
471
472			`//`
473			`// Block 11`
474			`//`
475			`RAMB4_S2 ramb4_s2_11(`
476			`.CLK(clk),`
477			`.RST(rst),`
478			`.ADDR(addr),`
479			`.DI(di[23:22]),`
480			`.EN(ce),`
481			`.WE(we[2]),`
482			`.DO(do[23:22])`
483			`//`
484			`// Block 12`
485			`//`
486			`RAMB4_S2 ramb4_s2_12(`
487			`.CLK(clk),`
488			`.RST(rst),`
489			`.ADDR(addr),`
490			`.DI(di[25:24]),`
491			`.EN(ce),`
492			`.WE(we[3]),`
493			`.DO(do[25:24])`
494			`);`
495
496			`//`
497			`// Block 13`
498			`//`
499			`RAMB4_S2 ramb4_s2_13(`
500			`.CLK(clk),`
501			`.RST(rst),`
502			`.ADDR(addr),`
503			`.DI(di[27:26]),`
504			`.EN(ce),`
505			`.WE(we[3]),`
506			`.DO(do[27:26])`
507			`);`
508
509			`//`
510			`// Block 14`
511			`//`
512			`RAMB4_S2 ramb4_s2_14(`
513			`.CLK(clk),`
514			`.RST(rst),`
515			`.ADDR(addr),`
516			`.DI(di[29:28]),`
517			`.EN(ce),`
518			`.WE(we[3]),`
519			`.DO(do[29:28])`
520			`);`
521
522			`//`
523			`// Block 15`
524			`//`
525			`RAMB4_S2 ramb4_s2_15(`
526			`.CLK(clk),`
527			`.RST(rst),`
528			`.ADDR(addr),`
529			`.DI(di[31:30]),`
530			`.EN(ce),`
531			`.WE(we[3]),`
532			`.DO(do[31:30])`
533
534			`else
535
536			`//`
537			`// Generic single-port synchronous RAM model`
538			`//`
539
540			`//`
541			`// Generic RAM's registers and wires`
542			`//`
543			`reg [31:0] mem_0 [10:0]; // RAM content`
544			`reg [31:0] mem_1 [10:0]; // RAM content`
545			`reg [31:0] mem_2 [10:0]; // RAM content`
546			`reg [31:0] mem_3 [10:0]; // RAM content`
547			`reg [31:0] do_reg; // RAM data output register`
548
549			`//`
550			`// Data output drivers`
551			`//`
552			`assign do = (oe) ? do_reg : {32{1'b0}};`
553
554			`//`
555			`// RAM read and write`
556			`//`
557			`always @(posedge clk)`
558			`if (ce && !we) begin`
559			`do_reg[7:0] <= #1 mem_0[addr];`
560			`do_reg[15:8] <= #1 mem_1[addr];`
561			`do_reg[23:16] <= #1 mem_2[addr];`
562			`do_reg[31:24] <= #1 mem_3[addr];`
563			`end`
564			`else if (ce && we[0])`
565			`mem_0[addr] <= #1 di[7:0];`
566			`else if (ce && we[1])`
567			`mem_1[addr] <= #1 di[15:8];`
568			`else if (ce && we[2])`
569			`mem_2[addr] <= #1 di[23:16];`
570			`else if (ce && we[3])`
571			`mem_3[addr] <= #1 di[31:24];`
572
573			`endif // !OR1200_XILINX_RAMB4_S16
574			`endif // !OR1200_VIRTUALSILICON_SSP
575			`endif // !OR1200_VIRAGE_SSP
576			`endif // !OR1200_AVANT_ATP
577			`endif // !OR1200_ARTISAN_SSP
578
579			`endmodule`