URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_spram_64x24.v] - Blame information for rev 1765

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16                                   ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2003/04/07 01:19:07  lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2  2002/10/17 20:04:41  lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8  2001/11/02 18:57:14  lampret
// Modified virtual silicon instantiations.
//
// Revision 1.7  2001/10/22 19:39:56  lampret
// Fixed parameters in generic sprams.
//
// Revision 1.6  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_64x24(
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
);
 
//
// Default address and data buses width
//
parameter aw = 6;
parameter dw = 24;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] do;     // output data bus
 
//
// Internal wires and registers
//
wire    [7:0]            unconnected;
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_64x24 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_64x24_bist artisan_ssp(
`else
art_hssp_64x24 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CLK(clk),
        .CEN(~ce),
        .WEN(~we),
        .A(addr),
        .D(di),
        .OEN(~oe),
        .Q(do)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(do)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_64x24 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_64x24_bist vs_ssp(
`else
vs_hdsp_64x24 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di),
        .WEN(~we),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
        .CLK(clk),
        .RST(rst),
        .ADDR({2'b00, addr}),
        .DI(di[15:0]),
        .EN(ce),
        .WE(we),
        .DO(do[15:0])
);
 
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
        .CLK(clk),
        .RST(rst),
        .ADDR({2'b00, addr}),
        .DI({unconnected, di[23:16]}),
        .EN(ce),
        .WE(we),
        .DO({unconnected, do[23:16]})
);
 
`else
 
`ifdef OR1200_ALTERA_LPM
 
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
 
wire    wr;
 
assign  wr = ce & we;
 
initial $display("Using Altera LPM.");
 
lpm_ram_dq lpm_ram_dq_component (
        .address(addr),
        .inclock(clk),
        .outclock(clk),
        .data(di),
        .we(wr),
        .q(do)
);
 
defparam lpm_ram_dq_component.lpm_width = dw,
        lpm_ram_dq_component.lpm_widthad = aw,
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
        // examplar attribute lpm_ram_dq_component NOOPT TRUE
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [dw-1:0] do_reg;                 // RAM data output register
 
//
// Data output drivers
//
assign do = (oe) ? do_reg : {dw{1'b0}};
 
//
// RAM read and write
//
always @(posedge clk)
        if (ce && !we)
                do_reg <= #1 mem[addr];
        else if (ce && we)
                mem[addr] <= #1 di;
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB4_S16
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB4_S16 ////`
26	1129	lampret	`//// - Altera LPM ////`
27	504	lampret	`//// ////`
28			`//// To Do: ////`
29			`//// - xilinx rams need external tri-state logic ////`
30			`//// - fix avant! two-port ram ////`
31	1129	lampret	`//// - add additional RAMs ////`
32	504	lampret	`//// ////`
33			`//// Author(s): ////`
34			`//// - Damjan Lampret, lampret@opencores.org ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//// ////`
38			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
39			`//// ////`
40			`//// This source file may be used and distributed without ////`
41			`//// restriction provided that this copyright statement is not ////`
42			`//// removed from the file and that any derivative work contains ////`
43			`//// the original copyright notice and the associated disclaimer. ////`
44			`//// ////`
45			`//// This source file is free software; you can redistribute it ////`
46			`//// and/or modify it under the terms of the GNU Lesser General ////`
47			`//// Public License as published by the Free Software Foundation; ////`
48			`//// either version 2.1 of the License, or (at your option) any ////`
49			`//// later version. ////`
50			`//// ////`
51			`//// This source is distributed in the hope that it will be ////`
52			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
53			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
54			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
55			`//// details. ////`
56			`//// ////`
57			`//// You should have received a copy of the GNU Lesser General ////`
58			`//// Public License along with this source; if not, download it ////`
59			`//// from http://www.opencores.org/lgpl.shtml ////`
60			`//// ////`
61			`//////////////////////////////////////////////////////////////////////`
62			`//`
63			`// CVS Revision History`
64			`//`
65			`// $Log: not supported by cvs2svn $`
66	1214	simons	`// Revision 1.3 2003/04/07 01:19:07 lampret`
67			`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`
68			`//`
69	1129	lampret	`// Revision 1.2 2002/10/17 20:04:41 lampret`
70			`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
71			`//`
72	1063	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
73			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
74			`//`
75	504	lampret	`// Revision 1.8 2001/11/02 18:57:14 lampret`
76			`// Modified virtual silicon instantiations.`
77			`//`
78			`// Revision 1.7 2001/10/22 19:39:56 lampret`
79			`// Fixed parameters in generic sprams.`
80			`//`
81			`// Revision 1.6 2001/10/21 17:57:16 lampret`
82			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
83			`//`
84			`// Revision 1.5 2001/10/14 13:12:09 lampret`
85			`// MP3 version.`
86			`//`
87			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
88			`// no message`
89			`//`
90			`// Revision 1.1 2001/08/09 13:39:33 lampret`
91			`// Major clean-up.`
92			`//`
93			`// Revision 1.2 2001/07/30 05:38:02 lampret`
94			`// Adding empty directories required by HDL coding guidelines`
95			`//`
96			`//`
97
98			`// synopsys translate_off`
99			`include "timescale.v"
100			`// synopsys translate_on`
101			`include "or1200_defines.v"
102
103			`module or1200_spram_64x24(`
104	1063	lampret	`ifdef OR1200_BIST
105			`// RAM BIST`
106	1214	simons	`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
107	1063	lampret	`endif
108	504	lampret	`// Generic synchronous single-port RAM interface`
109			`clk, rst, ce, we, oe, addr, di, do`
110			`);`
111
112			`//`
113			`// Default address and data buses width`
114			`//`
115			`parameter aw = 6;`
116			`parameter dw = 24;`
117
118	1063	lampret	`ifdef OR1200_BIST
119	504	lampret	`//`
120	1063	lampret	`// RAM BIST`
121			`//`
122	1214	simons	`input mbist_si_i;`
123			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
124			`output mbist_so_o;`
125	1063	lampret	`endif
126
127			`//`
128	504	lampret	`// Generic synchronous single-port RAM interface`
129			`//`
130			`input clk; // Clock`
131			`input rst; // Reset`
132			`input ce; // Chip enable input`
133			`input we; // Write enable input`
134			`input oe; // Output enable input`
135			`input [aw-1:0] addr; // address bus inputs`
136			`input [dw-1:0] di; // input data bus`
137			`output [dw-1:0] do; // output data bus`
138
139			`//`
140			`// Internal wires and registers`
141			`//`
142			`wire [7:0] unconnected;`
143
144	1214	simons	`ifdef OR1200_ARTISAN_SSP
145			`else
146	1063	lampret	`ifdef OR1200_VIRTUALSILICON_SSP
147			`else
148			`ifdef OR1200_BIST
149	1214	simons	`assign mbist_so_o = mbist_si_i;`
150	1063	lampret	`endif
151			`endif
152	1214	simons	`endif
153	1063	lampret
154	504	lampret	`ifdef OR1200_ARTISAN_SSP
155
156			`//`
157			`// Instantiation of ASIC memory:`
158			`//`
159			`// Artisan Synchronous Single-Port RAM (ra1sh)`
160			`//`
161			`ifdef UNUSED
162			`art_hssp_64x24 #(dw, 1<<aw, aw) artisan_ssp(`
163			`else
164	1214	simons	`ifdef OR1200_BIST
165			`art_hssp_64x24_bist artisan_ssp(`
166			`else
167	504	lampret	`art_hssp_64x24 artisan_ssp(`
168			`endif
169	1214	simons	`endif
170			`ifdef OR1200_BIST
171			`// RAM BIST`
172			`.mbist_si_i(mbist_si_i),`
173			`.mbist_so_o(mbist_so_o),`
174			`.mbist_ctrl_i(mbist_ctrl_i),`
175			`endif
176			`.CLK(clk),`
177			`.CEN(~ce),`
178			`.WEN(~we),`
179			`.A(addr),`
180			`.D(di),`
181			`.OEN(~oe),`
182			`.Q(do)`
183	504	lampret	`);`
184
185			`else
186
187			`ifdef OR1200_AVANT_ATP
188
189			`//`
190			`// Instantiation of ASIC memory:`
191			`//`
192			`// Avant! Asynchronous Two-Port RAM`
193			`//`
194			`avant_atp avant_atp(`
195			`.web(~we),`
196			`.reb(),`
197			`.oeb(~oe),`
198			`.rcsb(),`
199			`.wcsb(),`
200			`.ra(addr),`
201			`.wa(addr),`
202			`.di(di),`
203			`.do(do)`
204			`);`
205
206			`else
207
208			`ifdef OR1200_VIRAGE_SSP
209
210			`//`
211			`// Instantiation of ASIC memory:`
212			`//`
213			`// Virage Synchronous 1-port R/W RAM`
214			`//`
215			`virage_ssp virage_ssp(`
216			`.clk(clk),`
217			`.adr(addr),`
218			`.d(di),`
219			`.we(we),`
220			`.oe(oe),`
221			`.me(ce),`
222			`.q(do)`
223			`);`
224
225			`else
226
227			`ifdef OR1200_VIRTUALSILICON_SSP
228
229			`//`
230			`// Instantiation of ASIC memory:`
231			`//`
232			`// Virtual Silicon Single-Port Synchronous SRAM`
233			`//`
234			`ifdef UNUSED
235			`vs_hdsp_64x24 #(1<<aw, aw-1, dw-1) vs_ssp(`
236			`else
237	1063	lampret	`ifdef OR1200_BIST
238			`vs_hdsp_64x24_bist vs_ssp(`
239			`else
240	504	lampret	`vs_hdsp_64x24 vs_ssp(`
241			`endif
242	1063	lampret	`endif
243			`ifdef OR1200_BIST
244			`// RAM BIST`
245	1214	simons	`.mbist_si_i(mbist_si_i),`
246			`.mbist_so_o(mbist_so_o),`
247			`.mbist_ctrl_i(mbist_ctrl_i),`
248	1063	lampret	`endif
249	504	lampret	`.CK(clk),`
250			`.ADR(addr),`
251			`.DI(di),`
252			`.WEN(~we),`
253			`.CEN(~ce),`
254			`.OEN(~oe),`
255			`.DOUT(do)`
256			`);`
257
258			`else
259
260			`ifdef OR1200_XILINX_RAMB4
261
262			`//`
263			`// Instantiation of FPGA memory:`
264			`//`
265			`// Virtex/Spartan2`
266			`//`
267
268			`//`
269			`// Block 0`
270			`//`
271			`RAMB4_S16 ramb4_s16_0(`
272			`.CLK(clk),`
273			`.RST(rst),`
274			`.ADDR({2'b00, addr}),`
275			`.DI(di[15:0]),`
276			`.EN(ce),`
277			`.WE(we),`
278			`.DO(do[15:0])`
279			`);`
280
281			`//`
282			`// Block 1`
283			`//`
284			`RAMB4_S16 ramb4_s16_1(`
285			`.CLK(clk),`
286			`.RST(rst),`
287			`.ADDR({2'b00, addr}),`
288			`.DI({unconnected, di[23:16]}),`
289			`.EN(ce),`
290			`.WE(we),`
291			`.DO({unconnected, do[23:16]})`
292			`);`
293
294			`else
295
296	1129	lampret	`ifdef OR1200_ALTERA_LPM
297
298	504	lampret	`//`
299	1129	lampret	`// Instantiation of FPGA memory:`
300			`//`
301			`// Altera LPM`
302			`//`
303			`// Added By Jamil Khatib`
304			`//`
305
306			`wire wr;`
307
308			`assign wr = ce & we;`
309
310			`initial $display("Using Altera LPM.");`
311
312			`lpm_ram_dq lpm_ram_dq_component (`
313			`.address(addr),`
314			`.inclock(clk),`
315			`.outclock(clk),`
316			`.data(di),`
317			`.we(wr),`
318			`.q(do)`
319			`);`
320
321			`defparam lpm_ram_dq_component.lpm_width = dw,`
322			`lpm_ram_dq_component.lpm_widthad = aw,`
323			`lpm_ram_dq_component.lpm_indata = "REGISTERED",`
324			`lpm_ram_dq_component.lpm_address_control = "REGISTERED",`
325			`lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",`
326			`lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";`
327			`// examplar attribute lpm_ram_dq_component NOOPT TRUE`
328
329			`else
330
331			`//`
332	504	lampret	`// Generic single-port synchronous RAM model`
333			`//`
334
335			`//`
336			`// Generic RAM's registers and wires`
337			`//`
338			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
339			`reg [dw-1:0] do_reg; // RAM data output register`
340
341			`//`
342			`// Data output drivers`
343			`//`
344	1129	lampret	`assign do = (oe) ? do_reg : {dw{1'b0}};`
345	504	lampret
346			`//`
347			`// RAM read and write`
348			`//`
349			`always @(posedge clk)`
350			`if (ce && !we)`
351			`do_reg <= #1 mem[addr];`
352			`else if (ce && we)`
353			`mem[addr] <= #1 di;`
354
355	1129	lampret	`endif // !OR1200_ALTERA_LPM
356	504	lampret	`endif // !OR1200_XILINX_RAMB4_S16
357			`endif // !OR1200_VIRTUALSILICON_SSP
358			`endif // !OR1200_VIRAGE_SSP
359			`endif // !OR1200_AVANT_ATP
360			`endif // !OR1200_ARTISAN_SSP
361
362			`endmodule`

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_spram_64x24.v] - Blame information for rev 1765