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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_wb_biu.v] - Blame information for rev 895

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's WISHBONE BIU                                       ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Implements WISHBONE interface                               ////
////                                                              ////
////  To Do:                                                      ////
////   - add support for wb_err_i                                 ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.12  2001/11/22 13:42:51  lampret
// Added wb_cyc_o assignment after it was removed by accident.
//
// Revision 1.11  2001/11/20 21:28:10  lampret
// Added optional sampling of inputs.
//
// Revision 1.10  2001/11/18 11:32:00  lampret
// OR1200_REGISTERED_OUTPUTS can now be enabled.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/14 13:12:10  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.3  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/22 03:31:54  lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1  2001/07/20 00:46:23  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_wb_biu(
        // RISC clock, reset and clock control
        clk, rst, clmode,
 
        // WISHBONE interface
        wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,
        wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_cab_o, wb_dat_o,
 
        // Internal RISC bus
        biu_dat_i, biu_adr_i, biu_cyc_i, biu_stb_i, biu_we_i, biu_sel_i, biu_cab_i,
        biu_dat_o, biu_ack_o, biu_err_o
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
 
//
// RISC clock, reset and clock control
//
input                   clk;            // RISC clock
input                   rst;            // RISC reset
input   [1:0]            clmode;         // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
 
//
// WISHBONE interface
//
input                   wb_clk_i;       // clock input
input                   wb_rst_i;       // reset input
input                   wb_ack_i;       // normal termination
input                   wb_err_i;       // termination w/ error
input                   wb_rty_i;       // termination w/ retry
input   [dw-1:0] wb_dat_i;       // input data bus
output                  wb_cyc_o;       // cycle valid output
output  [aw-1:0] wb_adr_o;       // address bus outputs
output                  wb_stb_o;       // strobe output
output                  wb_we_o;        // indicates write transfer
output  [3:0]            wb_sel_o;       // byte select outputs
output                  wb_cab_o;       // consecutive address burst
output  [dw-1:0] wb_dat_o;       // output data bus
 
//
// Internal RISC interface
//
input   [dw-1:0] biu_dat_i;      // input data bus
input   [aw-1:0] biu_adr_i;      // address bus
input                   biu_cyc_i;      // WB cycle
input                   biu_stb_i;      // WB strobe
input                   biu_we_i;       // WB write enable
input                   biu_cab_i;      // CAB input
input   [3:0]            biu_sel_i;      // byte selects
output  [31:0]           biu_dat_o;      // output data bus
output                  biu_ack_o;      // ack output
output                  biu_err_o;      // err output
 
//
// Registers
//
reg     [1:0]            valid_div;      // Used for synchronization
`ifdef OR1200_REGISTERED_OUTPUTS
reg     [aw-1:0] wb_adr_o;       // address bus outputs
reg                     wb_cyc_o;       // cycle output
reg                     wb_stb_o;       // strobe output
reg                     wb_we_o;        // indicates write transfer
reg     [3:0]            wb_sel_o;       // byte select outputs
reg                     wb_cab_o;       // CAB output
reg     [dw-1:0] wb_dat_o;       // output data bus
`endif
`ifdef OR1200_REGISTERED_INPUTS
reg                     long_ack_o;     // normal termination
reg                     long_err_o;     // error termination
reg     [dw-1:0] biu_dat_o;      // output data bus
`else
wire                    long_ack_o;     // normal termination
wire                    long_err_o;     // error termination
`endif
 
//
// WISHBONE I/F <-> Internal RISC I/F conversion
//
 
//
// Address bus
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_adr_o <= #1 {aw{1'b0}};
        else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i)
                wb_adr_o <= #1 biu_adr_i;
`else
assign wb_adr_o = biu_adr_i;
`endif
 
//
// Input data bus
//
`ifdef OR1200_REGISTERED_INPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                biu_dat_o <= #1 32'h0000_0000;
        else if (wb_ack_i)
                biu_dat_o <= #1 wb_dat_i;
`else
assign biu_dat_o = wb_dat_i;
`endif
 
//
// Output data bus
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_dat_o <= #1 {dw{1'b0}};
        else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i)
                wb_dat_o <= #1 biu_dat_i;
`else
assign wb_dat_o = biu_dat_i;
`endif
 
//
// Valid_div counts RISC clock cycles by modulo 4
// and is used to synchronize external WB i/f to
// RISC clock
//
always @(posedge clk or posedge rst)
        if (rst)
                valid_div <= #1 2'b0;
        else
                valid_div <= #1 valid_div + 'd1;
 
//
// biu_ack_o is one RISC clock cycle long long_ack_o.
// long_ack_o is one, two or four RISC clock cycles long because
// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.
//
assign biu_ack_o = long_ack_o
`ifdef OR1200_CLKDIV_4_SUPPORTED
                & (valid_div[1] | ~clmode[1])
`ifdef OR1200_CLKDIV_2_SUPPORTED
                & (valid_div[0] | ~clmode[0])
`endif
`endif
                ;
 
//
// Acknowledgment of the data to the RISC
//
// long_ack_o
//
`ifdef OR1200_REGISTERED_INPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                long_ack_o <= #1 1'b0;
        else
                long_ack_o <= #1 wb_ack_i;
`else
assign long_ack_o = wb_ack_i;
`endif
 
//
// biu_err_o is one RISC clock cycle long long_err_o.
// long_err_o is one, two or four RISC clock cycles long because
// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.
//
assign biu_err_o = long_err_o
`ifdef OR1200_CLKDIV_4_SUPPORTED
                & (valid_div[1] | ~clmode[1])
`ifdef OR1200_CLKDIV_2_SUPPORTED
                & (valid_div[0] | ~clmode[0])
`endif
`endif
                ;
 
//
// Error termination
//
// long_err_o
//
`ifdef OR1200_REGISTERED_INPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                long_err_o <= #1 1'b0;
        else
                long_err_o <= #1 wb_err_i;
`else
assign long_err_o = wb_err_i;
`endif
 
//
// WB cyc_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_cyc_o <= #1 1'b0;
        else
`ifdef OR1200_NO_BURSTS
                wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i;
`else
                wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i | biu_cab_i;
`endif
`else
`ifdef OR1200_NO_BURSTS
assign wb_cyc_o = biu_cyc_i;
`else
assign wb_cyc_o = biu_cyc_i | biu_cab_i;
`endif
`endif
 
//
// WB stb_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_stb_o <= #1 1'b0;
        else
                wb_stb_o <= #1 (biu_cyc_i & biu_stb_i) & ~wb_ack_i;
`else
assign wb_stb_o = biu_cyc_i & biu_stb_i;
`endif
 
//
// WB we_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_we_o <= #1 1'b0;
        else
                wb_we_o <= #1 biu_cyc_i & biu_stb_i & biu_we_i;
`else
assign wb_we_o = biu_cyc_i & biu_stb_i & biu_we_i;
`endif
 
//
// WB sel_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_sel_o <= #1 4'b0000;
        else
                wb_sel_o <= #1 biu_sel_i;
`else
assign wb_sel_o = biu_sel_i;
`endif
 
//
// WB cab_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_cab_o <= #1 1'b0;
        else
                wb_cab_o <= #1 biu_cab_i;
`else
assign wb_cab_o = biu_cab_i;
`endif
 
endmodule

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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_wb_biu.v] - Blame information for rev 895

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's WISHBONE BIU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Implements WISHBONE interface ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - add support for wb_err_i ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	895	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
48			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
49			`//`
50	504	lampret	`// Revision 1.12 2001/11/22 13:42:51 lampret`
51			`// Added wb_cyc_o assignment after it was removed by accident.`
52			`//`
53			`// Revision 1.11 2001/11/20 21:28:10 lampret`
54			`// Added optional sampling of inputs.`
55			`//`
56			`// Revision 1.10 2001/11/18 11:32:00 lampret`
57			`// OR1200_REGISTERED_OUTPUTS can now be enabled.`
58			`//`
59			`// Revision 1.9 2001/10/21 17:57:16 lampret`
60			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
61			`//`
62			`// Revision 1.8 2001/10/14 13:12:10 lampret`
63			`// MP3 version.`
64			`//`
65			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
66			`// no message`
67			`//`
68			`// Revision 1.3 2001/08/09 13:39:33 lampret`
69			`// Major clean-up.`
70			`//`
71			`// Revision 1.2 2001/07/22 03:31:54 lampret`
72			`// Fixed RAM's oen bug. Cache bypass under development.`
73			`//`
74			`// Revision 1.1 2001/07/20 00:46:23 lampret`
75			`// Development version of RTL. Libraries are missing.`
76			`//`
77			`//`
78
79			`// synopsys translate_off`
80			`include "timescale.v"
81			`// synopsys translate_on`
82			`include "or1200_defines.v"
83
84			`module or1200_wb_biu(`
85			`// RISC clock, reset and clock control`
86			`clk, rst, clmode,`
87
88			`// WISHBONE interface`
89			`wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,`
90			`wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_cab_o, wb_dat_o,`
91
92			`// Internal RISC bus`
93			`biu_dat_i, biu_adr_i, biu_cyc_i, biu_stb_i, biu_we_i, biu_sel_i, biu_cab_i,`
94			`biu_dat_o, biu_ack_o, biu_err_o`
95			`);`
96
97			parameter dw = `OR1200_OPERAND_WIDTH;
98			parameter aw = `OR1200_OPERAND_WIDTH;
99
100			`//`
101			`// RISC clock, reset and clock control`
102			`//`
103			`input clk; // RISC clock`
104			`input rst; // RISC reset`
105			`input [1:0] clmode; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4`
106
107			`//`
108			`// WISHBONE interface`
109			`//`
110			`input wb_clk_i; // clock input`
111			`input wb_rst_i; // reset input`
112			`input wb_ack_i; // normal termination`
113			`input wb_err_i; // termination w/ error`
114			`input wb_rty_i; // termination w/ retry`
115			`input [dw-1:0] wb_dat_i; // input data bus`
116			`output wb_cyc_o; // cycle valid output`
117			`output [aw-1:0] wb_adr_o; // address bus outputs`
118			`output wb_stb_o; // strobe output`
119			`output wb_we_o; // indicates write transfer`
120			`output [3:0] wb_sel_o; // byte select outputs`
121			`output wb_cab_o; // consecutive address burst`
122			`output [dw-1:0] wb_dat_o; // output data bus`
123
124			`//`
125			`// Internal RISC interface`
126			`//`
127			`input [dw-1:0] biu_dat_i; // input data bus`
128			`input [aw-1:0] biu_adr_i; // address bus`
129			`input biu_cyc_i; // WB cycle`
130			`input biu_stb_i; // WB strobe`
131			`input biu_we_i; // WB write enable`
132			`input biu_cab_i; // CAB input`
133			`input [3:0] biu_sel_i; // byte selects`
134			`output [31:0] biu_dat_o; // output data bus`
135			`output biu_ack_o; // ack output`
136			`output biu_err_o; // err output`
137
138			`//`
139			`// Registers`
140			`//`
141			`reg [1:0] valid_div; // Used for synchronization`
142			`ifdef OR1200_REGISTERED_OUTPUTS
143			`reg [aw-1:0] wb_adr_o; // address bus outputs`
144			`reg wb_cyc_o; // cycle output`
145			`reg wb_stb_o; // strobe output`
146			`reg wb_we_o; // indicates write transfer`
147			`reg [3:0] wb_sel_o; // byte select outputs`
148			`reg wb_cab_o; // CAB output`
149			`reg [dw-1:0] wb_dat_o; // output data bus`
150			`endif
151			`ifdef OR1200_REGISTERED_INPUTS
152			`reg long_ack_o; // normal termination`
153			`reg long_err_o; // error termination`
154			`reg [dw-1:0] biu_dat_o; // output data bus`
155			`else
156			`wire long_ack_o; // normal termination`
157			`wire long_err_o; // error termination`
158			`endif
159
160			`//`
161			`// WISHBONE I/F <-> Internal RISC I/F conversion`
162			`//`
163
164			`//`
165			`// Address bus`
166			`//`
167			`ifdef OR1200_REGISTERED_OUTPUTS
168			`always @(posedge wb_clk_i or posedge wb_rst_i)`
169			`if (wb_rst_i)`
170			`wb_adr_o <= #1 {aw{1'b0}};`
171			`else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i)`
172			`wb_adr_o <= #1 biu_adr_i;`
173			`else
174			`assign wb_adr_o = biu_adr_i;`
175			`endif
176
177			`//`
178			`// Input data bus`
179			`//`
180			`ifdef OR1200_REGISTERED_INPUTS
181			`always @(posedge wb_clk_i or posedge wb_rst_i)`
182			`if (wb_rst_i)`
183			`biu_dat_o <= #1 32'h0000_0000;`
184			`else if (wb_ack_i)`
185			`biu_dat_o <= #1 wb_dat_i;`
186			`else
187			`assign biu_dat_o = wb_dat_i;`
188			`endif
189
190			`//`
191			`// Output data bus`
192			`//`
193			`ifdef OR1200_REGISTERED_OUTPUTS
194			`always @(posedge wb_clk_i or posedge wb_rst_i)`
195			`if (wb_rst_i)`
196			`wb_dat_o <= #1 {dw{1'b0}};`
197			`else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i)`
198			`wb_dat_o <= #1 biu_dat_i;`
199			`else
200			`assign wb_dat_o = biu_dat_i;`
201			`endif
202
203			`//`
204			`// Valid_div counts RISC clock cycles by modulo 4`
205			`// and is used to synchronize external WB i/f to`
206			`// RISC clock`
207			`//`
208			`always @(posedge clk or posedge rst)`
209			`if (rst)`
210			`valid_div <= #1 2'b0;`
211			`else`
212			`valid_div <= #1 valid_div + 'd1;`
213
214			`//`
215			`// biu_ack_o is one RISC clock cycle long long_ack_o.`
216			`// long_ack_o is one, two or four RISC clock cycles long because`
217			`// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.`
218			`//`
219			`assign biu_ack_o = long_ack_o`
220			`ifdef OR1200_CLKDIV_4_SUPPORTED
221			`& (valid_div[1] \| ~clmode[1])`
222			`ifdef OR1200_CLKDIV_2_SUPPORTED
223			`& (valid_div[0] \| ~clmode[0])`
224			`endif
225			`endif
226			`;`
227
228			`//`
229			`// Acknowledgment of the data to the RISC`
230			`//`
231			`// long_ack_o`
232			`//`
233			`ifdef OR1200_REGISTERED_INPUTS
234			`always @(posedge wb_clk_i or posedge wb_rst_i)`
235			`if (wb_rst_i)`
236			`long_ack_o <= #1 1'b0;`
237			`else`
238			`long_ack_o <= #1 wb_ack_i;`
239			`else
240			`assign long_ack_o = wb_ack_i;`
241			`endif
242
243			`//`
244			`// biu_err_o is one RISC clock cycle long long_err_o.`
245			`// long_err_o is one, two or four RISC clock cycles long because`
246			`// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.`
247			`//`
248			`assign biu_err_o = long_err_o`
249			`ifdef OR1200_CLKDIV_4_SUPPORTED
250			`& (valid_div[1] \| ~clmode[1])`
251			`ifdef OR1200_CLKDIV_2_SUPPORTED
252			`& (valid_div[0] \| ~clmode[0])`
253			`endif
254			`endif
255			`;`
256
257			`//`
258			`// Error termination`
259			`//`
260			`// long_err_o`
261			`//`
262			`ifdef OR1200_REGISTERED_INPUTS
263			`always @(posedge wb_clk_i or posedge wb_rst_i)`
264			`if (wb_rst_i)`
265			`long_err_o <= #1 1'b0;`
266			`else`
267			`long_err_o <= #1 wb_err_i;`
268			`else
269			`assign long_err_o = wb_err_i;`
270			`endif
271
272			`//`
273			`// WB cyc_o`
274			`//`
275			`ifdef OR1200_REGISTERED_OUTPUTS
276			`always @(posedge wb_clk_i or posedge wb_rst_i)`
277			`if (wb_rst_i)`
278			`wb_cyc_o <= #1 1'b0;`
279			`else`
280	895	lampret	`ifdef OR1200_NO_BURSTS
281			`wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i;`
282			`else
283	504	lampret	`wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i \| biu_cab_i;`
284	895	lampret	`endif
285	504	lampret	`else
286	895	lampret	`ifdef OR1200_NO_BURSTS
287			`assign wb_cyc_o = biu_cyc_i;`
288			`else
289	504	lampret	`assign wb_cyc_o = biu_cyc_i \| biu_cab_i;`
290			`endif
291	895	lampret	`endif
292	504	lampret
293			`//`
294			`// WB stb_o`
295			`//`
296			`ifdef OR1200_REGISTERED_OUTPUTS
297			`always @(posedge wb_clk_i or posedge wb_rst_i)`
298			`if (wb_rst_i)`
299			`wb_stb_o <= #1 1'b0;`
300			`else`
301			`wb_stb_o <= #1 (biu_cyc_i & biu_stb_i) & ~wb_ack_i;`
302			`else
303			`assign wb_stb_o = biu_cyc_i & biu_stb_i;`
304			`endif
305
306			`//`
307			`// WB we_o`
308			`//`
309			`ifdef OR1200_REGISTERED_OUTPUTS
310			`always @(posedge wb_clk_i or posedge wb_rst_i)`
311			`if (wb_rst_i)`
312			`wb_we_o <= #1 1'b0;`
313			`else`
314			`wb_we_o <= #1 biu_cyc_i & biu_stb_i & biu_we_i;`
315			`else
316			`assign wb_we_o = biu_cyc_i & biu_stb_i & biu_we_i;`
317			`endif
318
319			`//`
320			`// WB sel_o`
321			`//`
322			`ifdef OR1200_REGISTERED_OUTPUTS
323			`always @(posedge wb_clk_i or posedge wb_rst_i)`
324			`if (wb_rst_i)`
325			`wb_sel_o <= #1 4'b0000;`
326			`else`
327			`wb_sel_o <= #1 biu_sel_i;`
328			`else
329			`assign wb_sel_o = biu_sel_i;`
330			`endif
331
332			`//`
333			`// WB cab_o`
334			`//`
335			`ifdef OR1200_REGISTERED_OUTPUTS
336			`always @(posedge wb_clk_i or posedge wb_rst_i)`
337			`if (wb_rst_i)`
338			`wb_cab_o <= #1 1'b0;`
339			`else`
340			`wb_cab_o <= #1 biu_cab_i;`
341			`else
342			`assign wb_cab_o = biu_cab_i;`
343			`endif
344
345			`endmodule`