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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Double-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common double-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  double-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Double-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage 2-port Sync RAM                                    ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16_S16                               ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - fix Avant!                                               ////
////   - xilinx rams need external tri-state logic                ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.7.4.1  2003/07/08 15:36:37  lampret
// Added embedded memory QMEM.
//
// Revision 1.7  2003/04/07 01:19:07  lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.6  2002/03/28 19:25:42  lampret
// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.
//
// Revision 1.5  2002/02/01 19:56:54  lampret
// Fixed combinational loops.
//
// Revision 1.4  2002/01/23 07:52:36  lampret
// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
//
// Revision 1.3  2002/01/19 14:10:22  lampret
// Fixed OR1200_XILINX_RAM32X1D.
//
// Revision 1.2  2002/01/15 06:12:22  lampret
// Fixed module name when compiling with OR1200_XILINX_RAM32X1D
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/05 14:48:00  lampret
// Added missing endif
//
// Revision 1.9  2001/11/02 18:57:14  lampret
// Modified virtual silicon instantiations.
//
// Revision 1.8  2001/10/22 19:39:56  lampret
// Fixed parameters in generic sprams.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_dpram_32x32(
        // Generic synchronous double-port RAM interface
        clk_a, rst_a, ce_a, oe_a, addr_a, do_a,
        clk_b, rst_b, ce_b, we_b, addr_b, di_b
);
 
//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 32;
 
//
// Generic synchronous double-port RAM interface
//
input                   clk_a;  // Clock
input                   rst_a;  // Reset
input                   ce_a;   // Chip enable input
input                   oe_a;   // Output enable input
input   [aw-1:0] addr_a; // address bus inputs
output  [dw-1:0] do_a;   // output data bus
input                   clk_b;  // Clock
input                   rst_b;  // Reset
input                   ce_b;   // Chip enable input
input                   we_b;   // Write enable input
input   [aw-1:0] addr_b; // address bus inputs
input   [dw-1:0] di_b;   // input data bus
 
//
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SDP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Double-Port RAM (ra2sh)
//
`ifdef UNUSED
art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(
`else
art_hsdp_32x32 artisan_sdp(
`endif
        .qa(do_a),
        .clka(clk_a),
        .cena(~ce_a),
        .wena(1'b1),
        .aa(addr_a),
        .da(32'h00000000),
        .oena(~oe_a),
        .qb(),
        .clkb(clk_b),
        .cenb(~ce_b),
        .wenb(~we_b),
        .ab(addr_b),
        .db(di_b),
        .oenb(1'b1)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .doq(doq)
);
 
`else
 
`ifdef OR1200_VIRAGE_STP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 2-port R/W RAM
//
virage_stp virage_stp(
        .QA(do_a),
        .QB(),
 
        .ADRA(addr_a),
        .DA(32'h00000000),
        .WEA(1'b0),
        .OEA(oe_a),
        .MEA(ce_a),
        .CLKA(clk_a),
 
        .ADRB(addr_b),
        .DB(di_b),
        .WEB(we_b),
        .OEB(1'b1),
        .MEB(ce_b),
        .CLKB(clk_b)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_STP_T1
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Two-port R/W SRAM Type 1
//
`ifdef UNUSED
vs_hdtp_64x32 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
vs_hdtp_64x32 vs_ssp(
`endif
        .P1CK(clk_a),
        .P1CEN(~ce_a),
        .P1WEN(1'b1),
        .P1OEN(~oe_a),
        .P1ADR({1'b0, addr_a}),
        .P1DI(32'h0000_0000),
        .P1DOUT(do_a),
 
        .P2CK(clk_b),
        .P2CEN(~ce_b),
        .P2WEN(~ce_b),
        .P2OEN(1'b1),
        .P2ADR({1'b0, addr_b}),
        .P2DI(di_b),
        .P2DOUT()
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_STP_T2
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Two-port R/W SRAM Type 2
//
`ifdef UNUSED
vs_hdtp_32x32 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
vs_hdtp_32x32 vs_ssp(
`endif
        .RCK(clk_a),
        .REN(~ce_a),
        .OEN(~oe_a),
        .RADR(addr_a),
        .DOUT(do_a),
 
        .WCK(clk_b),
        .WEN(~ce_b),
        .WADR(addr_b),
        .DI(di_b)
);
 
`else
 
`ifdef OR1200_XILINX_RAM32X1D
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
reg     [4:0]    addr_a_r;
 
always @(posedge clk_a or posedge rst_a)
        if (rst_a)
                addr_a_r <= #1 5'b00000;
        else if (ce_a)
                addr_a_r <= #1 addr_a;
 
//
// Block 0
//
or1200_xcv_ram32x8d xcv_ram32x8d_0 (
        .DPO(do_a[7:0]),
        .SPO(),
        .A(addr_b),
        .D(di_b[7:0]),
        .DPRA(addr_a_r),
        .WCLK(clk_b),
        .WE(we_b)
);
 
//
// Block 1
//
or1200_xcv_ram32x8d xcv_ram32x8d_1 (
        .DPO(do_a[15:8]),
        .SPO(),
        .A(addr_b),
        .D(di_b[15:8]),
        .DPRA(addr_a_r),
        .WCLK(clk_b),
        .WE(we_b)
);
 
 
//
// Block 2
//
or1200_xcv_ram32x8d xcv_ram32x8d_2 (
        .DPO(do_a[23:16]),
        .SPO(),
        .A(addr_b),
        .D(di_b[23:16]),
        .DPRA(addr_a_r),
        .WCLK(clk_b),
        .WE(we_b)
);
 
//
// Block 3
//
or1200_xcv_ram32x8d xcv_ram32x8d_3 (
        .DPO(do_a[31:24]),
        .SPO(),
        .A(addr_b),
        .D(di_b[31:24]),
        .DPRA(addr_a_r),
        .WCLK(clk_b),
        .WE(we_b)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S16_S16 ramb4_s16_0(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA({3'b000, addr_a}),
        .DIA(16'h0000),
        .ENA(ce_a),
        .WEA(1'b0),
        .DOA(do_a[15:0]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB({3'b000, addr_b}),
        .DIB(di_b[15:0]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB()
);
 
//
// Block 1
//
RAMB4_S16_S16 ramb4_s16_1(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA({3'b000, addr_a}),
        .DIA(16'h0000),
        .ENA(ce_a),
        .WEA(1'b0),
        .DOA(do_a[31:16]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB({3'b000, addr_b}),
        .DIB(di_b[31:16]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB()
);
 
`else
 
`ifdef OR1200_ALTERA_LPM_XXX
 
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
altqpram altqpram_component (
        .wraddress_a (addr_a),
        .inclocken_a (ce_a),
        .wraddress_b (addr_b),
        .wren_a (we_a),
        .inclocken_b (ce_b),
        .wren_b (we_b),
        .inaclr_a (rst_a),
        .inaclr_b (rst_b),
        .inclock_a (clk_a),
        .inclock_b (clk_b),
        .data_a (di_a),
        .data_b (di_b),
        .q_a (do_a),
        .q_b (do_b)
);
 
defparam altqpram_component.operation_mode = "BIDIR_DUAL_PORT",
        altqpram_component.width_write_a = dw,
        altqpram_component.widthad_write_a = aw,
        altqpram_component.numwords_write_a = dw,
        altqpram_component.width_read_a = dw,
        altqpram_component.widthad_read_a = aw,
        altqpram_component.numwords_read_a = dw,
        altqpram_component.width_write_b = dw,
        altqpram_component.widthad_write_b = aw,
        altqpram_component.numwords_write_b = dw,
        altqpram_component.width_read_b = dw,
        altqpram_component.widthad_read_b = aw,
        altqpram_component.numwords_read_b = dw,
        altqpram_component.indata_reg_a = "INCLOCK_A",
        altqpram_component.wrcontrol_wraddress_reg_a = "INCLOCK_A",
        altqpram_component.outdata_reg_a = "INCLOCK_A",
        altqpram_component.indata_reg_b = "INCLOCK_B",
        altqpram_component.wrcontrol_wraddress_reg_b = "INCLOCK_B",
        altqpram_component.outdata_reg_b = "INCLOCK_B",
        altqpram_component.indata_aclr_a = "INACLR_A",
        altqpram_component.wraddress_aclr_a = "INACLR_A",
        altqpram_component.wrcontrol_aclr_a = "INACLR_A",
        altqpram_component.outdata_aclr_a = "INACLR_A",
        altqpram_component.indata_aclr_b = "NONE",
        altqpram_component.wraddress_aclr_b = "NONE",
        altqpram_component.wrcontrol_aclr_b = "NONE",
        altqpram_component.outdata_aclr_b = "INACLR_B",
        altqpram_component.lpm_hint = "USE_ESB=ON";
        //examplar attribute altqpram_component NOOPT TRUE
 
`else
 
//
// Generic double-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [aw-1:0] addr_a_reg;             // RAM address registered
 
//
// Data output drivers
//
assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};
 
//
// RAM read
//
always @(posedge clk_a or posedge rst_a)
        if (rst_a)
                addr_a_reg <= #1 {aw{1'b0}};
        else if (ce_a)
                addr_a_reg <= #1 addr_a;
 
//
// RAM write
//
always @(posedge clk_b)
        if (ce_b && we_b)
                mem[addr_b] <= #1 di_b;
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB4_S16_S16
`endif  // !OR1200_XILINX_RAM32X1D
`endif  // !OR1200_VIRTUALSILICON_SSP_T1
`endif  // !OR1200_VIRTUALSILICON_SSP_T2
`endif  // !OR1200_VIRAGE_STP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SDP
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Double-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common double-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// double-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Double-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage 2-port Sync RAM ////`
22			`//// ////`
23			`//// Supported FPGA RAMs are: ////`
24			`//// - Xilinx Virtex RAMB4_S16_S16 ////`
25	1129	lampret	`//// - Altera LPM ////`
26	504	lampret	`//// ////`
27			`//// To Do: ////`
28			`//// - fix Avant! ////`
29			`//// - xilinx rams need external tri-state logic ////`
30	1129	lampret	`//// - add additional RAMs ////`
31	504	lampret	`//// ////`
32			`//// Author(s): ////`
33			`//// - Damjan Lampret, lampret@opencores.org ////`
34			`//// ////`
35			`//////////////////////////////////////////////////////////////////////`
36			`//// ////`
37			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
38			`//// ////`
39			`//// This source file may be used and distributed without ////`
40			`//// restriction provided that this copyright statement is not ////`
41			`//// removed from the file and that any derivative work contains ////`
42			`//// the original copyright notice and the associated disclaimer. ////`
43			`//// ////`
44			`//// This source file is free software; you can redistribute it ////`
45			`//// and/or modify it under the terms of the GNU Lesser General ////`
46			`//// Public License as published by the Free Software Foundation; ////`
47			`//// either version 2.1 of the License, or (at your option) any ////`
48			`//// later version. ////`
49			`//// ////`
50			`//// This source is distributed in the hope that it will be ////`
51			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
52			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
53			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
54			`//// details. ////`
55			`//// ////`
56			`//// You should have received a copy of the GNU Lesser General ////`
57			`//// Public License along with this source; if not, download it ////`
58			`//// from http://www.opencores.org/lgpl.shtml ////`
59			`//// ////`
60			`//////////////////////////////////////////////////////////////////////`
61			`//`
62			`// CVS Revision History`
63			`//`
64			`// $Log: not supported by cvs2svn $`
65	1291	lampret	`// Revision 1.8 2004/04/05 08:29:57 lampret`
66			`// Merged branch_qmem into main tree.`
67			`//`
68	1267	lampret	`// Revision 1.7.4.1 2003/07/08 15:36:37 lampret`
69			`// Added embedded memory QMEM.`
70			`//`
71			`// Revision 1.7 2003/04/07 01:19:07 lampret`
72			`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`
73			`//`
74	1129	lampret	`// Revision 1.6 2002/03/28 19:25:42 lampret`
75			`// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.`
76			`//`
77	778	lampret	`// Revision 1.5 2002/02/01 19:56:54 lampret`
78			`// Fixed combinational loops.`
79			`//`
80	636	lampret	`// Revision 1.4 2002/01/23 07:52:36 lampret`
81			`// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.`
82			`//`
83	610	lampret	`// Revision 1.3 2002/01/19 14:10:22 lampret`
84			`// Fixed OR1200_XILINX_RAM32X1D.`
85			`//`
86	597	lampret	`// Revision 1.2 2002/01/15 06:12:22 lampret`
87			`// Fixed module name when compiling with OR1200_XILINX_RAM32X1D`
88			`//`
89	573	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
90			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
91			`//`
92	504	lampret	`// Revision 1.10 2001/11/05 14:48:00 lampret`
93			`// Added missing endif`
94			`//`
95			`// Revision 1.9 2001/11/02 18:57:14 lampret`
96			`// Modified virtual silicon instantiations.`
97			`//`
98			`// Revision 1.8 2001/10/22 19:39:56 lampret`
99			`// Fixed parameters in generic sprams.`
100			`//`
101			`// Revision 1.7 2001/10/21 17:57:16 lampret`
102			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
103			`//`
104			`// Revision 1.6 2001/10/14 13:12:09 lampret`
105			`// MP3 version.`
106			`//`
107			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
108			`// no message`
109			`//`
110			`// Revision 1.1 2001/08/09 13:39:33 lampret`
111			`// Major clean-up.`
112			`//`
113			`// Revision 1.2 2001/07/30 05:38:02 lampret`
114			`// Adding empty directories required by HDL coding guidelines`
115			`//`
116			`//`
117
118			`// synopsys translate_off`
119			`include "timescale.v"
120			`// synopsys translate_on`
121			`include "or1200_defines.v"
122
123			`module or1200_dpram_32x32(`
124			`// Generic synchronous double-port RAM interface`
125			`clk_a, rst_a, ce_a, oe_a, addr_a, do_a,`
126			`clk_b, rst_b, ce_b, we_b, addr_b, di_b`
127			`);`
128
129			`//`
130			`// Default address and data buses width`
131			`//`
132			`parameter aw = 5;`
133			`parameter dw = 32;`
134
135			`//`
136			`// Generic synchronous double-port RAM interface`
137			`//`
138			`input clk_a; // Clock`
139			`input rst_a; // Reset`
140			`input ce_a; // Chip enable input`
141			`input oe_a; // Output enable input`
142			`input [aw-1:0] addr_a; // address bus inputs`
143			`output [dw-1:0] do_a; // output data bus`
144			`input clk_b; // Clock`
145			`input rst_b; // Reset`
146			`input ce_b; // Chip enable input`
147			`input we_b; // Write enable input`
148			`input [aw-1:0] addr_b; // address bus inputs`
149			`input [dw-1:0] di_b; // input data bus`
150
151			`//`
152			`// Internal wires and registers`
153			`//`
154
155			`ifdef OR1200_ARTISAN_SDP
156
157			`//`
158			`// Instantiation of ASIC memory:`
159			`//`
160			`// Artisan Synchronous Double-Port RAM (ra2sh)`
161			`//`
162			`ifdef UNUSED
163			`art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(`
164			`else
165			`art_hsdp_32x32 artisan_sdp(`
166			`endif
167			`.qa(do_a),`
168			`.clka(clk_a),`
169			`.cena(~ce_a),`
170			`.wena(1'b1),`
171			`.aa(addr_a),`
172			`.da(32'h00000000),`
173			`.oena(~oe_a),`
174			`.qb(),`
175			`.clkb(clk_b),`
176			`.cenb(~ce_b),`
177			`.wenb(~we_b),`
178			`.ab(addr_b),`
179			`.db(di_b),`
180			`.oenb(1'b1)`
181			`);`
182
183			`else
184
185			`ifdef OR1200_AVANT_ATP
186
187			`//`
188			`// Instantiation of ASIC memory:`
189			`//`
190			`// Avant! Asynchronous Two-Port RAM`
191			`//`
192			`avant_atp avant_atp(`
193			`.web(~we),`
194			`.reb(),`
195			`.oeb(~oe),`
196			`.rcsb(),`
197			`.wcsb(),`
198			`.ra(addr),`
199			`.wa(addr),`
200			`.di(di),`
201	1291	lampret	`.doq(doq)`
202	504	lampret	`);`
203
204			`else
205
206			`ifdef OR1200_VIRAGE_STP
207
208			`//`
209			`// Instantiation of ASIC memory:`
210			`//`
211			`// Virage Synchronous 2-port R/W RAM`
212			`//`
213			`virage_stp virage_stp(`
214			`.QA(do_a),`
215			`.QB(),`
216
217			`.ADRA(addr_a),`
218			`.DA(32'h00000000),`
219			`.WEA(1'b0),`
220			`.OEA(oe_a),`
221			`.MEA(ce_a),`
222			`.CLKA(clk_a),`
223
224			`.ADRB(addr_b),`
225			`.DB(di_b),`
226			`.WEB(we_b),`
227			`.OEB(1'b1),`
228			`.MEB(ce_b),`
229			`.CLKB(clk_b)`
230			`);`
231
232			`else
233
234	778	lampret	`ifdef OR1200_VIRTUALSILICON_STP_T1
235	504	lampret
236			`//`
237			`// Instantiation of ASIC memory:`
238			`//`
239	778	lampret	`// Virtual Silicon Two-port R/W SRAM Type 1`
240	504	lampret	`//`
241			`ifdef UNUSED
242	636	lampret	`vs_hdtp_64x32 #(1<<aw, aw-1, dw-1) vs_ssp(`
243	504	lampret	`else
244	636	lampret	`vs_hdtp_64x32 vs_ssp(`
245	504	lampret	`endif
246	636	lampret	`.P1CK(clk_a),`
247			`.P1CEN(~ce_a),`
248			`.P1WEN(1'b1),`
249			`.P1OEN(~oe_a),`
250			`.P1ADR({1'b0, addr_a}),`
251			`.P1DI(32'h0000_0000),`
252			`.P1DOUT(do_a),`
253
254			`.P2CK(clk_b),`
255			`.P2CEN(~ce_b),`
256			`.P2WEN(~ce_b),`
257			`.P2OEN(1'b1),`
258			`.P2ADR({1'b0, addr_b}),`
259			`.P2DI(di_b),`
260			`.P2DOUT()`
261	504	lampret	`);`
262
263			`else
264
265	778	lampret	`ifdef OR1200_VIRTUALSILICON_STP_T2
266
267			`//`
268			`// Instantiation of ASIC memory:`
269			`//`
270			`// Virtual Silicon Two-port R/W SRAM Type 2`
271			`//`
272			`ifdef UNUSED
273			`vs_hdtp_32x32 #(1<<aw, aw-1, dw-1) vs_ssp(`
274			`else
275			`vs_hdtp_32x32 vs_ssp(`
276			`endif
277			`.RCK(clk_a),`
278			`.REN(~ce_a),`
279			`.OEN(~oe_a),`
280			`.RADR(addr_a),`
281			`.DOUT(do_a),`
282
283			`.WCK(clk_b),`
284			`.WEN(~ce_b),`
285			`.WADR(addr_b),`
286			`.DI(di_b)`
287			`);`
288
289			`else
290
291	504	lampret	`ifdef OR1200_XILINX_RAM32X1D
292
293			`//`
294			`// Instantiation of FPGA memory:`
295			`//`
296			`// Virtex/Spartan2`
297			`//`
298
299	597	lampret	`reg [4:0] addr_a_r;`
300
301			`always @(posedge clk_a or posedge rst_a)`
302	610	lampret	`if (rst_a)`
303			`addr_a_r <= #1 5'b00000;`
304			`else if (ce_a)`
305	597	lampret	`addr_a_r <= #1 addr_a;`
306
307	504	lampret	`//`
308			`// Block 0`
309			`//`
310	573	lampret	`or1200_xcv_ram32x8d xcv_ram32x8d_0 (`
311	504	lampret	`.DPO(do_a[7:0]),`
312			`.SPO(),`
313			`.A(addr_b),`
314			`.D(di_b[7:0]),`
315	597	lampret	`.DPRA(addr_a_r),`
316	504	lampret	`.WCLK(clk_b),`
317			`.WE(we_b)`
318			`);`
319
320			`//`
321			`// Block 1`
322			`//`
323	573	lampret	`or1200_xcv_ram32x8d xcv_ram32x8d_1 (`
324	504	lampret	`.DPO(do_a[15:8]),`
325			`.SPO(),`
326			`.A(addr_b),`
327			`.D(di_b[15:8]),`
328	597	lampret	`.DPRA(addr_a_r),`
329	504	lampret	`.WCLK(clk_b),`
330			`.WE(we_b)`
331			`);`
332
333
334			`//`
335			`// Block 2`
336			`//`
337	573	lampret	`or1200_xcv_ram32x8d xcv_ram32x8d_2 (`
338	504	lampret	`.DPO(do_a[23:16]),`
339			`.SPO(),`
340			`.A(addr_b),`
341			`.D(di_b[23:16]),`
342	597	lampret	`.DPRA(addr_a_r),`
343	504	lampret	`.WCLK(clk_b),`
344			`.WE(we_b)`
345			`);`
346
347			`//`
348			`// Block 3`
349			`//`
350	573	lampret	`or1200_xcv_ram32x8d xcv_ram32x8d_3 (`
351	504	lampret	`.DPO(do_a[31:24]),`
352			`.SPO(),`
353			`.A(addr_b),`
354			`.D(di_b[31:24]),`
355	597	lampret	`.DPRA(addr_a_r),`
356	504	lampret	`.WCLK(clk_b),`
357			`.WE(we_b)`
358			`);`
359
360			`else
361
362			`ifdef OR1200_XILINX_RAMB4
363
364			`//`
365			`// Instantiation of FPGA memory:`
366			`//`
367			`// Virtex/Spartan2`
368			`//`
369
370			`//`
371			`// Block 0`
372			`//`
373			`RAMB4_S16_S16 ramb4_s16_0(`
374			`.CLKA(clk_a),`
375			`.RSTA(rst_a),`
376			`.ADDRA({3'b000, addr_a}),`
377			`.DIA(16'h0000),`
378			`.ENA(ce_a),`
379			`.WEA(1'b0),`
380			`.DOA(do_a[15:0]),`
381
382			`.CLKB(clk_b),`
383			`.RSTB(rst_b),`
384			`.ADDRB({3'b000, addr_b}),`
385			`.DIB(di_b[15:0]),`
386			`.ENB(ce_b),`
387			`.WEB(we_b),`
388			`.DOB()`
389			`);`
390
391			`//`
392			`// Block 1`
393			`//`
394			`RAMB4_S16_S16 ramb4_s16_1(`
395			`.CLKA(clk_a),`
396			`.RSTA(rst_a),`
397			`.ADDRA({3'b000, addr_a}),`
398			`.DIA(16'h0000),`
399			`.ENA(ce_a),`
400			`.WEA(1'b0),`
401			`.DOA(do_a[31:16]),`
402
403			`.CLKB(clk_b),`
404			`.RSTB(rst_b),`
405			`.ADDRB({3'b000, addr_b}),`
406			`.DIB(di_b[31:16]),`
407			`.ENB(ce_b),`
408			`.WEB(we_b),`
409			`.DOB()`
410			`);`
411
412			`else
413
414	1267	lampret	`ifdef OR1200_ALTERA_LPM_XXX
415	1129	lampret
416	504	lampret	`//`
417	1129	lampret	`// Instantiation of FPGA memory:`
418			`//`
419			`// Altera LPM`
420			`//`
421			`// Added By Jamil Khatib`
422			`//`
423			`altqpram altqpram_component (`
424			`.wraddress_a (addr_a),`
425			`.inclocken_a (ce_a),`
426			`.wraddress_b (addr_b),`
427			`.wren_a (we_a),`
428			`.inclocken_b (ce_b),`
429			`.wren_b (we_b),`
430			`.inaclr_a (rst_a),`
431			`.inaclr_b (rst_b),`
432			`.inclock_a (clk_a),`
433			`.inclock_b (clk_b),`
434			`.data_a (di_a),`
435			`.data_b (di_b),`
436			`.q_a (do_a),`
437			`.q_b (do_b)`
438			`);`
439
440			`defparam altqpram_component.operation_mode = "BIDIR_DUAL_PORT",`
441			`altqpram_component.width_write_a = dw,`
442			`altqpram_component.widthad_write_a = aw,`
443			`altqpram_component.numwords_write_a = dw,`
444			`altqpram_component.width_read_a = dw,`
445			`altqpram_component.widthad_read_a = aw,`
446			`altqpram_component.numwords_read_a = dw,`
447			`altqpram_component.width_write_b = dw,`
448			`altqpram_component.widthad_write_b = aw,`
449			`altqpram_component.numwords_write_b = dw,`
450			`altqpram_component.width_read_b = dw,`
451			`altqpram_component.widthad_read_b = aw,`
452			`altqpram_component.numwords_read_b = dw,`
453			`altqpram_component.indata_reg_a = "INCLOCK_A",`
454			`altqpram_component.wrcontrol_wraddress_reg_a = "INCLOCK_A",`
455			`altqpram_component.outdata_reg_a = "INCLOCK_A",`
456			`altqpram_component.indata_reg_b = "INCLOCK_B",`
457			`altqpram_component.wrcontrol_wraddress_reg_b = "INCLOCK_B",`
458			`altqpram_component.outdata_reg_b = "INCLOCK_B",`
459			`altqpram_component.indata_aclr_a = "INACLR_A",`
460			`altqpram_component.wraddress_aclr_a = "INACLR_A",`
461			`altqpram_component.wrcontrol_aclr_a = "INACLR_A",`
462			`altqpram_component.outdata_aclr_a = "INACLR_A",`
463			`altqpram_component.indata_aclr_b = "NONE",`
464			`altqpram_component.wraddress_aclr_b = "NONE",`
465			`altqpram_component.wrcontrol_aclr_b = "NONE",`
466			`altqpram_component.outdata_aclr_b = "INACLR_B",`
467			`altqpram_component.lpm_hint = "USE_ESB=ON";`
468			`//examplar attribute altqpram_component NOOPT TRUE`
469
470			`else
471
472			`//`
473	504	lampret	`// Generic double-port synchronous RAM model`
474			`//`
475
476			`//`
477			`// Generic RAM's registers and wires`
478			`//`
479			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
480	1291	lampret	`reg [aw-1:0] addr_a_reg; // RAM address registered`
481	504	lampret
482			`//`
483			`// Data output drivers`
484			`//`
485	1291	lampret	`assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};`
486	504	lampret
487			`//`
488			`// RAM read`
489			`//`
490	1291	lampret	`always @(posedge clk_a or posedge rst_a)`
491			`if (rst_a)`
492			`addr_a_reg <= #1 {aw{1'b0}};`
493			`else if (ce_a)`
494			`addr_a_reg <= #1 addr_a;`
495	504	lampret
496			`//`
497			`// RAM write`
498			`//`
499			`always @(posedge clk_b)`
500			`if (ce_b && we_b)`

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