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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16                                   ////
////                                                              ////
////  To Do:                                                      ////
////   - add support for other RAM's                              ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2004/04/08 11:00:46  simont
// Add support for 512B instruction cache.
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_128x32(
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, doq
);
 
//
// Default address and data buses width
//
parameter aw = 7;
parameter dw = 32;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] doq;    // output data bus
 
//
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
`endif
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
`endif
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
        .CLK(clk),
        .RST(rst),
        .ADDR({1'b0, addr}),
        .DI(di[15:0]),
        .EN(ce),
        .WE(we),
        .DO(doq[15:0])
);
 
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
        .CLK(clk),
        .RST(rst),
        .ADDR({1'b0, addr}),
        .DI(di[31:16]),
        .EN(ce),
        .WE(we),
        .DO(doq[31:16])
);
 
`else
 
`ifdef OR1200_ALTERA_LPM
 
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
 
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [aw-1:0] addr_reg;               // RAM address register
 
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
 
//
// RAM address register
//
always @(posedge clk or posedge rst)
        if (rst)
                addr_reg <= #1 {aw{1'b0}};
        else if (ce)
                addr_reg <= #1 addr;
 
//
// RAM write
//
always @(posedge clk)
        if (ce && we)
                mem[addr] <= #1 di;
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB4_S16
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

Line No.	Rev	Author	Line
1	1273	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// ////`
20			`//// Supported FPGA RAMs are: ////`
21			`//// - Xilinx Virtex RAMB4_S16 ////`
22			`//// ////`
23			`//// To Do: ////`
24			`//// - add support for other RAM's ////`
25			`//// - xilinx rams need external tri-state logic ////`
26			`//// - fix avant! two-port ram ////`
27			`//// - add additional RAMs ////`
28			`//// ////`
29			`//// Author(s): ////`
30			`//// - Damjan Lampret, lampret@opencores.org ////`
31			`//// ////`
32			`//////////////////////////////////////////////////////////////////////`
33			`//// ////`
34			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
35			`//// ////`
36			`//// This source file may be used and distributed without ////`
37			`//// restriction provided that this copyright statement is not ////`
38			`//// removed from the file and that any derivative work contains ////`
39			`//// the original copyright notice and the associated disclaimer. ////`
40			`//// ////`
41			`//// This source file is free software; you can redistribute it ////`
42			`//// and/or modify it under the terms of the GNU Lesser General ////`
43			`//// Public License as published by the Free Software Foundation; ////`
44			`//// either version 2.1 of the License, or (at your option) any ////`
45			`//// later version. ////`
46			`//// ////`
47			`//// This source is distributed in the hope that it will be ////`
48			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
49			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
50			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
51			`//// details. ////`
52			`//// ////`
53			`//// You should have received a copy of the GNU Lesser General ////`
54			`//// Public License along with this source; if not, download it ////`
55			`//// from http://www.opencores.org/lgpl.shtml ////`
56			`//// ////`
57			`//////////////////////////////////////////////////////////////////////`
58			`//`
59			`// CVS Revision History`
60			`//`
61			`// $Log: not supported by cvs2svn $`
62	1291	lampret	`// Revision 1.1 2004/04/08 11:00:46 simont`
63			`// Add support for 512B instruction cache.`
64	1273	simont	`//`
65			`//`
66	1291	lampret	`//`
67	1273	simont
68			`// synopsys translate_off`
69			`include "timescale.v"
70			`// synopsys translate_on`
71			`include "or1200_defines.v"
72
73			`module or1200_spram_128x32(`
74			`ifdef OR1200_BIST
75			`// RAM BIST`
76			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
77			`endif
78			`// Generic synchronous single-port RAM interface`
79	1291	lampret	`clk, rst, ce, we, oe, addr, di, doq`
80	1273	simont	`);`
81
82			`//`
83			`// Default address and data buses width`
84			`//`
85			`parameter aw = 7;`
86			`parameter dw = 32;`
87
88			`ifdef OR1200_BIST
89			`//`
90			`// RAM BIST`
91			`//`
92			`input mbist_si_i;`
93			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
94			`output mbist_so_o;`
95			`endif
96
97			`//`
98			`// Generic synchronous single-port RAM interface`
99			`//`
100			`input clk; // Clock`
101			`input rst; // Reset`
102			`input ce; // Chip enable input`
103			`input we; // Write enable input`
104			`input oe; // Output enable input`
105			`input [aw-1:0] addr; // address bus inputs`
106			`input [dw-1:0] di; // input data bus`
107	1291	lampret	`output [dw-1:0] doq; // output data bus`
108	1273	simont
109			`//`
110			`// Internal wires and registers`
111			`//`
112
113			`ifdef OR1200_ARTISAN_SSP
114			`else
115			`ifdef OR1200_VIRTUALSILICON_SSP
116			`else
117			`ifdef OR1200_BIST
118			`endif
119			`endif
120			`endif
121
122			`ifdef OR1200_ARTISAN_SSP
123
124			`//`
125			`// Instantiation of ASIC memory:`
126			`//`
127			`// Artisan Synchronous Single-Port RAM (ra1sh)`
128			`//`
129			`ifdef UNUSED
130			`else
131			`ifdef OR1200_BIST
132			`else
133			`endif
134			`endif
135			`ifdef OR1200_BIST
136			`endif
137			`else
138
139			`ifdef OR1200_AVANT_ATP
140
141			`//`
142			`// Instantiation of ASIC memory:`
143			`//`
144			`// Avant! Asynchronous Two-Port RAM`
145			`//`
146
147			`else
148
149			`ifdef OR1200_VIRAGE_SSP
150
151			`//`
152			`// Instantiation of ASIC memory:`
153			`//`
154			`// Virage Synchronous 1-port R/W RAM`
155			`//`
156
157			`else
158
159			`ifdef OR1200_VIRTUALSILICON_SSP
160
161			`//`
162			`// Instantiation of ASIC memory:`
163			`//`
164			`// Virtual Silicon Single-Port Synchronous SRAM`
165			`//`
166			`ifdef UNUSED
167			`else
168			`ifdef OR1200_BIST
169			`else
170			`endif
171			`endif
172			`ifdef OR1200_BIST
173			`// RAM BIST`
174			`endif
175
176			`else
177
178			`ifdef OR1200_XILINX_RAMB4
179
180			`//`
181			`// Instantiation of FPGA memory:`
182			`//`
183			`// Virtex/Spartan2`
184			`//`
185
186			`//`
187			`// Block 0`
188			`//`
189			`RAMB4_S16 ramb4_s16_0(`
190			`.CLK(clk),`
191			`.RST(rst),`
192			`.ADDR({1'b0, addr}),`
193			`.DI(di[15:0]),`
194			`.EN(ce),`
195			`.WE(we),`
196	1291	lampret	`.DO(doq[15:0])`
197	1273	simont	`);`
198
199			`//`
200			`// Block 1`
201			`//`
202			`RAMB4_S16 ramb4_s16_1(`
203			`.CLK(clk),`
204			`.RST(rst),`
205			`.ADDR({1'b0, addr}),`
206			`.DI(di[31:16]),`
207			`.EN(ce),`
208			`.WE(we),`
209	1291	lampret	`.DO(doq[31:16])`
210	1273	simont	`);`
211
212			`else
213
214			`ifdef OR1200_ALTERA_LPM
215
216			`//`
217			`// Instantiation of FPGA memory:`
218			`//`
219			`// Altera LPM`
220			`//`
221			`// Added By Jamil Khatib`
222			`//`
223
224
225			`else
226
227			`//`
228			`// Generic single-port synchronous RAM model`
229			`//`
230
231			`//`
232			`// Generic RAM's registers and wires`
233			`//`
234			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
235	1291	lampret	`reg [aw-1:0] addr_reg; // RAM address register`
236	1273	simont
237			`//`
238			`// Data output drivers`
239			`//`
240	1291	lampret	`assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};`
241	1273	simont
242			`//`
243	1291	lampret	`// RAM address register`
244	1273	simont	`//`
245	1291	lampret	`always @(posedge clk or posedge rst)`
246			`if (rst)`
247			`addr_reg <= #1 {aw{1'b0}};`
248			`else if (ce)`
249			`addr_reg <= #1 addr;`
250
251			`//`
252			`// RAM write`
253			`//`
254	1273	simont	`always @(posedge clk)`
255	1291	lampret	`if (ce && we)`
256	1273	simont	`mem[addr] <= #1 di;`
257
258			`endif // !OR1200_ALTERA_LPM
259			`endif // !OR1200_XILINX_RAMB4_S16
260			`endif // !OR1200_VIRTUALSILICON_SSP
261			`endif // !OR1200_VIRAGE_SSP
262			`endif // !OR1200_AVANT_ATP
263			`endif // !OR1200_ARTISAN_SSP
264
265			`endmodule`

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[/] [or1k/] [tags/] [rel_29/] [or1200/] [rtl/] [verilog/] [or1200_spram_128x32.v] - Blame information for rev 1765