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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16                                   ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1  2003/12/09 11:46:48  simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3  2003/04/07 01:19:07  lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2  2002/10/17 20:04:40  lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/27 21:24:04  lampret
// Changed instantiation name of VS RAMs.
//
// Revision 1.9  2001/11/27 19:45:04  lampret
// Fixed VS RAM instantiation - again.
//
// Revision 1.8  2001/11/23 21:42:31  simons
// Program counter divided to PPC and NPC.
//
// Revision 1.6  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_512x20(
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, doq
);
 
//
// Default address and data buses width
//
parameter aw = 9;
parameter dw = 20;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] doq;    // output data bus
 
//
// Internal wires and registers
//
wire    [3:0]            unconnected;
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_512x20 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_512x20_bist artisan_ssp(
`else
art_hssp_512x20 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CLK(clk),
        .CEN(~ce),
        .WEN(~we),
        .A(addr),
        .D(di),
        .OEN(~oe),
        .Q(doq)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .doq(doq)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(doq)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_512x20 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_512x20_bist vs_ssp(
`else
vs_hdsp_512x20 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di),
        .WEN(~we),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(doq)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S8 ramb4_s8_0(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[7:0]),
        .EN(ce),
        .WE(we),
        .DO(doq[7:0])
);
 
//
// Block 1
//
RAMB4_S8 ramb4_s8_1(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[15:8]),
        .EN(ce),
        .WE(we),
        .DO(doq[15:8])
);
 
//
// Block 2
//
RAMB4_S8 ramb4_s8_2(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI({4'b0000, di[19:16]}),
        .EN(ce),
        .WE(we),
        .DO({unconnected, doq[19:16]})
);
 
`else
 
`ifdef OR1200_ALTERA_LPM
 
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
 
wire    wr;
 
assign  wr = ce & we;
 
initial $display("Using Altera LPM.");
 
lpm_ram_dq lpm_ram_dq_component (
        .address(addr),
        .inclock(clk),
        .outclock(clk),
        .data(di),
        .we(wr),
        .q(doq)
);
 
defparam lpm_ram_dq_component.lpm_width = dw,
        lpm_ram_dq_component.lpm_widthad = aw,
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
        // examplar attribute lpm_ram_dq_component NOOPT TRUE
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [aw-1:0] addr_reg;               // RAM address register
 
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
 
//
// RAM address register
//
always @(posedge clk or posedge rst)
        if (rst)
                addr_reg <= #1 {aw{1'b0}};
        else if (ce)
                addr_reg <= #1 addr;
 
//
// RAM write
//
always @(posedge clk)
        if (ce && we)
                mem[addr] <= #1 di;
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB4_S16
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB4_S16 ////`
26	1129	lampret	`//// - Altera LPM ////`
27	504	lampret	`//// ////`
28			`//// To Do: ////`
29			`//// - xilinx rams need external tri-state logic ////`
30			`//// - fix avant! two-port ram ////`
31	1129	lampret	`//// - add additional RAMs ////`
32	504	lampret	`//// ////`
33			`//// Author(s): ////`
34			`//// - Damjan Lampret, lampret@opencores.org ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//// ////`
38			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
39			`//// ////`
40			`//// This source file may be used and distributed without ////`
41			`//// restriction provided that this copyright statement is not ////`
42			`//// removed from the file and that any derivative work contains ////`
43			`//// the original copyright notice and the associated disclaimer. ////`
44			`//// ////`
45			`//// This source file is free software; you can redistribute it ////`
46			`//// and/or modify it under the terms of the GNU Lesser General ////`
47			`//// Public License as published by the Free Software Foundation; ////`
48			`//// either version 2.1 of the License, or (at your option) any ////`
49			`//// later version. ////`
50			`//// ////`
51			`//// This source is distributed in the hope that it will be ////`
52			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
53			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
54			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
55			`//// details. ////`
56			`//// ////`
57			`//// You should have received a copy of the GNU Lesser General ////`
58			`//// Public License along with this source; if not, download it ////`
59			`//// from http://www.opencores.org/lgpl.shtml ////`
60			`//// ////`
61			`//////////////////////////////////////////////////////////////////////`
62			`//`
63			`// CVS Revision History`
64			`//`
65			`// $Log: not supported by cvs2svn $`
66	1291	lampret	`// Revision 1.7 2004/04/05 08:29:57 lampret`
67			`// Merged branch_qmem into main tree.`
68			`//`
69	1267	lampret	`// Revision 1.3.4.1 2003/12/09 11:46:48 simons`
70			`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`
71	1200	markom	`//`
72	1179	simons	`// Revision 1.3 2003/04/07 01:19:07 lampret`
73			`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`
74			`//`
75	1129	lampret	`// Revision 1.2 2002/10/17 20:04:40 lampret`
76			`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
77			`//`
78	1063	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
79			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
80			`//`
81	504	lampret	`// Revision 1.10 2001/11/27 21:24:04 lampret`
82			`// Changed instantiation name of VS RAMs.`
83			`//`
84			`// Revision 1.9 2001/11/27 19:45:04 lampret`
85			`// Fixed VS RAM instantiation - again.`
86			`//`
87			`// Revision 1.8 2001/11/23 21:42:31 simons`
88			`// Program counter divided to PPC and NPC.`
89			`//`
90			`// Revision 1.6 2001/10/21 17:57:16 lampret`
91			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
92			`//`
93			`// Revision 1.5 2001/10/14 13:12:09 lampret`
94			`// MP3 version.`
95			`//`
96			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
97			`// no message`
98			`//`
99			`// Revision 1.1 2001/08/09 13:39:33 lampret`
100			`// Major clean-up.`
101			`//`
102			`// Revision 1.2 2001/07/30 05:38:02 lampret`
103			`// Adding empty directories required by HDL coding guidelines`
104			`//`
105			`//`
106
107			`// synopsys translate_off`
108			`include "timescale.v"
109			`// synopsys translate_on`
110			`include "or1200_defines.v"
111
112			`module or1200_spram_512x20(`
113	1063	lampret	`ifdef OR1200_BIST
114			`// RAM BIST`
115	1200	markom	`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
116	1063	lampret	`endif
117	504	lampret	`// Generic synchronous single-port RAM interface`
118	1291	lampret	`clk, rst, ce, we, oe, addr, di, doq`
119	504	lampret	`);`
120
121			`//`
122			`// Default address and data buses width`
123			`//`
124			`parameter aw = 9;`
125			`parameter dw = 20;`
126
127	1063	lampret	`ifdef OR1200_BIST
128	504	lampret	`//`
129	1063	lampret	`// RAM BIST`
130			`//`
131	1267	lampret	`input mbist_si_i;`
132			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
133			`output mbist_so_o;`
134	1063	lampret	`endif
135
136			`//`
137	504	lampret	`// Generic synchronous single-port RAM interface`
138			`//`
139			`input clk; // Clock`
140			`input rst; // Reset`
141			`input ce; // Chip enable input`
142			`input we; // Write enable input`
143			`input oe; // Output enable input`
144			`input [aw-1:0] addr; // address bus inputs`
145			`input [dw-1:0] di; // input data bus`
146	1291	lampret	`output [dw-1:0] doq; // output data bus`
147	504	lampret
148			`//`
149			`// Internal wires and registers`
150			`//`
151			`wire [3:0] unconnected;`
152
153	1184	simons	`ifdef OR1200_ARTISAN_SSP
154			`else
155			`ifdef OR1200_VIRTUALSILICON_SSP
156			`else
157	1063	lampret	`ifdef OR1200_BIST
158	1200	markom	`assign mbist_so_o = mbist_si_i;`
159	1063	lampret	`endif
160	1184	simons	`endif
161			`endif
162	1063	lampret
163	504	lampret	`ifdef OR1200_ARTISAN_SSP
164
165			`//`
166			`// Instantiation of ASIC memory:`
167			`//`
168			`// Artisan Synchronous Single-Port RAM (ra1sh)`
169			`//`
170			`ifdef UNUSED
171			`art_hssp_512x20 #(dw, 1<<aw, aw) artisan_ssp(`
172			`else
173	1179	simons	`ifdef OR1200_BIST
174			`art_hssp_512x20_bist artisan_ssp(`
175			`else
176	504	lampret	`art_hssp_512x20 artisan_ssp(`
177			`endif
178	1179	simons	`endif
179			`ifdef OR1200_BIST
180			`// RAM BIST`
181	1200	markom	`.mbist_si_i(mbist_si_i),`
182			`.mbist_so_o(mbist_so_o),`
183			`.mbist_ctrl_i(mbist_ctrl_i),`
184	1179	simons	`endif
185			`.CLK(clk),`
186			`.CEN(~ce),`
187			`.WEN(~we),`
188			`.A(addr),`
189			`.D(di),`
190			`.OEN(~oe),`
191	1291	lampret	`.Q(doq)`
192	504	lampret	`);`
193
194			`else
195
196			`ifdef OR1200_AVANT_ATP
197
198			`//`
199			`// Instantiation of ASIC memory:`
200			`//`
201			`// Avant! Asynchronous Two-Port RAM`
202			`//`
203			`avant_atp avant_atp(`
204			`.web(~we),`
205			`.reb(),`
206			`.oeb(~oe),`
207			`.rcsb(),`
208			`.wcsb(),`
209			`.ra(addr),`
210			`.wa(addr),`
211			`.di(di),`
212	1291	lampret	`.doq(doq)`
213	504	lampret	`);`
214
215			`else
216
217			`ifdef OR1200_VIRAGE_SSP
218
219			`//`
220			`// Instantiation of ASIC memory:`
221			`//`
222			`// Virage Synchronous 1-port R/W RAM`
223			`//`
224			`virage_ssp virage_ssp(`
225			`.clk(clk),`
226			`.adr(addr),`
227			`.d(di),`
228			`.we(we),`
229			`.oe(oe),`
230			`.me(ce),`
231	1291	lampret	`.q(doq)`
232	504	lampret	`);`
233
234			`else
235
236			`ifdef OR1200_VIRTUALSILICON_SSP
237
238			`//`
239			`// Instantiation of ASIC memory:`
240			`//`
241			`// Virtual Silicon Single-Port Synchronous SRAM`
242			`//`
243			`ifdef UNUSED
244			`vs_hdsp_512x20 #(1<<aw, aw-1, dw-1) vs_ssp(`
245			`else
246	1063	lampret	`ifdef OR1200_BIST
247			`vs_hdsp_512x20_bist vs_ssp(`
248			`else
249	504	lampret	`vs_hdsp_512x20 vs_ssp(`
250			`endif
251	1063	lampret	`endif
252			`ifdef OR1200_BIST
253			`// RAM BIST`
254	1200	markom	`.mbist_si_i(mbist_si_i),`
255			`.mbist_so_o(mbist_so_o),`
256			`.mbist_ctrl_i(mbist_ctrl_i),`
257	1063	lampret	`endif
258	504	lampret	`.CK(clk),`
259			`.ADR(addr),`
260			`.DI(di),`
261			`.WEN(~we),`
262			`.CEN(~ce),`
263			`.OEN(~oe),`
264	1291	lampret	`.DOUT(doq)`
265	504	lampret	`);`
266
267			`else
268
269			`ifdef OR1200_XILINX_RAMB4
270
271			`//`
272			`// Instantiation of FPGA memory:`
273			`//`
274			`// Virtex/Spartan2`
275			`//`
276
277			`//`
278			`// Block 0`
279			`//`
280			`RAMB4_S8 ramb4_s8_0(`
281			`.CLK(clk),`
282			`.RST(rst),`
283			`.ADDR(addr),`
284			`.DI(di[7:0]),`
285			`.EN(ce),`
286			`.WE(we),`
287	1291	lampret	`.DO(doq[7:0])`
288	504	lampret	`);`
289
290			`//`
291			`// Block 1`
292			`//`
293			`RAMB4_S8 ramb4_s8_1(`
294			`.CLK(clk),`
295			`.RST(rst),`
296			`.ADDR(addr),`
297			`.DI(di[15:8]),`
298			`.EN(ce),`
299			`.WE(we),`
300	1291	lampret	`.DO(doq[15:8])`
301	504	lampret	`);`
302
303			`//`
304			`// Block 2`
305			`//`
306			`RAMB4_S8 ramb4_s8_2(`
307			`.CLK(clk),`
308			`.RST(rst),`
309			`.ADDR(addr),`
310			`.DI({4'b0000, di[19:16]}),`
311			`.EN(ce),`
312			`.WE(we),`
313	1291	lampret	`.DO({unconnected, doq[19:16]})`
314	504	lampret	`);`
315
316			`else
317
318	1129	lampret	`ifdef OR1200_ALTERA_LPM
319
320	504	lampret	`//`
321	1129	lampret	`// Instantiation of FPGA memory:`
322			`//`
323			`// Altera LPM`
324			`//`
325			`// Added By Jamil Khatib`
326			`//`
327
328			`wire wr;`
329
330			`assign wr = ce & we;`
331
332			`initial $display("Using Altera LPM.");`
333
334			`lpm_ram_dq lpm_ram_dq_component (`
335			`.address(addr),`
336			`.inclock(clk),`
337			`.outclock(clk),`
338			`.data(di),`
339			`.we(wr),`
340	1291	lampret	`.q(doq)`
341	1129	lampret	`);`
342
343			`defparam lpm_ram_dq_component.lpm_width = dw,`
344			`lpm_ram_dq_component.lpm_widthad = aw,`
345			`lpm_ram_dq_component.lpm_indata = "REGISTERED",`
346			`lpm_ram_dq_component.lpm_address_control = "REGISTERED",`
347			`lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",`
348			`lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";`
349			`// examplar attribute lpm_ram_dq_component NOOPT TRUE`
350
351			`else
352
353			`//`
354	504	lampret	`// Generic single-port synchronous RAM model`
355			`//`
356
357			`//`
358			`// Generic RAM's registers and wires`
359			`//`
360			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
361	1291	lampret	`reg [aw-1:0] addr_reg; // RAM address register`
362	504	lampret
363			`//`
364			`// Data output drivers`
365			`//`
366	1291	lampret	`assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};`
367	504	lampret
368			`//`
369	1291	lampret	`// RAM address register`
370	504	lampret	`//`
371	1291	lampret	`always @(posedge clk or posedge rst)`
372			`if (rst)`
373			`addr_reg <= #1 {aw{1'b0}};`
374			`else if (ce)`
375			`addr_reg <= #1 addr;`
376
377			`//`
378			`// RAM write`
379			`//`
380	504	lampret	`always @(posedge clk)`
381	1291	lampret	`if (ce && we)`
382	504	lampret	`mem[addr] <= #1 di;`
383
384	1129	lampret	`endif // !OR1200_ALTERA_LPM
385	504	lampret	`endif // !OR1200_XILINX_RAMB4_S16
386			`endif // !OR1200_VIRTUALSILICON_SSP
387			`endif // !OR1200_VIRAGE_SSP
388			`endif // !OR1200_AVANT_ATP
389			`endif // !OR1200_ARTISAN_SSP
390
391			`endmodule`

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