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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Exception logic                                    ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Handles all OR1K exceptions inside CPU block.               ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2002/01/14 19:09:57  lampret
// Fixed order of syscall and range exceptions.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.15  2001/11/27 23:13:11  lampret
// Fixed except_stop width and fixed EX PC for 1400444f no-ops.
//
// Revision 1.14  2001/11/23 08:38:51  lampret
// Changed DSR/DRR behavior and exception detection.
//
// Revision 1.13  2001/11/20 18:46:15  simons
// Break point bug fixed
//
// Revision 1.12  2001/11/18 09:58:28  lampret
// Fixed some l.trap typos.
//
// Revision 1.11  2001/11/18 08:36:28  lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.10  2001/11/13 10:02:21  lampret
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
//
// Revision 1.9  2001/11/10 03:43:57  lampret
// Fixed exceptions.
//
// Revision 1.8  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
`define OR1200_EXCEPTFSM_WIDTH 3
`define OR1200_EXCEPTFSM_IDLE   `OR1200_EXCEPTFSM_WIDTH'd0
`define OR1200_EXCEPTFSM_FLU1   `OR1200_EXCEPTFSM_WIDTH'd1
`define OR1200_EXCEPTFSM_FLU2   `OR1200_EXCEPTFSM_WIDTH'd2
`define OR1200_EXCEPTFSM_FLU3   `OR1200_EXCEPTFSM_WIDTH'd3
`define OR1200_EXCEPTFSM_FLU4   `OR1200_EXCEPTFSM_WIDTH'd4
`define OR1200_EXCEPTFSM_FLU5   `OR1200_EXCEPTFSM_WIDTH'd5
 
//
// Exception recognition and sequencing
//
 
module or1200_except(
        // Clock and reset
        clk, rst,
 
        // Internal i/f
        sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,
        sig_inthigh, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_intlow,
        branch_taken, id_freeze, ex_freeze, wb_freeze, if_stall,
        if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
        except_started, except_stop,
        wb_pc, ex_pc, id_pc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
        esr, sr, lsu_addr
);
 
//
// I/O
//
input                           clk;
input                           rst;
input                           sig_ibuserr;
input                           sig_dbuserr;
input                           sig_illegal;
input                           sig_align;
input                           sig_range;
input                           sig_dtlbmiss;
input                           sig_dmmufault;
input                           sig_inthigh;
input                           sig_syscall;
input                           sig_trap;
input                           sig_itlbmiss;
input                           sig_immufault;
input                           sig_intlow;
input                           branch_taken;
input                           id_freeze;
input                           ex_freeze;
input                           wb_freeze;
input                           if_stall;
input   [31:0]                   if_pc;
output  [31:2]                  lr_sav;
input   [31:0]                   datain;
input   [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;
input                           epcr_we;
input                           eear_we;
input                           esr_we;
input                           pc_we;
output  [31:0]                   epcr;
output  [31:0]                   eear;
output  [`OR1200_SR_WIDTH-1:0]           esr;
input   [`OR1200_SR_WIDTH-1:0]           sr;
input   [31:0]                   lsu_addr;
output                          flushpipe;
output                          extend_flush;
output  [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
output                          except_start;
output                          except_started;
output  [12:0]                   except_stop;
output  [31:0]                   wb_pc;
output  [31:0]                   ex_pc;
output  [31:0]                   id_pc;
 
//
// Internal regs and wires
//
reg     [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
reg     [31:0]                   id_pc;
reg     [31:0]                   ex_pc;
reg     [31:0]                   wb_pc;
reg     [31:0]                   epcr;
reg     [31:0]                   eear;
reg     [`OR1200_SR_WIDTH-1:0]           esr;
reg     [3:0]                    id_exceptflags;
reg     [3:0]                    ex_exceptflags;
reg     [`OR1200_EXCEPTFSM_WIDTH-1:0]    state;
reg                             extend_flush;
reg                             extend_flush_last;
reg                             ex_dslot;
reg                             delayed1_ex_dslot;
reg                             delayed2_ex_dslot;
wire                            except_started;
wire    [12:0]                   except_trig;
wire                            except_flushpipe;
reg     [2:0]                    delayed_eir;
wire                            inthigh_pending;
wire                            intlow_pending;
 
//
// Simple combinatorial logic
//
assign except_started = extend_flush & except_start;
assign lr_sav = ex_pc[31:2];
//assign except_start = (except_type != `OR1200_EXCEPT_NONE);  // damjan
assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
assign inthigh_pending = sig_inthigh & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
assign intlow_pending = sig_intlow & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~delayed1_ex_dslot & ~delayed2_ex_dslot;
 
//
// Order defines exception detection priority
//
assign except_trig = {
                        inthigh_pending         & ~du_dsr[`OR1200_DU_DSR_HPINTE],
                        ex_exceptflags[2]       & ~du_dsr[`OR1200_DU_DSR_IME],
                        ex_exceptflags[1]       & ~du_dsr[`OR1200_DU_DSR_IPFE],
                        ex_exceptflags[3]       & ~du_dsr[`OR1200_DU_DSR_BUSEE],
                        sig_illegal             & ~du_dsr[`OR1200_DU_DSR_IIE],
                        sig_align               & ~du_dsr[`OR1200_DU_DSR_AE],
                        sig_dtlbmiss            & ~du_dsr[`OR1200_DU_DSR_DME],
                        sig_dmmufault           & ~du_dsr[`OR1200_DU_DSR_DPFE],
                        sig_dbuserr             & ~du_dsr[`OR1200_DU_DSR_BUSEE],
                        ex_exceptflags[0]        & ~du_dsr[`OR1200_DU_DSR_LPINTE],
                        sig_range               & ~du_dsr[`OR1200_DU_DSR_RE],
                        sig_trap                & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
                        sig_syscall             & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
                };
assign except_stop = {
                        inthigh_pending         & du_dsr[`OR1200_DU_DSR_HPINTE],
                        ex_exceptflags[2]       & du_dsr[`OR1200_DU_DSR_IME],
                        ex_exceptflags[1]       & du_dsr[`OR1200_DU_DSR_IPFE],
                        ex_exceptflags[3]       & du_dsr[`OR1200_DU_DSR_BUSEE],
                        sig_illegal             & du_dsr[`OR1200_DU_DSR_IIE],
                        sig_align               & du_dsr[`OR1200_DU_DSR_AE],
                        sig_dtlbmiss            & du_dsr[`OR1200_DU_DSR_DME],
                        sig_dmmufault           & du_dsr[`OR1200_DU_DSR_DPFE],
                        sig_dbuserr             & du_dsr[`OR1200_DU_DSR_BUSEE],
                        ex_exceptflags[0]        & du_dsr[`OR1200_DU_DSR_LPINTE],
                        sig_range               & du_dsr[`OR1200_DU_DSR_RE],
                        sig_trap                & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
                        sig_syscall             & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
                };
 
//
// PC and Exception flags pipelines
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                id_pc <= #1 32'd0;
                id_exceptflags <= #1 4'b0000;
        end
        else if (flushpipe) begin
                id_pc <= #1 32'h0000_0000;
                id_exceptflags <= #1 4'b0000;
        end
        else if (!id_freeze) begin
                id_pc <= #1 if_pc;
                id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault, intlow_pending };
        end
end
 
//
// delayed_eir
//
// SR[EIR] should not enable interrupts right away
// when it is restored with l.rfe. Instead delayed_eir
// together with SR[EIR] enables interrupts once
// pipeline is again ready.
//
always @(posedge rst or posedge clk)
        if (rst)
                delayed_eir <= #1 3'b000;
        else if (!sr[`OR1200_SR_EIR])
                delayed_eir <= #1 3'b000;
        else
                delayed_eir <= #1 {delayed_eir[1:0], 1'b1};
 
//
// PC and Exception flags pipelines
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                ex_dslot <= #1 1'b0;
                ex_pc <= #1 32'd0;
                ex_exceptflags <= #1 4'b0000;
                delayed1_ex_dslot <= #1 1'b0;
                delayed2_ex_dslot <= #1 1'b0;
        end
        else if (flushpipe) begin
                ex_dslot <= #1 1'b0;
                ex_pc <= #1 32'h0000_0000;
                ex_exceptflags <= #1 4'b0000;
                delayed1_ex_dslot <= #1 1'b0;
                delayed2_ex_dslot <= #1 1'b0;
        end
        else if (!ex_freeze & id_freeze) begin
                ex_dslot <= #1 1'b0;
                ex_pc <= #1 id_pc;
                ex_exceptflags <= #1 4'b0000;
                delayed1_ex_dslot <= #1 ex_dslot;
                delayed2_ex_dslot <= #1 delayed1_ex_dslot;
        end
        else if (!ex_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                $display("%t: ex_pc <= %h", $time, id_pc);
// synopsys translate_on
`endif
                ex_dslot <= #1 branch_taken;
                ex_pc <= #1 id_pc;
                ex_exceptflags <= #1 id_exceptflags;
                delayed1_ex_dslot <= #1 ex_dslot;
                delayed2_ex_dslot <= #1 delayed1_ex_dslot;
        end
end
 
//
// PC and Exception flags pipelines
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                wb_pc <= #1 32'd0;
        end
        else if (!wb_freeze) begin
                wb_pc <= #1 ex_pc;
        end
end
 
//
// Flush pipeline
//
assign flushpipe = except_flushpipe | pc_we | extend_flush;
 
//
// We have started execution of exception handler:
//  1. Asserted for 3 clock cycles
//  2. Don't execute any instruction that is still in pipeline and is not part of exception handler
//
assign except_flushpipe = |except_trig & !state;
 
//
// Exception FSM that sequences execution of exception handler
//
// except_type signals which exception handler we start fetching in:
//  1. Asserted in next clock cycle after exception is recognized
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                state <= #1 `OR1200_EXCEPTFSM_IDLE;
                except_type <= #1 `OR1200_EXCEPT_NONE;
                extend_flush <= #1 1'b0;
                epcr <= #1 32'b0;
                eear <= #1 32'b0;
                esr <= #1 `OR1200_SR_WIDTH'b010;
                extend_flush_last <= #1 1'b0;
        end
        else begin
                case (state)    // synopsys full_case parallel_case
                        `OR1200_EXCEPTFSM_IDLE:
                                if (except_flushpipe) begin
                                        state <= #1 `OR1200_EXCEPTFSM_FLU1;
                                        extend_flush <= #1 1'b1;
                                        if (ex_dslot) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                                $display(" INFO: Exception during first delay slot instruction.");
// synopsys translate_on
`endif
                                        end
                                        else if (delayed1_ex_dslot) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                                $display(" INFO: Exception during second (NOP) delay slot instruction.");
// synopsys translate_on
`endif
                                        end
                                        else if (delayed2_ex_dslot) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                                $display(" INFO: Exception during third delay slot (SHOULD NOT HAPPEN).");
// synopsys translate_on
`endif
                                        end
                                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                                $display(" INFO: Exception during normal (no delay slot) instruction.");
// synopsys translate_on
`endif
                                        end
 
                                        esr <= #1 sr;
                                        casex (except_trig)
                                                13'b1_xxxx_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_HPINT;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_1xxx_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
                                                        eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_01xx_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_IPF;
                                                        eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_001x_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_BUSERR;
                                                        eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_0001_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_0000_1xxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_ALIGN;
                                                        eear <= #1 lsu_addr;
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
                                                end
                                                13'b0_0000_01xx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
                                                        eear <= #1 lsu_addr;
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
                                                end
                                                13'b0_0000_001x_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_DPF;
                                                        eear <= #1 lsu_addr;
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
                                                end
                                                13'b0_0000_0001_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_BUSERR;
                                                        eear <= #1 lsu_addr;
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
                                                end
                                                13'b0_0000_0000_1xxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_LPINT;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_0000_0000_01xx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_RANGE;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_0000_0000_001x: begin
                                                        except_type <= #1 `OR1200_EXCEPT_TRAP;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_0000_0000_0001: begin
                                                        except_type <= #1 `OR1200_EXCEPT_SYSCALL;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                default:
                                                        except_type <= #1 `OR1200_EXCEPT_NONE;
                                        endcase
                                end
                                else if (pc_we) begin
                                        state <= #1 `OR1200_EXCEPTFSM_FLU1;
                                        extend_flush <= #1 1'b1;
                                end
                                else begin
                                        if (epcr_we)
                                                epcr <= #1 datain;
                                        if (eear_we)
                                                eear <= #1 datain;
                                        if (esr_we)
                                                esr <= #1 {datain[`OR1200_SR_WIDTH-1:2], 1'b1, datain[0]};
                                end
                        `OR1200_EXCEPTFSM_FLU1:
//                              if (!if_stall & !id_freeze)
                                        state <= #1 `OR1200_EXCEPTFSM_FLU2;
                        `OR1200_EXCEPTFSM_FLU2:
                                if (except_type == `OR1200_EXCEPT_TRAP) begin
                                        state <= #1 `OR1200_EXCEPTFSM_IDLE;
                                        extend_flush <= #1 1'b0;
                                        extend_flush_last <= #1 1'b0;
                                        except_type <= #1 `OR1200_EXCEPT_NONE;
                                end
                                else
//                              if (!if_stall & !id_freeze)
                                        state <= #1 `OR1200_EXCEPTFSM_FLU3;
                        `OR1200_EXCEPTFSM_FLU3:
//                              if (!if_stall && !id_freeze)
                                        begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                                if (except_flushpipe)
                                                        $display(" INFO: EPCR0 %h  EEAR %h  ESR %h", epcr, eear, esr);
// synopsys translate_on
`endif
                                                state <= #1 `OR1200_EXCEPTFSM_FLU4;
                                        end
                        `OR1200_EXCEPTFSM_FLU4: begin
                                        state <= #1 `OR1200_EXCEPTFSM_FLU5;
                                        extend_flush <= #1 1'b0;
                                        extend_flush_last <= #1 1'b0; // damjan
                                end
                        `OR1200_EXCEPTFSM_FLU5: begin
                                if (!if_stall && !id_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display(" INFO: Just finished flushing pipeline.");
// synopsys translate_on
`endif
                                state <= #1 `OR1200_EXCEPTFSM_IDLE;
                                except_type <= #1 `OR1200_EXCEPT_NONE;
                                extend_flush_last <= #1 1'b0;
                        end
                        end
                endcase
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Exception logic ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Handles all OR1K exceptions inside CPU block. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	571	lampret	`// Revision 1.3 2002/01/14 19:09:57 lampret`
48			`// Fixed order of syscall and range exceptions.`
49			`//`
50	570	lampret	`// Revision 1.2 2002/01/14 06:18:22 lampret`
51			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
52			`//`
53	562	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
54			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
55			`//`
56	504	lampret	`// Revision 1.15 2001/11/27 23:13:11 lampret`
57			`// Fixed except_stop width and fixed EX PC for 1400444f no-ops.`
58			`//`
59			`// Revision 1.14 2001/11/23 08:38:51 lampret`
60			`// Changed DSR/DRR behavior and exception detection.`
61			`//`
62			`// Revision 1.13 2001/11/20 18:46:15 simons`
63			`// Break point bug fixed`
64			`//`
65			`// Revision 1.12 2001/11/18 09:58:28 lampret`
66			`// Fixed some l.trap typos.`
67			`//`
68			`// Revision 1.11 2001/11/18 08:36:28 lampret`
69			`// For GDB changed single stepping and disabled trap exception.`
70			`//`
71			`// Revision 1.10 2001/11/13 10:02:21 lampret`
72			`// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)`
73			`//`
74			`// Revision 1.9 2001/11/10 03:43:57 lampret`
75			`// Fixed exceptions.`
76			`//`
77			`// Revision 1.8 2001/10/21 17:57:16 lampret`
78			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
79			`//`
80			`// Revision 1.7 2001/10/14 13:12:09 lampret`
81			`// MP3 version.`
82			`//`
83			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
84			`// no message`
85			`//`
86			`// Revision 1.2 2001/08/09 13:39:33 lampret`
87			`// Major clean-up.`
88			`//`
89			`// Revision 1.1 2001/07/20 00:46:03 lampret`
90			`// Development version of RTL. Libraries are missing.`
91			`//`
92			`//`
93
94			`// synopsys translate_off`
95			`include "timescale.v"
96			`// synopsys translate_on`
97			`include "or1200_defines.v"
98
99			`define OR1200_EXCEPTFSM_WIDTH 3
100			`define OR1200_EXCEPTFSM_IDLE `OR1200_EXCEPTFSM_WIDTH'd0
101			`define OR1200_EXCEPTFSM_FLU1 `OR1200_EXCEPTFSM_WIDTH'd1
102			`define OR1200_EXCEPTFSM_FLU2 `OR1200_EXCEPTFSM_WIDTH'd2
103			`define OR1200_EXCEPTFSM_FLU3 `OR1200_EXCEPTFSM_WIDTH'd3
104			`define OR1200_EXCEPTFSM_FLU4 `OR1200_EXCEPTFSM_WIDTH'd4
105			`define OR1200_EXCEPTFSM_FLU5 `OR1200_EXCEPTFSM_WIDTH'd5
106
107			`//`
108			`// Exception recognition and sequencing`
109			`//`
110
111			`module or1200_except(`
112			`// Clock and reset`
113			`clk, rst,`
114
115			`// Internal i/f`
116			`sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,`
117			`sig_inthigh, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_intlow,`
118			`branch_taken, id_freeze, ex_freeze, wb_freeze, if_stall,`
119			`if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,`
120			`except_started, except_stop,`
121	562	lampret	`wb_pc, ex_pc, id_pc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,`
122	504	lampret	`esr, sr, lsu_addr`
123			`);`
124
125			`//`
126			`// I/O`
127			`//`
128			`input clk;`
129			`input rst;`
130			`input sig_ibuserr;`
131			`input sig_dbuserr;`
132			`input sig_illegal;`
133			`input sig_align;`
134			`input sig_range;`
135			`input sig_dtlbmiss;`
136			`input sig_dmmufault;`
137			`input sig_inthigh;`
138			`input sig_syscall;`
139			`input sig_trap;`
140			`input sig_itlbmiss;`
141			`input sig_immufault;`
142			`input sig_intlow;`
143			`input branch_taken;`
144			`input id_freeze;`
145			`input ex_freeze;`
146			`input wb_freeze;`
147			`input if_stall;`
148			`input [31:0] if_pc;`
149			`output [31:2] lr_sav;`
150			`input [31:0] datain;`
151			input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
152			`input epcr_we;`
153			`input eear_we;`
154			`input esr_we;`
155			`input pc_we;`
156			`output [31:0] epcr;`
157			`output [31:0] eear;`
158			output [`OR1200_SR_WIDTH-1:0] esr;
159			input [`OR1200_SR_WIDTH-1:0] sr;
160			`input [31:0] lsu_addr;`
161			`output flushpipe;`
162			`output extend_flush;`
163			output [`OR1200_EXCEPT_WIDTH-1:0] except_type;
164			`output except_start;`
165			`output except_started;`
166			`output [12:0] except_stop;`
167			`output [31:0] wb_pc;`
168			`output [31:0] ex_pc;`
169	562	lampret	`output [31:0] id_pc;`
170	504	lampret
171			`//`
172			`// Internal regs and wires`
173			`//`
174			reg [`OR1200_EXCEPT_WIDTH-1:0] except_type;
175			`reg [31:0] id_pc;`
176			`reg [31:0] ex_pc;`
177			`reg [31:0] wb_pc;`
178			`reg [31:0] epcr;`
179			`reg [31:0] eear;`
180			reg [`OR1200_SR_WIDTH-1:0] esr;
181			`reg [3:0] id_exceptflags;`
182			`reg [3:0] ex_exceptflags;`
183			reg [`OR1200_EXCEPTFSM_WIDTH-1:0] state;
184			`reg extend_flush;`
185			`reg extend_flush_last;`
186			`reg ex_dslot;`
187			`reg delayed1_ex_dslot;`
188			`reg delayed2_ex_dslot;`
189			`wire except_started;`
190			`wire [12:0] except_trig;`
191			`wire except_flushpipe;`
192			`reg [2:0] delayed_eir;`
193			`wire inthigh_pending;`
194			`wire intlow_pending;`
195
196			`//`
197			`// Simple combinatorial logic`
198			`//`
199			`assign except_started = extend_flush & except_start;`
200			`assign lr_sav = ex_pc[31:2];`
201	562	lampret	//assign except_start = (except_type != `OR1200_EXCEPT_NONE); // damjan
202			assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
203			assign inthigh_pending = sig_inthigh & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
204	504	lampret	assign intlow_pending = sig_intlow & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~delayed1_ex_dslot & ~delayed2_ex_dslot;
205
206			`//`
207			`// Order defines exception detection priority`
208			`//`
209			`assign except_trig = {`
210			inthigh_pending & ~du_dsr[`OR1200_DU_DSR_HPINTE],
211			ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_IME],
212			ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IPFE],
213			ex_exceptflags[3] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
214			sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE],
215			sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
216			sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
217			sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
218			sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
219			ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_LPINTE],
220	570	lampret	sig_range & ~du_dsr[`OR1200_DU_DSR_RE],
221	562	lampret	sig_trap & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
222	570	lampret	sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
223	504	lampret	`};`
224			`assign except_stop = {`
225			inthigh_pending & du_dsr[`OR1200_DU_DSR_HPINTE],
226			ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_IME],
227			ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IPFE],
228			ex_exceptflags[3] & du_dsr[`OR1200_DU_DSR_BUSEE],
229			sig_illegal & du_dsr[`OR1200_DU_DSR_IIE],
230			sig_align & du_dsr[`OR1200_DU_DSR_AE],
231			sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
232			sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
233			sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
234			ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_LPINTE],
235	570	lampret	sig_range & du_dsr[`OR1200_DU_DSR_RE],
236	562	lampret	sig_trap & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
237	570	lampret	sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
238	504	lampret	`};`
239
240			`//`
241			`// PC and Exception flags pipelines`
242			`//`
243			`always @(posedge clk or posedge rst) begin`
244			`if (rst) begin`
245			`id_pc <= #1 32'd0;`
246			`id_exceptflags <= #1 4'b0000;`
247			`end`
248	562	lampret	`else if (flushpipe) begin`
249			`id_pc <= #1 32'h0000_0000;`
250			`id_exceptflags <= #1 4'b0000;`
251			`end`
252	504	lampret	`else if (!id_freeze) begin`
253			`id_pc <= #1 if_pc;`
254			`id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault, intlow_pending };`
255			`end`
256			`end`
257
258			`//`
259			`// delayed_eir`
260			`//`
261			`// SR[EIR] should not enable interrupts right away`
262			`// when it is restored with l.rfe. Instead delayed_eir`
263			`// together with SR[EIR] enables interrupts once`
264			`// pipeline is again ready.`
265			`//`
266			`always @(posedge rst or posedge clk)`
267			`if (rst)`
268			`delayed_eir <= #1 3'b000;`
269			else if (!sr[`OR1200_SR_EIR])
270			`delayed_eir <= #1 3'b000;`
271			`else`
272			`delayed_eir <= #1 {delayed_eir[1:0], 1'b1};`
273
274			`//`
275			`// PC and Exception flags pipelines`
276			`//`
277			`always @(posedge clk or posedge rst) begin`
278			`if (rst) begin`
279			`ex_dslot <= #1 1'b0;`
280			`ex_pc <= #1 32'd0;`
281			`ex_exceptflags <= #1 4'b0000;`
282			`delayed1_ex_dslot <= #1 1'b0;`
283			`delayed2_ex_dslot <= #1 1'b0;`
284			`end`
285	562	lampret	`else if (flushpipe) begin`
286			`ex_dslot <= #1 1'b0;`
287			`ex_pc <= #1 32'h0000_0000;`
288			`ex_exceptflags <= #1 4'b0000;`
289			`delayed1_ex_dslot <= #1 1'b0;`
290			`delayed2_ex_dslot <= #1 1'b0;`
291			`end`
292	504	lampret	`else if (!ex_freeze & id_freeze) begin`
293			`ex_dslot <= #1 1'b0;`
294			`ex_pc <= #1 id_pc;`
295			`ex_exceptflags <= #1 4'b0000;`
296			`delayed1_ex_dslot <= #1 ex_dslot;`
297			`delayed2_ex_dslot <= #1 delayed1_ex_dslot;`
298			`end`
299			`else if (!ex_freeze) begin`
300			`ifdef OR1200_VERBOSE
301			`// synopsys translate_off`
302			`$display("%t: ex_pc <= %h", $time, id_pc);`
303			`// synopsys translate_on`
304			`endif
305			`ex_dslot <= #1 branch_taken;`
306			`ex_pc <= #1 id_pc;`
307			`ex_exceptflags <= #1 id_exceptflags;`
308			`delayed1_ex_dslot <= #1 ex_dslot;`
309			`delayed2_ex_dslot <= #1 delayed1_ex_dslot;`
310			`end`
311			`end`
312
313			`//`
314			`// PC and Exception flags pipelines`
315			`//`
316			`always @(posedge clk or posedge rst) begin`
317			`if (rst) begin`
318			`wb_pc <= #1 32'd0;`
319			`end`
320			`else if (!wb_freeze) begin`
321			`wb_pc <= #1 ex_pc;`
322			`end`
323			`end`
324
325			`//`
326			`// Flush pipeline`
327			`//`
328	562	lampret	`assign flushpipe = except_flushpipe \| pc_we \| extend_flush;`
329	504	lampret
330			`//`
331			`// We have started execution of exception handler:`
332			`// 1. Asserted for 3 clock cycles`
333			`// 2. Don't execute any instruction that is still in pipeline and is not part of exception handler`
334			`//`
335	562	lampret	`assign except_flushpipe = \|except_trig & !state;`
336	504	lampret
337			`//`
338			`// Exception FSM that sequences execution of exception handler`
339			`//`
340			`// except_type signals which exception handler we start fetching in:`
341			`// 1. Asserted in next clock cycle after exception is recognized`
342			`//`
343			`always @(posedge clk or posedge rst) begin`
344			`if (rst) begin`
345			state <= #1 `OR1200_EXCEPTFSM_IDLE;
346			except_type <= #1 `OR1200_EXCEPT_NONE;
347			`extend_flush <= #1 1'b0;`
348			`epcr <= #1 32'b0;`
349			`eear <= #1 32'b0;`
350			esr <= #1 `OR1200_SR_WIDTH'b010;
351			`extend_flush_last <= #1 1'b0;`
352			`end`
353			`else begin`
354			`case (state) // synopsys full_case parallel_case`
355			`OR1200_EXCEPTFSM_IDLE:
356			`if (except_flushpipe) begin`
357			state <= #1 `OR1200_EXCEPTFSM_FLU1;
358			`extend_flush <= #1 1'b1;`
359			`if (ex_dslot) begin`
360			`ifdef OR1200_VERBOSE
361			`// synopsys translate_off`
362			`$display(" INFO: Exception during first delay slot instruction.");`
363			`// synopsys translate_on`
364			`endif
365			`end`
366			`else if (delayed1_ex_dslot) begin`
367			`ifdef OR1200_VERBOSE
368			`// synopsys translate_off`
369			`$display(" INFO: Exception during second (NOP) delay slot instruction.");`
370			`// synopsys translate_on`
371			`endif
372			`end`
373			`else if (delayed2_ex_dslot) begin`
374			`ifdef OR1200_VERBOSE
375			`// synopsys translate_off`
376			`$display(" INFO: Exception during third delay slot (SHOULD NOT HAPPEN).");`
377			`// synopsys translate_on`
378			`endif
379			`end`
380			`else begin`
381			`ifdef OR1200_VERBOSE
382			`// synopsys translate_off`
383			`$display(" INFO: Exception during normal (no delay slot) instruction.");`
384			`// synopsys translate_on`
385			`endif
386			`end`
387
388			`esr <= #1 sr;`
389			`casex (except_trig)`
390			`13'b1_xxxx_xxxx_xxxx: begin`
391			except_type <= #1 `OR1200_EXCEPT_HPINT;
392			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
393			`end`
394			`13'b0_1xxx_xxxx_xxxx: begin`
395			except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
396			`eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
397			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
398			`end`
399			`13'b0_01xx_xxxx_xxxx: begin`
400			except_type <= #1 `OR1200_EXCEPT_IPF;
401			`eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
402			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
403			`end`
404			`13'b0_001x_xxxx_xxxx: begin`
405			except_type <= #1 `OR1200_EXCEPT_BUSERR;
406			`eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
407			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
408			`end`
409			`13'b0_0001_xxxx_xxxx: begin`
410			except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
411			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
412			`end`
413			`13'b0_0000_1xxx_xxxx: begin`
414			except_type <= #1 `OR1200_EXCEPT_ALIGN;
415			`eear <= #1 lsu_addr;`
416	571	lampret	`epcr <= #1 ex_dslot ? wb_pc : ex_pc;`
417	504	lampret	`end`
418			`13'b0_0000_01xx_xxxx: begin`
419			except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
420			`eear <= #1 lsu_addr;`
421			`epcr <= #1 ex_dslot ? wb_pc : ex_pc;`
422			`end`
423			`13'b0_0000_001x_xxxx: begin`
424			except_type <= #1 `OR1200_EXCEPT_DPF;
425			`eear <= #1 lsu_addr;`
426			`epcr <= #1 ex_dslot ? wb_pc : ex_pc;`
427			`end`
428			`13'b0_0000_0001_xxxx: begin`
429			except_type <= #1 `OR1200_EXCEPT_BUSERR;
430			`eear <= #1 lsu_addr;`
431	562	lampret	`epcr <= #1 ex_dslot ? wb_pc : ex_pc;`
432	504	lampret	`end`
433			`13'b0_0000_0000_1xxx: begin`
434			except_type <= #1 `OR1200_EXCEPT_LPINT;
435			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
436			`end`
437			`13'b0_0000_0000_01xx: begin`
438			except_type <= #1 `OR1200_EXCEPT_RANGE;
439			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
440			`end`
441			`13'b0_0000_0000_001x: begin`
442			except_type <= #1 `OR1200_EXCEPT_TRAP;
443			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
444			`end`
445			`13'b0_0000_0000_0001: begin`
446			except_type <= #1 `OR1200_EXCEPT_SYSCALL;
447			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
448			`end`
449			`default:`
450			except_type <= #1 `OR1200_EXCEPT_NONE;
451			`endcase`
452			`end`
453			`else if (pc_we) begin`
454			state <= #1 `OR1200_EXCEPTFSM_FLU1;
455			`extend_flush <= #1 1'b1;`
456			`end`
457			`else begin`
458			`if (epcr_we)`
459			`epcr <= #1 datain;`
460			`if (eear_we)`
461			`eear <= #1 datain;`
462			`if (esr_we)`
463			esr <= #1 {datain[`OR1200_SR_WIDTH-1:2], 1'b1, datain[0]};
464			`end`
465			`OR1200_EXCEPTFSM_FLU1:
466	562	lampret	`// if (!if_stall & !id_freeze)`
467	504	lampret	state <= #1 `OR1200_EXCEPTFSM_FLU2;
468			`OR1200_EXCEPTFSM_FLU2:
469			if (except_type == `OR1200_EXCEPT_TRAP) begin
470			state <= #1 `OR1200_EXCEPTFSM_IDLE;
471			`extend_flush <= #1 1'b0;`
472			`extend_flush_last <= #1 1'b0;`
473			except_type <= #1 `OR1200_EXCEPT_NONE;
474			`end`
475	562	lampret	`else`
476			`// if (!if_stall & !id_freeze)`
477	504	lampret	state <= #1 `OR1200_EXCEPTFSM_FLU3;
478			`OR1200_EXCEPTFSM_FLU3:
479	562	lampret	`// if (!if_stall && !id_freeze)`
480	504	lampret	`begin`
481			`ifdef OR1200_VERBOSE
482			`// synopsys translate_off`
483			`if (except_flushpipe)`
484			`$display(" INFO: EPCR0 %h EEAR %h ESR %h", epcr, eear, esr);`
485			`// synopsys translate_on`
486			`endif
487			state <= #1 `OR1200_EXCEPTFSM_FLU4;
488			`end`
489			`OR1200_EXCEPTFSM_FLU4: begin
490	562	lampret	state <= #1 `OR1200_EXCEPTFSM_FLU5;
491			`extend_flush <= #1 1'b0;`
492			`extend_flush_last <= #1 1'b0; // damjan`
493			`end`
494	504	lampret	`OR1200_EXCEPTFSM_FLU5: begin
495	562	lampret	`if (!if_stall && !id_freeze) begin`
496	504	lampret	`ifdef OR1200_VERBOSE
497			`// synopsys translate_off`
498			`$display(" INFO: Just finished flushing pipeline.");`
499			`// synopsys translate_on`
500			`endif

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