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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  OR1200's Data MMU top level                                 ////

////                                                              ////

////  This file is part of the OpenRISC 1200 project              ////

////  http://www.opencores.org/cores/or1k/                        ////

////                                                              ////

////  Description                                                 ////

////  Instantiation of all DMMU blocks.                           ////

////                                                              ////

////  To Do:                                                      ////

////   - make it smaller and faster                               ////

////                                                              ////

////  Author(s):                                                  ////

////      - Damjan Lampret, lampret@opencores.org                 ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// Revision 1.5  2002/02/14 15:34:02  simons

// Lapsus fixed.

//

// Revision 1.4  2002/02/11 04:33:17  lampret

// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.

//

// Revision 1.3  2002/01/28 01:16:00  lampret

// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.

//

// Revision 1.2  2002/01/14 06:18:22  lampret

// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.

//

// Revision 1.1  2002/01/03 08:16:15  lampret

// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.

//

// Revision 1.6  2001/10/21 17:57:16  lampret

// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.

//

// Revision 1.5  2001/10/14 13:12:09  lampret

// MP3 version.

//

// Revision 1.1.1.1  2001/10/06 10:18:36  igorm

// no message

//

// Revision 1.1  2001/08/17 08:03:35  lampret

// *** empty log message ***

//

// Revision 1.2  2001/07/22 03:31:53  lampret

// Fixed RAM's oen bug. Cache bypass under development.

//

// Revision 1.1  2001/07/20 00:46:03  lampret

// Development version of RTL. Libraries are missing.

//

//

// synopsys translate_off

`include "timescale.v"

// synopsys translate_on

`include "or1200_defines.v"

//

// Data MMU

//

module or1200_dmmu_top(

        // Rst and clk

        clk, rst,

        // CPU i/f

        dc_en, dmmu_en, supv, dcpu_adr_i, dcpu_cycstb_i, dcpu_we_i,

        dcpu_tag_o, dcpu_err_o,

        // SPR access

        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,

        // DC i/f

        dcdmmu_err_i, dcdmmu_tag_i, dcdmmu_adr_o, dcdmmu_cycstb_o, dcdmmu_ci_o

);

parameter dw = `OR1200_OPERAND_WIDTH;

parameter aw = `OR1200_OPERAND_WIDTH;

//

// I/O

//

//

// Clock and reset

//

input                           clk;

input                           rst;

//

// CPU I/F

//

input                           dc_en;

input                           dmmu_en;

input                           supv;

input   [aw-1:0]         dcpu_adr_i;

input                           dcpu_cycstb_i;

input                           dcpu_we_i;

output  [3:0]                    dcpu_tag_o;

output                          dcpu_err_o;

//

// SPR access

//

input                           spr_cs;

input                           spr_write;

input   [aw-1:0]         spr_addr;

input   [31:0]                   spr_dat_i;

output  [31:0]                   spr_dat_o;

//

// DC I/F

//

input                           dcdmmu_err_i;

input   [3:0]                    dcdmmu_tag_i;

output  [aw-1:0]         dcdmmu_adr_o;

output                          dcdmmu_cycstb_o;

output                          dcdmmu_ci_o;

//

// Internal wires and regs

//

wire                            dtlb_spr_access;

wire    [31:`OR1200_DMMU_PS]    dtlb_ppn;

wire                            dtlb_hit;

wire                            dtlb_uwe;

wire                            dtlb_ure;

wire                            dtlb_swe;

wire                            dtlb_sre;

wire    [31:0]                   dtlb_dat_o;

wire                            dtlb_en;

wire                            dtlb_ci;

wire                            fault;

wire                            miss;

`ifdef OR1200_NO_DMMU

`else

reg                             dtlb_done;

reg     [31:`OR1200_DMMU_PS]    dcpu_vpn_r;

`endif

//

// Implemented bits inside match and translate registers

//

// dtlbwYmrX: vpn 31-10  v 0

// dtlbwYtrX: ppn 31-10  swe 9  sre 8  uwe 7  ure 6

//

// dtlb memory width:

// 19 bits for ppn

// 13 bits for vpn

// 1 bit for valid

// 4 bits for protection

// 1 bit for cache inhibit

`ifdef OR1200_NO_DMMU

//

// Put all outputs in inactive state

//

assign spr_dat_o = 32'h00000000;

assign dcdmmu_adr_o = dcpu_adr_i;

assign dcpu_tag_o = dcdmmu_tag_i;

assign dcdmmu_cycstb_o = dcpu_cycstb_i;

assign dcpu_err_o = dcdmmu_err_i;

assign dcdmmu_ci_o = `OR1200_DMMU_CI;

`else

//

// DTLB SPR access

//

// 0A00 - 0AFF  dtlbmr w0

// 0A00 - 0A3F  dtlbmr w0 [63:0]

//

// 0B00 - 0BFF  dtlbtr w0

// 0B00 - 0B3F  dtlbtr w0 [63:0]

//

assign dtlb_spr_access = spr_cs;

//

// Tags:

//

// OR1200_DTAG_TE - TLB miss Exception

// OR1200_DTAG_PE - Page fault Exception

//

assign dcpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : dcdmmu_tag_i;

//

// dcpu_err_o

//

assign dcpu_err_o = miss | fault | dcdmmu_err_i;

//

// Assert dtlb_done one clock cycle after new address and dtlb_en must be active.

//

always @(posedge clk or posedge rst)

        if (rst)

                dtlb_done <= #1 1'b0;

        else if (dtlb_en)

                dtlb_done <= #1 dcpu_cycstb_i;

        else

                dtlb_done <= #1 1'b0;

//

// Cut transfer if something goes wrong with translation. Also delayed signals because of translation delay.

//

assign dcdmmu_cycstb_o = (!dc_en & dmmu_en) ? ~(miss | fault) & dtlb_done & dcpu_cycstb_i : ~(miss | fault) & dcpu_cycstb_i;

//assign dcdmmu_cycstb_o = (dmmu_en) ? ~(miss | fault) & dcpu_cycstb_i : (miss | fault) ? 1'b0 : dcpu_cycstb_i;

//

// Cache Inhibit

//

assign dcdmmu_ci_o = dmmu_en ? dtlb_done & dtlb_ci : `OR1200_DMMU_CI;

//

// Register dcpu_adr_i's VPN for use when DMMU is not enabled but PPN is expected to come

// one clock cycle after offset part.

//

always @(posedge clk or posedge rst)

        if (rst)

                dcpu_vpn_r <= #1 {31-`OR1200_DMMU_PS{1'b0}};

        else

                dcpu_vpn_r <= #1 dcpu_adr_i[31:`OR1200_DMMU_PS];

//

// Physical address is either translated virtual address or

// simply equal when DMMU is disabled

//

// assign dcdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : {dcpu_vpn_r, dcpu_adr_i[`OR1200_DMMU_PS-1:0]};

assign dcdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : dcpu_adr_i;

//

// Output to SPRS unit

//

assign spr_dat_o = dtlb_spr_access ? dtlb_dat_o : 32'h00000000;

//

// Page fault exception logic

//

assign fault = dtlb_done &

                        (  (!dcpu_we_i & !supv & !dtlb_ure) // Load in user mode not enabled

                        || (!dcpu_we_i & supv & !dtlb_sre) // Load in supv mode not enabled

                        || (dcpu_we_i & !supv & !dtlb_uwe) // Store in user mode not enabled

                        || (dcpu_we_i & supv & !dtlb_swe) ); // Store in supv mode not enabled

//

// TLB Miss exception logic

//

assign miss = dtlb_done & !dtlb_hit;

//

// DTLB Enable

//

assign dtlb_en = dmmu_en & dcpu_cycstb_i;

//

// Instantiation of DTLB

//

or1200_dmmu_tlb or1200_dmmu_tlb(

        // Rst and clk

        .clk(clk),

        .rst(rst),

        // I/F for translation

        .tlb_en(dtlb_en),

        .vaddr(dcpu_adr_i),

        .hit(dtlb_hit),

        .ppn(dtlb_ppn),

        .uwe(dtlb_uwe),

        .ure(dtlb_ure),

        .swe(dtlb_swe),

        .sre(dtlb_sre),

        .ci(dtlb_ci),

        // SPR access

        .spr_cs(dtlb_spr_access),

        .spr_write(spr_write),

        .spr_addr(spr_addr),

        .spr_dat_i(spr_dat_i),

        .spr_dat_o(dtlb_dat_o)

);

`endif

endmodule