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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Exception logic                                    ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Handles all OR1K exceptions inside CPU block.               ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2002/01/14 21:11:50  lampret
// Changed alignment exception EPCR. Not tested yet.
//
// Revision 1.3  2002/01/14 19:09:57  lampret
// Fixed order of syscall and range exceptions.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.15  2001/11/27 23:13:11  lampret
// Fixed except_stop width and fixed EX PC for 1400444f no-ops.
//
// Revision 1.14  2001/11/23 08:38:51  lampret
// Changed DSR/DRR behavior and exception detection.
//
// Revision 1.13  2001/11/20 18:46:15  simons
// Break point bug fixed
//
// Revision 1.12  2001/11/18 09:58:28  lampret
// Fixed some l.trap typos.
//
// Revision 1.11  2001/11/18 08:36:28  lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.10  2001/11/13 10:02:21  lampret
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
//
// Revision 1.9  2001/11/10 03:43:57  lampret
// Fixed exceptions.
//
// Revision 1.8  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
`define OR1200_EXCEPTFSM_WIDTH 3
`define OR1200_EXCEPTFSM_IDLE   `OR1200_EXCEPTFSM_WIDTH'd0
`define OR1200_EXCEPTFSM_FLU1   `OR1200_EXCEPTFSM_WIDTH'd1
`define OR1200_EXCEPTFSM_FLU2   `OR1200_EXCEPTFSM_WIDTH'd2
`define OR1200_EXCEPTFSM_FLU3   `OR1200_EXCEPTFSM_WIDTH'd3
`define OR1200_EXCEPTFSM_FLU4   `OR1200_EXCEPTFSM_WIDTH'd4
`define OR1200_EXCEPTFSM_FLU5   `OR1200_EXCEPTFSM_WIDTH'd5
 
//
// Exception recognition and sequencing
//
 
module or1200_except(
        // Clock and reset
        clk, rst,
 
        // Internal i/f
        sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,
        sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick,
        branch_taken, id_freeze, ex_freeze, wb_freeze, if_stall,
        if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
        except_started, except_stop, has_dslot,
        spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
        esr, sr, lsu_addr
);
 
//
// I/O
//
input                           clk;
input                           rst;
input                           sig_ibuserr;
input                           sig_dbuserr;
input                           sig_illegal;
input                           sig_align;
input                           sig_range;
input                           sig_dtlbmiss;
input                           sig_dmmufault;
input                           sig_int;
input                           sig_syscall;
input                           sig_trap;
input                           sig_itlbmiss;
input                           sig_immufault;
input                           sig_tick;
input                           branch_taken;
input                           id_freeze;
input                           ex_freeze;
input                           wb_freeze;
input                           if_stall;
input   [31:0]                   if_pc;
output  [31:2]                  lr_sav;
input   [31:0]                   datain;
input   [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;
input                           epcr_we;
input                           eear_we;
input                           esr_we;
input                           pc_we;
output  [31:0]                   epcr;
output  [31:0]                   eear;
output  [`OR1200_SR_WIDTH-1:0]           esr;
input   [`OR1200_SR_WIDTH-1:0]           sr;
input   [31:0]                   lsu_addr;
output                          flushpipe;
output                          extend_flush;
output  [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
output                          except_start;
output                          except_started;
output  [12:0]                   except_stop;
input                           has_dslot;
output  [31:0]                   spr_dat_ppc;
output  [31:0]                   spr_dat_npc;
 
//
// Internal regs and wires
//
reg     [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
reg     [31:0]                   id_pc;
reg     [31:0]                   ex_pc;
reg     [31:0]                   wb_pc;
reg     [31:0]                   epcr;
reg     [31:0]                   eear;
reg     [`OR1200_SR_WIDTH-1:0]           esr;
reg     [2:0]                    id_exceptflags;
reg     [2:0]                    ex_exceptflags;
reg     [`OR1200_EXCEPTFSM_WIDTH-1:0]    state;
reg                             extend_flush;
reg                             extend_flush_last;
reg                             ex_dslot;
reg                             delayed1_ex_dslot;
reg                             delayed2_ex_dslot;
wire                            except_started;
wire    [12:0]                   except_trig;
wire                            except_flushpipe;
reg     [2:0]                    delayed_iee;
reg     [2:0]                    delayed_tee;
wire                            int_pending;
wire                            tick_pending;
 
//
// Simple combinatorial logic
//
assign except_started = extend_flush & except_start;
assign lr_sav = ex_pc[31:2];
assign spr_dat_ppc = wb_pc;
assign spr_dat_npc = has_dslot ? ex_pc : id_pc;
//assign except_start = (except_type != `OR1200_EXCEPT_NONE);  // damjan
assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
assign int_pending = sig_int & sr[`OR1200_SR_IEE] & delayed_iee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & delayed_tee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
 
//
// Order defines exception detection priority
//
assign except_trig = {
                        int_pending             & ~du_dsr[`OR1200_DU_DSR_IE],
                        ex_exceptflags[1]       & ~du_dsr[`OR1200_DU_DSR_IME],
                        ex_exceptflags[0]        & ~du_dsr[`OR1200_DU_DSR_IPFE],
                        ex_exceptflags[2]       & ~du_dsr[`OR1200_DU_DSR_BUSEE],
                        sig_illegal             & ~du_dsr[`OR1200_DU_DSR_IIE],
                        sig_align               & ~du_dsr[`OR1200_DU_DSR_AE],
                        sig_dtlbmiss            & ~du_dsr[`OR1200_DU_DSR_DME],
                        sig_dmmufault           & ~du_dsr[`OR1200_DU_DSR_DPFE],
                        sig_dbuserr             & ~du_dsr[`OR1200_DU_DSR_BUSEE],
                        tick_pending            & ~du_dsr[`OR1200_DU_DSR_TTE],
                        sig_range               & ~du_dsr[`OR1200_DU_DSR_RE],
                        sig_trap                & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
                        sig_syscall             & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
                };
assign except_stop = {
                        int_pending             & du_dsr[`OR1200_DU_DSR_IE],
                        ex_exceptflags[1]       & du_dsr[`OR1200_DU_DSR_IME],
                        ex_exceptflags[0]        & du_dsr[`OR1200_DU_DSR_IPFE],
                        ex_exceptflags[2]       & du_dsr[`OR1200_DU_DSR_BUSEE],
                        sig_illegal             & du_dsr[`OR1200_DU_DSR_IIE],
                        sig_align               & du_dsr[`OR1200_DU_DSR_AE],
                        sig_dtlbmiss            & du_dsr[`OR1200_DU_DSR_DME],
                        sig_dmmufault           & du_dsr[`OR1200_DU_DSR_DPFE],
                        sig_dbuserr             & du_dsr[`OR1200_DU_DSR_BUSEE],
                        tick_pending            & du_dsr[`OR1200_DU_DSR_TTE],
                        sig_range               & du_dsr[`OR1200_DU_DSR_RE],
                        sig_trap                & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
                        sig_syscall             & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
                };
 
//
// PC and Exception flags pipelines
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                id_pc <= #1 32'd0;
                id_exceptflags <= #1 3'b000;
        end
        else if (flushpipe) begin
                id_pc <= #1 32'h0000_0000;
                id_exceptflags <= #1 3'b000;
        end
        else if (!id_freeze) begin
                id_pc <= #1 if_pc;
                id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault };
        end
end
 
//
// delayed_iee
//
// SR[IEE] should not enable interrupts right away
// when it is restored with l.rfe. Instead delayed_iee
// together with SR[IEE] enables interrupts once
// pipeline is again ready.
//
always @(posedge rst or posedge clk)
        if (rst)
                delayed_iee <= #1 3'b000;
        else if (!sr[`OR1200_SR_IEE])
                delayed_iee <= #1 3'b000;
        else
                delayed_iee <= #1 {delayed_iee[1:0], 1'b1};
 
//
// delayed_tee
//
// SR[TEE] should not enable tick exceptions right away
// when it is restored with l.rfe. Instead delayed_tee
// together with SR[TEE] enables tick exceptions once
// pipeline is again ready.
//
always @(posedge rst or posedge clk)
        if (rst)
                delayed_tee <= #1 3'b000;
        else if (!sr[`OR1200_SR_TEE])
                delayed_tee <= #1 3'b000;
        else
                delayed_tee <= #1 {delayed_tee[1:0], 1'b1};
 
//
// PC and Exception flags pipelines
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                ex_dslot <= #1 1'b0;
                ex_pc <= #1 32'd0;
                ex_exceptflags <= #1 3'b000;
                delayed1_ex_dslot <= #1 1'b0;
                delayed2_ex_dslot <= #1 1'b0;
        end
        else if (flushpipe) begin
                ex_dslot <= #1 1'b0;
                ex_pc <= #1 32'h0000_0000;
                ex_exceptflags <= #1 3'b000;
                delayed1_ex_dslot <= #1 1'b0;
                delayed2_ex_dslot <= #1 1'b0;
        end
        else if (!ex_freeze & id_freeze) begin
                ex_dslot <= #1 1'b0;
                ex_pc <= #1 id_pc;
                ex_exceptflags <= #1 3'b000;
                delayed1_ex_dslot <= #1 ex_dslot;
                delayed2_ex_dslot <= #1 delayed1_ex_dslot;
        end
        else if (!ex_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                $display("%t: ex_pc <= %h", $time, id_pc);
// synopsys translate_on
`endif
                ex_dslot <= #1 branch_taken;
                ex_pc <= #1 id_pc;
                ex_exceptflags <= #1 id_exceptflags;
                delayed1_ex_dslot <= #1 ex_dslot;
                delayed2_ex_dslot <= #1 delayed1_ex_dslot;
        end
end
 
//
// PC and Exception flags pipelines
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                wb_pc <= #1 32'd0;
        end
        else if (!wb_freeze) begin
                wb_pc <= #1 ex_pc;
        end
end
 
//
// Flush pipeline
//
assign flushpipe = except_flushpipe | pc_we | extend_flush;
 
//
// We have started execution of exception handler:
//  1. Asserted for 3 clock cycles
//  2. Don't execute any instruction that is still in pipeline and is not part of exception handler
//
assign except_flushpipe = |except_trig & !state;
 
//
// Exception FSM that sequences execution of exception handler
//
// except_type signals which exception handler we start fetching in:
//  1. Asserted in next clock cycle after exception is recognized
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                state <= #1 `OR1200_EXCEPTFSM_IDLE;
                except_type <= #1 `OR1200_EXCEPT_NONE;
                extend_flush <= #1 1'b0;
                epcr <= #1 32'b0;
                eear <= #1 32'b0;
                esr <= #1 `OR1200_SR_WIDTH'b001;
                extend_flush_last <= #1 1'b0;
        end
        else begin
                case (state)    // synopsys full_case parallel_case
                        `OR1200_EXCEPTFSM_IDLE:
                                if (except_flushpipe) begin
                                        state <= #1 `OR1200_EXCEPTFSM_FLU1;
                                        extend_flush <= #1 1'b1;
                                        if (ex_dslot) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                                $display(" INFO: Exception during first delay slot instruction.");
// synopsys translate_on
`endif
                                        end
                                        else if (delayed1_ex_dslot) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                                $display(" INFO: Exception during second (NOP) delay slot instruction.");
// synopsys translate_on
`endif
                                        end
                                        else if (delayed2_ex_dslot) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                                $display(" INFO: Exception during third delay slot (SHOULD NOT HAPPEN).");
// synopsys translate_on
`endif
                                        end
                                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                                $display(" INFO: Exception during normal (no delay slot) instruction.");
// synopsys translate_on
`endif
                                        end
 
                                        esr <= #1 sr;
                                        casex (except_trig)
                                                13'b1_xxxx_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_INT;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_1xxx_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
                                                        eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_01xx_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_IPF;
                                                        eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_001x_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_BUSERR;
                                                        eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_0001_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_0000_1xxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_ALIGN;
                                                        eear <= #1 lsu_addr;
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
                                                end
                                                13'b0_0000_01xx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
                                                        eear <= #1 lsu_addr;
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
                                                end
                                                13'b0_0000_001x_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_DPF;
                                                        eear <= #1 lsu_addr;
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
                                                end
                                                13'b0_0000_0001_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_BUSERR;
                                                        eear <= #1 lsu_addr;
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
                                                end
                                                13'b0_0000_0000_1xxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_TICK;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_0000_0000_01xx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_RANGE;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_0000_0000_001x: begin
                                                        except_type <= #1 `OR1200_EXCEPT_TRAP;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_0000_0000_0001: begin
                                                        except_type <= #1 `OR1200_EXCEPT_SYSCALL;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                default:
                                                        except_type <= #1 `OR1200_EXCEPT_NONE;
                                        endcase
                                end
                                else if (pc_we) begin
                                        state <= #1 `OR1200_EXCEPTFSM_FLU1;
                                        extend_flush <= #1 1'b1;
                                end
                                else begin
                                        if (epcr_we)
                                                epcr <= #1 datain;
                                        if (eear_we)
                                                eear <= #1 datain;
                                        if (esr_we)
                                                esr <= #1 {1'b1, datain[`OR1200_SR_WIDTH-2:0]};
                                end
                        `OR1200_EXCEPTFSM_FLU1:
//                              if (!if_stall & !id_freeze)
                                        state <= #1 `OR1200_EXCEPTFSM_FLU2;
                        `OR1200_EXCEPTFSM_FLU2:
                                if (except_type == `OR1200_EXCEPT_TRAP) begin
                                        state <= #1 `OR1200_EXCEPTFSM_IDLE;
                                        extend_flush <= #1 1'b0;
                                        extend_flush_last <= #1 1'b0;
                                        except_type <= #1 `OR1200_EXCEPT_NONE;
                                end
                                else
//                              if (!if_stall & !id_freeze)
                                        state <= #1 `OR1200_EXCEPTFSM_FLU3;
                        `OR1200_EXCEPTFSM_FLU3:
//                              if (!if_stall && !id_freeze)
                                        begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                                if (except_flushpipe)
                                                        $display(" INFO: EPCR0 %h  EEAR %h  ESR %h", epcr, eear, esr);
// synopsys translate_on
`endif
                                                state <= #1 `OR1200_EXCEPTFSM_FLU4;
                                        end
                        `OR1200_EXCEPTFSM_FLU4: begin
                                        state <= #1 `OR1200_EXCEPTFSM_FLU5;
                                        extend_flush <= #1 1'b0;
                                        extend_flush_last <= #1 1'b0; // damjan
                                end
                        `OR1200_EXCEPTFSM_FLU5: begin
                                if (!if_stall && !id_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display(" INFO: Just finished flushing pipeline.");
// synopsys translate_on
`endif
                                state <= #1 `OR1200_EXCEPTFSM_IDLE;
                                except_type <= #1 `OR1200_EXCEPT_NONE;
                                extend_flush_last <= #1 1'b0;
                        end
                        end
                endcase
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Exception logic ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Handles all OR1K exceptions inside CPU block. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	589	lampret	`// Revision 1.4 2002/01/14 21:11:50 lampret`
48			`// Changed alignment exception EPCR. Not tested yet.`
49			`//`
50	571	lampret	`// Revision 1.3 2002/01/14 19:09:57 lampret`
51			`// Fixed order of syscall and range exceptions.`
52			`//`
53	570	lampret	`// Revision 1.2 2002/01/14 06:18:22 lampret`
54			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
55			`//`
56	562	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
57			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
58			`//`
59	504	lampret	`// Revision 1.15 2001/11/27 23:13:11 lampret`
60			`// Fixed except_stop width and fixed EX PC for 1400444f no-ops.`
61			`//`
62			`// Revision 1.14 2001/11/23 08:38:51 lampret`
63			`// Changed DSR/DRR behavior and exception detection.`
64			`//`
65			`// Revision 1.13 2001/11/20 18:46:15 simons`
66			`// Break point bug fixed`
67			`//`
68			`// Revision 1.12 2001/11/18 09:58:28 lampret`
69			`// Fixed some l.trap typos.`
70			`//`
71			`// Revision 1.11 2001/11/18 08:36:28 lampret`
72			`// For GDB changed single stepping and disabled trap exception.`
73			`//`
74			`// Revision 1.10 2001/11/13 10:02:21 lampret`
75			`// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)`
76			`//`
77			`// Revision 1.9 2001/11/10 03:43:57 lampret`
78			`// Fixed exceptions.`
79			`//`
80			`// Revision 1.8 2001/10/21 17:57:16 lampret`
81			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
82			`//`
83			`// Revision 1.7 2001/10/14 13:12:09 lampret`
84			`// MP3 version.`
85			`//`
86			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
87			`// no message`
88			`//`
89			`// Revision 1.2 2001/08/09 13:39:33 lampret`
90			`// Major clean-up.`
91			`//`
92			`// Revision 1.1 2001/07/20 00:46:03 lampret`
93			`// Development version of RTL. Libraries are missing.`
94			`//`
95			`//`
96
97			`// synopsys translate_off`
98			`include "timescale.v"
99			`// synopsys translate_on`
100			`include "or1200_defines.v"
101
102			`define OR1200_EXCEPTFSM_WIDTH 3
103			`define OR1200_EXCEPTFSM_IDLE `OR1200_EXCEPTFSM_WIDTH'd0
104			`define OR1200_EXCEPTFSM_FLU1 `OR1200_EXCEPTFSM_WIDTH'd1
105			`define OR1200_EXCEPTFSM_FLU2 `OR1200_EXCEPTFSM_WIDTH'd2
106			`define OR1200_EXCEPTFSM_FLU3 `OR1200_EXCEPTFSM_WIDTH'd3
107			`define OR1200_EXCEPTFSM_FLU4 `OR1200_EXCEPTFSM_WIDTH'd4
108			`define OR1200_EXCEPTFSM_FLU5 `OR1200_EXCEPTFSM_WIDTH'd5
109
110			`//`
111			`// Exception recognition and sequencing`
112			`//`
113
114			`module or1200_except(`
115			`// Clock and reset`
116			`clk, rst,`
117
118			`// Internal i/f`
119			`sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,`
120	589	lampret	`sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick,`
121	504	lampret	`branch_taken, id_freeze, ex_freeze, wb_freeze, if_stall,`
122			`if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,`
123	589	lampret	`except_started, except_stop, has_dslot,`
124			`spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,`
125	504	lampret	`esr, sr, lsu_addr`
126			`);`
127
128			`//`
129			`// I/O`
130			`//`
131			`input clk;`
132			`input rst;`
133			`input sig_ibuserr;`
134			`input sig_dbuserr;`
135			`input sig_illegal;`
136			`input sig_align;`
137			`input sig_range;`
138			`input sig_dtlbmiss;`
139			`input sig_dmmufault;`
140	589	lampret	`input sig_int;`
141	504	lampret	`input sig_syscall;`
142			`input sig_trap;`
143			`input sig_itlbmiss;`
144			`input sig_immufault;`
145	589	lampret	`input sig_tick;`
146	504	lampret	`input branch_taken;`
147			`input id_freeze;`
148			`input ex_freeze;`
149			`input wb_freeze;`
150			`input if_stall;`
151			`input [31:0] if_pc;`
152			`output [31:2] lr_sav;`
153			`input [31:0] datain;`
154			input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
155			`input epcr_we;`
156			`input eear_we;`
157			`input esr_we;`
158			`input pc_we;`
159			`output [31:0] epcr;`
160			`output [31:0] eear;`
161			output [`OR1200_SR_WIDTH-1:0] esr;
162			input [`OR1200_SR_WIDTH-1:0] sr;
163			`input [31:0] lsu_addr;`
164			`output flushpipe;`
165			`output extend_flush;`
166			output [`OR1200_EXCEPT_WIDTH-1:0] except_type;
167			`output except_start;`
168			`output except_started;`
169			`output [12:0] except_stop;`
170	589	lampret	`input has_dslot;`
171			`output [31:0] spr_dat_ppc;`
172			`output [31:0] spr_dat_npc;`
173	504	lampret
174			`//`
175			`// Internal regs and wires`
176			`//`
177			reg [`OR1200_EXCEPT_WIDTH-1:0] except_type;
178			`reg [31:0] id_pc;`
179			`reg [31:0] ex_pc;`
180			`reg [31:0] wb_pc;`
181			`reg [31:0] epcr;`
182			`reg [31:0] eear;`
183			reg [`OR1200_SR_WIDTH-1:0] esr;
184	589	lampret	`reg [2:0] id_exceptflags;`
185			`reg [2:0] ex_exceptflags;`
186	504	lampret	reg [`OR1200_EXCEPTFSM_WIDTH-1:0] state;
187			`reg extend_flush;`
188			`reg extend_flush_last;`
189			`reg ex_dslot;`
190			`reg delayed1_ex_dslot;`
191			`reg delayed2_ex_dslot;`
192			`wire except_started;`
193			`wire [12:0] except_trig;`
194			`wire except_flushpipe;`
195	589	lampret	`reg [2:0] delayed_iee;`
196			`reg [2:0] delayed_tee;`
197			`wire int_pending;`
198			`wire tick_pending;`
199	504	lampret
200			`//`
201			`// Simple combinatorial logic`
202			`//`
203			`assign except_started = extend_flush & except_start;`
204			`assign lr_sav = ex_pc[31:2];`
205	589	lampret	`assign spr_dat_ppc = wb_pc;`
206			`assign spr_dat_npc = has_dslot ? ex_pc : id_pc;`
207	562	lampret	//assign except_start = (except_type != `OR1200_EXCEPT_NONE); // damjan
208			assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
209	589	lampret	assign int_pending = sig_int & sr[`OR1200_SR_IEE] & delayed_iee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
210			assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & delayed_tee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
211	504	lampret
212			`//`
213			`// Order defines exception detection priority`
214			`//`
215			`assign except_trig = {`
216	589	lampret	int_pending & ~du_dsr[`OR1200_DU_DSR_IE],
217			ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IME],
218			ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_IPFE],
219			ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
220	504	lampret	sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE],
221			sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
222			sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
223			sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
224			sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
225	589	lampret	tick_pending & ~du_dsr[`OR1200_DU_DSR_TTE],
226	570	lampret	sig_range & ~du_dsr[`OR1200_DU_DSR_RE],
227	562	lampret	sig_trap & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
228	570	lampret	sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
229	504	lampret	`};`
230			`assign except_stop = {`
231	589	lampret	int_pending & du_dsr[`OR1200_DU_DSR_IE],
232			ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IME],
233			ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_IPFE],
234			ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_BUSEE],
235	504	lampret	sig_illegal & du_dsr[`OR1200_DU_DSR_IIE],
236			sig_align & du_dsr[`OR1200_DU_DSR_AE],
237			sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
238			sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
239			sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
240	589	lampret	tick_pending & du_dsr[`OR1200_DU_DSR_TTE],
241	570	lampret	sig_range & du_dsr[`OR1200_DU_DSR_RE],
242	562	lampret	sig_trap & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
243	570	lampret	sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
244	504	lampret	`};`
245
246			`//`
247			`// PC and Exception flags pipelines`
248			`//`
249			`always @(posedge clk or posedge rst) begin`
250			`if (rst) begin`
251			`id_pc <= #1 32'd0;`
252	589	lampret	`id_exceptflags <= #1 3'b000;`
253	504	lampret	`end`
254	562	lampret	`else if (flushpipe) begin`
255			`id_pc <= #1 32'h0000_0000;`
256	589	lampret	`id_exceptflags <= #1 3'b000;`
257	562	lampret	`end`
258	504	lampret	`else if (!id_freeze) begin`
259			`id_pc <= #1 if_pc;`
260	589	lampret	`id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault };`
261	504	lampret	`end`
262			`end`
263
264			`//`
265	589	lampret	`// delayed_iee`
266	504	lampret	`//`
267	589	lampret	`// SR[IEE] should not enable interrupts right away`
268			`// when it is restored with l.rfe. Instead delayed_iee`
269			`// together with SR[IEE] enables interrupts once`
270	504	lampret	`// pipeline is again ready.`
271			`//`
272			`always @(posedge rst or posedge clk)`
273			`if (rst)`
274	589	lampret	`delayed_iee <= #1 3'b000;`
275			else if (!sr[`OR1200_SR_IEE])
276			`delayed_iee <= #1 3'b000;`
277	504	lampret	`else`
278	589	lampret	`delayed_iee <= #1 {delayed_iee[1:0], 1'b1};`
279	504	lampret
280			`//`
281	589	lampret	`// delayed_tee`
282			`//`
283			`// SR[TEE] should not enable tick exceptions right away`
284			`// when it is restored with l.rfe. Instead delayed_tee`
285			`// together with SR[TEE] enables tick exceptions once`
286			`// pipeline is again ready.`
287			`//`
288			`always @(posedge rst or posedge clk)`
289			`if (rst)`
290			`delayed_tee <= #1 3'b000;`
291			else if (!sr[`OR1200_SR_TEE])
292			`delayed_tee <= #1 3'b000;`
293			`else`
294			`delayed_tee <= #1 {delayed_tee[1:0], 1'b1};`
295
296			`//`
297	504	lampret	`// PC and Exception flags pipelines`
298			`//`
299			`always @(posedge clk or posedge rst) begin`
300			`if (rst) begin`
301			`ex_dslot <= #1 1'b0;`
302			`ex_pc <= #1 32'd0;`
303	589	lampret	`ex_exceptflags <= #1 3'b000;`
304	504	lampret	`delayed1_ex_dslot <= #1 1'b0;`
305			`delayed2_ex_dslot <= #1 1'b0;`
306			`end`
307	562	lampret	`else if (flushpipe) begin`
308			`ex_dslot <= #1 1'b0;`
309			`ex_pc <= #1 32'h0000_0000;`
310	589	lampret	`ex_exceptflags <= #1 3'b000;`
311	562	lampret	`delayed1_ex_dslot <= #1 1'b0;`
312			`delayed2_ex_dslot <= #1 1'b0;`
313			`end`
314	504	lampret	`else if (!ex_freeze & id_freeze) begin`
315			`ex_dslot <= #1 1'b0;`
316			`ex_pc <= #1 id_pc;`
317	589	lampret	`ex_exceptflags <= #1 3'b000;`
318	504	lampret	`delayed1_ex_dslot <= #1 ex_dslot;`
319			`delayed2_ex_dslot <= #1 delayed1_ex_dslot;`
320			`end`
321			`else if (!ex_freeze) begin`
322			`ifdef OR1200_VERBOSE
323			`// synopsys translate_off`
324			`$display("%t: ex_pc <= %h", $time, id_pc);`
325			`// synopsys translate_on`
326			`endif
327			`ex_dslot <= #1 branch_taken;`
328			`ex_pc <= #1 id_pc;`
329			`ex_exceptflags <= #1 id_exceptflags;`
330			`delayed1_ex_dslot <= #1 ex_dslot;`
331			`delayed2_ex_dslot <= #1 delayed1_ex_dslot;`
332			`end`
333			`end`
334
335			`//`
336			`// PC and Exception flags pipelines`
337			`//`
338			`always @(posedge clk or posedge rst) begin`
339			`if (rst) begin`
340			`wb_pc <= #1 32'd0;`
341			`end`
342			`else if (!wb_freeze) begin`
343			`wb_pc <= #1 ex_pc;`
344			`end`
345			`end`
346
347			`//`
348			`// Flush pipeline`
349			`//`
350	562	lampret	`assign flushpipe = except_flushpipe \| pc_we \| extend_flush;`
351	504	lampret
352			`//`
353			`// We have started execution of exception handler:`
354			`// 1. Asserted for 3 clock cycles`
355			`// 2. Don't execute any instruction that is still in pipeline and is not part of exception handler`
356			`//`
357	562	lampret	`assign except_flushpipe = \|except_trig & !state;`
358	504	lampret
359			`//`
360			`// Exception FSM that sequences execution of exception handler`
361			`//`
362			`// except_type signals which exception handler we start fetching in:`
363			`// 1. Asserted in next clock cycle after exception is recognized`
364			`//`
365			`always @(posedge clk or posedge rst) begin`
366			`if (rst) begin`
367			state <= #1 `OR1200_EXCEPTFSM_IDLE;
368			except_type <= #1 `OR1200_EXCEPT_NONE;
369			`extend_flush <= #1 1'b0;`
370			`epcr <= #1 32'b0;`
371			`eear <= #1 32'b0;`
372	589	lampret	esr <= #1 `OR1200_SR_WIDTH'b001;
373	504	lampret	`extend_flush_last <= #1 1'b0;`
374			`end`
375			`else begin`
376			`case (state) // synopsys full_case parallel_case`
377			`OR1200_EXCEPTFSM_IDLE:
378			`if (except_flushpipe) begin`
379			state <= #1 `OR1200_EXCEPTFSM_FLU1;
380			`extend_flush <= #1 1'b1;`
381			`if (ex_dslot) begin`
382			`ifdef OR1200_VERBOSE
383			`// synopsys translate_off`
384			`$display(" INFO: Exception during first delay slot instruction.");`
385			`// synopsys translate_on`
386			`endif
387			`end`
388			`else if (delayed1_ex_dslot) begin`
389			`ifdef OR1200_VERBOSE
390			`// synopsys translate_off`
391			`$display(" INFO: Exception during second (NOP) delay slot instruction.");`
392			`// synopsys translate_on`
393			`endif
394			`end`
395			`else if (delayed2_ex_dslot) begin`
396			`ifdef OR1200_VERBOSE
397			`// synopsys translate_off`
398			`$display(" INFO: Exception during third delay slot (SHOULD NOT HAPPEN).");`
399			`// synopsys translate_on`
400			`endif
401			`end`
402			`else begin`
403			`ifdef OR1200_VERBOSE
404			`// synopsys translate_off`
405			`$display(" INFO: Exception during normal (no delay slot) instruction.");`
406			`// synopsys translate_on`
407			`endif
408			`end`
409
410			`esr <= #1 sr;`
411			`casex (except_trig)`
412			`13'b1_xxxx_xxxx_xxxx: begin`
413	589	lampret	except_type <= #1 `OR1200_EXCEPT_INT;
414	504	lampret	`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
415			`end`
416			`13'b0_1xxx_xxxx_xxxx: begin`
417			except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
418			`eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
419			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
420			`end`
421			`13'b0_01xx_xxxx_xxxx: begin`
422			except_type <= #1 `OR1200_EXCEPT_IPF;
423			`eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
424			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
425			`end`
426			`13'b0_001x_xxxx_xxxx: begin`
427			except_type <= #1 `OR1200_EXCEPT_BUSERR;
428			`eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
429			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
430			`end`
431			`13'b0_0001_xxxx_xxxx: begin`
432			except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
433			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
434			`end`
435			`13'b0_0000_1xxx_xxxx: begin`
436			except_type <= #1 `OR1200_EXCEPT_ALIGN;
437			`eear <= #1 lsu_addr;`
438	571	lampret	`epcr <= #1 ex_dslot ? wb_pc : ex_pc;`
439	504	lampret	`end`
440			`13'b0_0000_01xx_xxxx: begin`
441			except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
442			`eear <= #1 lsu_addr;`
443			`epcr <= #1 ex_dslot ? wb_pc : ex_pc;`
444			`end`
445			`13'b0_0000_001x_xxxx: begin`
446			except_type <= #1 `OR1200_EXCEPT_DPF;
447			`eear <= #1 lsu_addr;`
448			`epcr <= #1 ex_dslot ? wb_pc : ex_pc;`
449			`end`
450			`13'b0_0000_0001_xxxx: begin`
451			except_type <= #1 `OR1200_EXCEPT_BUSERR;
452			`eear <= #1 lsu_addr;`
453	562	lampret	`epcr <= #1 ex_dslot ? wb_pc : ex_pc;`
454	504	lampret	`end`
455			`13'b0_0000_0000_1xxx: begin`
456	589	lampret	except_type <= #1 `OR1200_EXCEPT_TICK;
457	504	lampret	`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
458			`end`
459			`13'b0_0000_0000_01xx: begin`
460			except_type <= #1 `OR1200_EXCEPT_RANGE;
461			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
462			`end`
463			`13'b0_0000_0000_001x: begin`
464			except_type <= #1 `OR1200_EXCEPT_TRAP;
465			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
466			`end`
467			`13'b0_0000_0000_0001: begin`
468			except_type <= #1 `OR1200_EXCEPT_SYSCALL;
469			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
470			`end`
471			`default:`
472			except_type <= #1 `OR1200_EXCEPT_NONE;
473			`endcase`
474			`end`
475			`else if (pc_we) begin`
476			state <= #1 `OR1200_EXCEPTFSM_FLU1;
477			`extend_flush <= #1 1'b1;`
478			`end`
479			`else begin`
480			`if (epcr_we)`
481			`epcr <= #1 datain;`
482			`if (eear_we)`
483			`eear <= #1 datain;`
484			`if (esr_we)`
485	589	lampret	esr <= #1 {1'b1, datain[`OR1200_SR_WIDTH-2:0]};
486	504	lampret	`end`
487			`OR1200_EXCEPTFSM_FLU1:
488	562	lampret	`// if (!if_stall & !id_freeze)`
489	504	lampret	state <= #1 `OR1200_EXCEPTFSM_FLU2;
490			`OR1200_EXCEPTFSM_FLU2:
491			if (except_type == `OR1200_EXCEPT_TRAP) begin
492			state <= #1 `OR1200_EXCEPTFSM_IDLE;
493			`extend_flush <= #1 1'b0;`
494			`extend_flush_last <= #1 1'b0;`
495			except_type <= #1 `OR1200_EXCEPT_NONE;
496			`end`
497	562	lampret	`else`
498			`// if (!if_stall & !id_freeze)`
499	504	lampret	state <= #1 `OR1200_EXCEPTFSM_FLU3;
500			`OR1200_EXCEPTFSM_FLU3:

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