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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's generate PC                                        ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  PC, interface to IC.                                        ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2002/01/18 07:56:00  lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/20 18:46:15  simons
// Break point bug fixed
//
// Revision 1.9  2001/11/18 09:58:28  lampret
// Fixed some l.trap typos.
//
// Revision 1.8  2001/11/18 08:36:28  lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_genpc(
        // Clock and reset
        clk, rst,
 
        // External i/f to IC
        icpu_adr_o, icpu_cyc_o, icpu_stb_o, icpu_sel_o, icpu_tag_o,
        icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i,
 
        // Internal i/f
        branch_op, except_type, except_prefix,
        branch_addrofs, lr_restor, flag, taken, except_start,
        binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
        genpc_freeze, flushpipe, no_more_dslot
);
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// External i/f to IC
//
output  [31:0]                   icpu_adr_o;
output                          icpu_cyc_o;
output                          icpu_stb_o;
output  [3:0]                    icpu_sel_o;
output  [3:0]                    icpu_tag_o;
input                           icpu_ack_i;
input                           icpu_rty_i;
input                           icpu_err_i;
input   [31:0]                   icpu_adr_i;
 
//
// Internal i/f
//
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
input   [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
input                                   except_prefix;
input   [31:2]                  branch_addrofs;
input   [31:0]                   lr_restor;
input                           flag;
output                          taken;
input                           except_start;
input   [31:2]                  binsn_addr;
input   [31:0]                   epcr;
input   [31:0]                   spr_dat_i;
input                           spr_pc_we;
input                           genpc_refetch;
input                           genpc_freeze;
input                           flushpipe;
input                           no_more_dslot;
 
//
// Internal wires and regs
//
reg     [31:2]                  pcreg;
reg     [31:0]                   pc;
reg                             taken;  /* Set to in case of jump or taken branch */
reg                             dslot;  /* set when fetching delay slot insn */
reg                             btarget; /* set when fetching branch target insns */
 
//
// Address of insn to be fecthed
//
assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
// assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
 
//
// Control access to IC subsystem
//
// assign icpu_cyc_o = !genpc_freeze & !no_more_dslot;
assign icpu_cyc_o = !genpc_freeze;
assign icpu_stb_o = icpu_cyc_o;
assign icpu_sel_o = 4'b1111;
assign icpu_tag_o = `OR1200_ITAG_NI;
 
//
// Async calculation of new PC value. This value is used for addressing the IC.
//
always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type
        or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin
        casex ({spr_pc_we, except_start, branch_op})    // synopsys parallel_case
                {2'b00, `OR1200_BRANCHOP_NOP}: begin
                        pc = {pcreg + 'd1, 2'b0};
                        taken = 1'b0;
                end
                {2'b00, `OR1200_BRANCHOP_J}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_J: pc <= branch_addrofs %h", $time, branch_addrofs);
// synopsys translate_on
`endif
                        pc = {branch_addrofs, 2'b0};
                        taken = 1'b1;
                end
                {2'b00, `OR1200_BRANCHOP_JR}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_JR: pc <= lr_restor %h", $time, lr_restor);
// synopsys translate_on
`endif
                        pc = lr_restor;
                        taken = 1'b1;
                end
                {2'b00, `OR1200_BRANCHOP_BAL}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_BAL: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
                        pc = {binsn_addr + branch_addrofs, 2'b0};
                        taken = 1'b1;
                end
                {2'b00, `OR1200_BRANCHOP_BF}:
                        if (flag) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
                                pc = {binsn_addr + branch_addrofs, 2'b0};
                                taken = 1'b1;
                        end
                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BF: not taken", $time);
// synopsys translate_on
`endif
                                pc = {pcreg + 'd1, 2'b0};
                                taken = 1'b0;
                        end
                {2'b00, `OR1200_BRANCHOP_BNF}:
                        if (flag) begin
                                pc = {pcreg + 'd1, 2'b0};
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BNF: not taken", $time);
// synopsys translate_on
`endif
                                taken = 1'b0;
                        end
                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BNF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
                                pc = {binsn_addr + branch_addrofs, 2'b0};
                                taken = 1'b1;
                        end
                {2'b00, `OR1200_BRANCHOP_RFE}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);
// synopsys translate_on
`endif
                        pc = epcr;
                        taken = 1'b1;
                end
                {2'b01, 3'bxxx}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("Starting exception: %h.", except_type);
// synopsys translate_on
`endif
                        pc = { {4{except_prefix}}, 16'h0000, except_type, 8'h00};
                        taken = 1'b1;
                end
                default: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("l.mtspr writing into PC: %h.", spr_dat_i);
// synopsys translate_on
`endif
                        pc = spr_dat_i;
                        taken = 1'b0;
                end
        endcase
end
 
//
// PC register
//
always @(posedge clk or posedge rst)
        if (rst)
                pcreg <= #1 30'd63;
        else if (spr_pc_we)
                pcreg <= #1 spr_dat_i[31:2];
        else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
//      else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
                pcreg <= #1 pc[31:2];
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's generate PC ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// PC, interface to IC. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	617	lampret	`// Revision 1.3 2002/01/18 07:56:00 lampret`
48			`// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.`
49			`//`
50	589	lampret	`// Revision 1.2 2002/01/14 06:18:22 lampret`
51			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
52			`//`
53	562	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
54			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
55			`//`
56	504	lampret	`// Revision 1.10 2001/11/20 18:46:15 simons`
57			`// Break point bug fixed`
58			`//`
59			`// Revision 1.9 2001/11/18 09:58:28 lampret`
60			`// Fixed some l.trap typos.`
61			`//`
62			`// Revision 1.8 2001/11/18 08:36:28 lampret`
63			`// For GDB changed single stepping and disabled trap exception.`
64			`//`
65			`// Revision 1.7 2001/10/21 17:57:16 lampret`
66			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
67			`//`
68			`// Revision 1.6 2001/10/14 13:12:09 lampret`
69			`// MP3 version.`
70			`//`
71			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
72			`// no message`
73			`//`
74			`// Revision 1.1 2001/08/09 13:39:33 lampret`
75			`// Major clean-up.`
76			`//`
77			`//`
78
79			`// synopsys translate_off`
80			`include "timescale.v"
81			`// synopsys translate_on`
82			`include "or1200_defines.v"
83
84			`module or1200_genpc(`
85			`// Clock and reset`
86			`clk, rst,`
87
88			`// External i/f to IC`
89			`icpu_adr_o, icpu_cyc_o, icpu_stb_o, icpu_sel_o, icpu_tag_o,`
90			`icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i,`
91
92			`// Internal i/f`
93	589	lampret	`branch_op, except_type, except_prefix,`
94	504	lampret	`branch_addrofs, lr_restor, flag, taken, except_start,`
95	562	lampret	`binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,`
96	617	lampret	`genpc_freeze, flushpipe, no_more_dslot`
97	504	lampret	`);`
98
99			`//`
100			`// I/O`
101			`//`
102
103			`//`
104			`// Clock and reset`
105			`//`
106			`input clk;`
107			`input rst;`
108
109			`//`
110			`// External i/f to IC`
111			`//`
112			`output [31:0] icpu_adr_o;`
113			`output icpu_cyc_o;`
114			`output icpu_stb_o;`
115			`output [3:0] icpu_sel_o;`
116			`output [3:0] icpu_tag_o;`
117			`input icpu_ack_i;`
118			`input icpu_rty_i;`
119			`input icpu_err_i;`
120			`input [31:0] icpu_adr_i;`
121
122			`//`
123			`// Internal i/f`
124			`//`
125			input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
126			input [`OR1200_EXCEPT_WIDTH-1:0] except_type;
127	589	lampret	`input except_prefix;`
128	504	lampret	`input [31:2] branch_addrofs;`
129			`input [31:0] lr_restor;`
130			`input flag;`
131			`output taken;`
132			`input except_start;`
133			`input [31:2] binsn_addr;`
134			`input [31:0] epcr;`
135			`input [31:0] spr_dat_i;`
136			`input spr_pc_we;`
137			`input genpc_refetch;`
138	562	lampret	`input genpc_freeze;`
139			`input flushpipe;`
140	617	lampret	`input no_more_dslot;`
141	504	lampret
142			`//`
143			`// Internal wires and regs`
144			`//`
145			`reg [31:2] pcreg;`
146			`reg [31:0] pc;`
147			`reg taken; /* Set to in case of jump or taken branch */`
148			`reg dslot; /* set when fetching delay slot insn */`
149			`reg btarget; /* set when fetching branch target insns */`
150
151			`//`
152			`// Address of insn to be fecthed`
153			`//`
154	617	lampret	`assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i \| genpc_refetch) ? icpu_adr_i : pc;`
155			`// assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i \| genpc_refetch) ? icpu_adr_i : pc;`
156	504	lampret
157			`//`
158			`// Control access to IC subsystem`
159			`//`
160	617	lampret	`// assign icpu_cyc_o = !genpc_freeze & !no_more_dslot;`
161	562	lampret	`assign icpu_cyc_o = !genpc_freeze;`
162			`assign icpu_stb_o = icpu_cyc_o;`
163	504	lampret	`assign icpu_sel_o = 4'b1111;`
164			assign icpu_tag_o = `OR1200_ITAG_NI;
165
166			`//`
167			`// Async calculation of new PC value. This value is used for addressing the IC.`
168			`//`
169			`always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type`
170	589	lampret	`or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin`
171	504	lampret	`casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case`
172			{2'b00, `OR1200_BRANCHOP_NOP}: begin
173			`pc = {pcreg + 'd1, 2'b0};`
174			`taken = 1'b0;`
175			`end`
176			{2'b00, `OR1200_BRANCHOP_J}: begin
177			`ifdef OR1200_VERBOSE
178			`// synopsys translate_off`
179			`$display("%t: BRANCHOP_J: pc <= branch_addrofs %h", $time, branch_addrofs);`
180			`// synopsys translate_on`
181			`endif
182			`pc = {branch_addrofs, 2'b0};`
183			`taken = 1'b1;`
184			`end`
185			{2'b00, `OR1200_BRANCHOP_JR}: begin
186			`ifdef OR1200_VERBOSE
187			`// synopsys translate_off`
188			`$display("%t: BRANCHOP_JR: pc <= lr_restor %h", $time, lr_restor);`
189			`// synopsys translate_on`
190			`endif
191			`pc = lr_restor;`
192			`taken = 1'b1;`
193			`end`
194			{2'b00, `OR1200_BRANCHOP_BAL}: begin
195			`ifdef OR1200_VERBOSE
196			`// synopsys translate_off`
197			`$display("%t: BRANCHOP_BAL: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);`
198			`// synopsys translate_on`
199			`endif
200			`pc = {binsn_addr + branch_addrofs, 2'b0};`
201			`taken = 1'b1;`
202			`end`
203			{2'b00, `OR1200_BRANCHOP_BF}:
204			`if (flag) begin`
205			`ifdef OR1200_VERBOSE
206			`// synopsys translate_off`
207			`$display("%t: BRANCHOP_BF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);`
208			`// synopsys translate_on`
209			`endif
210			`pc = {binsn_addr + branch_addrofs, 2'b0};`
211			`taken = 1'b1;`
212			`end`
213			`else begin`
214			`ifdef OR1200_VERBOSE
215			`// synopsys translate_off`
216			`$display("%t: BRANCHOP_BF: not taken", $time);`
217			`// synopsys translate_on`
218			`endif
219			`pc = {pcreg + 'd1, 2'b0};`
220			`taken = 1'b0;`
221			`end`
222			{2'b00, `OR1200_BRANCHOP_BNF}:
223			`if (flag) begin`
224			`pc = {pcreg + 'd1, 2'b0};`
225			`ifdef OR1200_VERBOSE
226			`// synopsys translate_off`
227			`$display("%t: BRANCHOP_BNF: not taken", $time);`
228			`// synopsys translate_on`
229			`endif
230			`taken = 1'b0;`
231			`end`
232			`else begin`
233			`ifdef OR1200_VERBOSE
234			`// synopsys translate_off`
235			`$display("%t: BRANCHOP_BNF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);`
236			`// synopsys translate_on`
237			`endif
238			`pc = {binsn_addr + branch_addrofs, 2'b0};`
239			`taken = 1'b1;`
240			`end`
241			{2'b00, `OR1200_BRANCHOP_RFE}: begin
242			`ifdef OR1200_VERBOSE
243			`// synopsys translate_off`
244			`$display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);`
245			`// synopsys translate_on`
246			`endif
247			`pc = epcr;`
248			`taken = 1'b1;`
249			`end`
250			`{2'b01, 3'bxxx}: begin`
251			`ifdef OR1200_VERBOSE
252			`// synopsys translate_off`
253			`$display("Starting exception: %h.", except_type);`
254			`// synopsys translate_on`
255			`endif
256	589	lampret	`pc = { {4{except_prefix}}, 16'h0000, except_type, 8'h00};`
257	504	lampret	`taken = 1'b1;`
258			`end`
259			`default: begin`
260			`ifdef OR1200_VERBOSE
261			`// synopsys translate_off`
262			`$display("l.mtspr writing into PC: %h.", spr_dat_i);`
263			`// synopsys translate_on`
264			`endif
265			`pc = spr_dat_i;`
266			`taken = 1'b0;`
267			`end`
268			`endcase`
269			`end`
270
271			`//`
272			`// PC register`
273			`//`
274			`always @(posedge clk or posedge rst)`
275			`if (rst)`
276			`pcreg <= #1 30'd63;`
277			`else if (spr_pc_we)`
278			`pcreg <= #1 spr_dat_i[31:2];`
279	617	lampret	`else if (no_more_dslot \| except_start \| !genpc_freeze & !icpu_rty_i & !genpc_refetch)`
280			`// else if (except_start \| !genpc_freeze & !icpu_rty_i & !genpc_refetch)`
281	504	lampret	`pcreg <= #1 pc[31:2];`
282
283			`endmodule`

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