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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's IC FSM                                             ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Data cache state machine                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from ic.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:46  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
`define OR1200_ICFSM_IDLE       3'd0
`define OR1200_ICFSM_DOLOAD     3'd1
`define OR1200_ICFSM_LREFILL3   3'd2
 
//
// Data cache FSM for cache line of 16 bytes (4x singleword)
//
 
module or1200_ic_fsm(
        // Clock and reset
        clk, rst,
 
        // Internal i/f to top level IC
        ic_en, icimmu_cyc_i, icimmu_stb_i, icimmu_ci_i, icpu_sel_i,
        tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
        icram_we, biu_read, first_hit_ack, first_miss_ack, first_miss_err,
        burst
);
 
//
// I/O
//
input                           clk;
input                           rst;
input                           ic_en;
input                           icimmu_cyc_i;
input                           icimmu_stb_i;
input                           icimmu_ci_i;
input   [3:0]                    icpu_sel_i;
input                           tagcomp_miss;
input                           biudata_valid;
input                           biudata_error;
input   [31:0]                   start_addr;
output  [31:0]                   saved_addr;
output  [3:0]                    icram_we;
output                          biu_read;
output                          first_hit_ack;
output                          first_miss_ack;
output                          first_miss_err;
output                          burst;
 
//
// Internal wires and regs
//
reg     [31:0]                   saved_addr;
reg     [2:0]                    state;
reg     [2:0]                    cnt;
reg                             hitmiss_eval;
reg                             load;
 
//
// Generate of ICRAM write enables
//
assign icram_we = {4{load & biudata_valid}};
 
//
// BIU read and write
//
assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
 
//
// Assert for cache hit first word ready
// Assert for cache miss first word stored/loaded OK
// Assert for cache miss first word stored/loaded with an error
//
assign first_hit_ack = (state == `OR1200_ICFSM_DOLOAD) & hitmiss_eval & !tagcomp_miss & !icimmu_ci_i;
assign first_miss_ack = (state == `OR1200_ICFSM_DOLOAD) & (tagcomp_miss | icimmu_ci_i) & biudata_valid;
assign first_miss_err = (state == `OR1200_ICFSM_DOLOAD) & (tagcomp_miss | icimmu_ci_i) & biudata_error;
 
//
// Assert burst when doing reload of complete cache line
//
assign burst = (state == `OR1200_ICFSM_DOLOAD) & tagcomp_miss
                | (state == `OR1200_ICFSM_LREFILL3);
 
//
// Main IC FSM
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                state <= #1 `OR1200_ICFSM_IDLE;
                saved_addr <= #1 32'b0;
                hitmiss_eval <= #1 1'b0;
                load <= #1 1'b0;
                cnt <= #1 3'b000;
        end
        else
        case (state)    // synopsys parallel_case
                `OR1200_ICFSM_IDLE :
                        if (ic_en & icimmu_cyc_i & icimmu_stb_i) begin                  // load
                                state <= #1 `OR1200_ICFSM_DOLOAD;
                                saved_addr <= #1 start_addr;
                                hitmiss_eval <= #1 1'b1;
                                load <= #1 1'b1;
                        end
                        else begin                                                      // idle
                                state <= #1 `OR1200_ICFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                        end
                `OR1200_ICFSM_DOLOAD:
                        if (hitmiss_eval & !(icimmu_cyc_i & icimmu_stb_i)) begin        // load aborted (usually caused by IMMU)
                                state <= #1 `OR1200_ICFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                        end
                        else if (icimmu_ci_i & biudata_valid) begin     // load from cache inhibit page
                                state <= #1 `OR1200_ICFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                        end
                        else if (tagcomp_miss & biudata_valid) begin    // load missed, finish current external load and refill
                                state <= #1 `OR1200_ICFSM_LREFILL3;
                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
                                hitmiss_eval <= #1 1'b0;
                                cnt <= #1 `OR1200_ICLS-2;
                        end
                        else if (!tagcomp_miss & !icimmu_ci_i) begin    // load hit and not cache inhibit, finish immediately
                                state <= #1 `OR1200_ICFSM_DOLOAD;
                                saved_addr <= #1 start_addr;
                                hitmiss_eval <= #1 1'b1;
                                load <= #1 1'b1;
                        end
                        else if (!icimmu_cyc_i | !icimmu_stb_i) begin   // load aborted (usually caused by exception)
                                state <= #1 `OR1200_ICFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                        end
                        else                                            // load in-progress
                                hitmiss_eval <= #1 1'b0;
                `OR1200_ICFSM_LREFILL3 : begin
                        if (biudata_valid && (|cnt)) begin              // refill ack, more loads to come
                                cnt <= #1 cnt - 'd1;
                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
                        end
                        else if (biudata_valid) begin                   // last load of line refill
                                state <= #1 `OR1200_ICFSM_IDLE;
                                saved_addr <= #1 start_addr;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                        end
                end
                default:
                        state <= #1 `OR1200_ICFSM_IDLE;
        endcase
end
 
endmodule

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[/] [or1k/] [tags/] [rel_5/] [or1200/] [rtl/] [verilog/] [or1200_ic_fsm.v] - Blame information for rev 562

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's IC FSM ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Data cache state machine ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	562	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
48			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
49			`//`
50	504	lampret	`// Revision 1.9 2001/10/21 17:57:16 lampret`
51			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from ic.v and ic.v. Fixed CR+LF.`
52			`//`
53			`// Revision 1.8 2001/10/19 23:28:46 lampret`
54			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
55			`//`
56			`// Revision 1.7 2001/10/14 13:12:09 lampret`
57			`// MP3 version.`
58			`//`
59			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
60			`// no message`
61			`//`
62			`// Revision 1.2 2001/08/09 13:39:33 lampret`
63			`// Major clean-up.`
64			`//`
65			`// Revision 1.1 2001/07/20 00:46:03 lampret`
66			`// Development version of RTL. Libraries are missing.`
67			`//`
68			`//`
69
70			`// synopsys translate_off`
71			`include "timescale.v"
72			`// synopsys translate_on`
73			`include "or1200_defines.v"
74
75			`define OR1200_ICFSM_IDLE 3'd0
76			`define OR1200_ICFSM_DOLOAD 3'd1
77			`define OR1200_ICFSM_LREFILL3 3'd2
78
79			`//`
80			`// Data cache FSM for cache line of 16 bytes (4x singleword)`
81			`//`
82
83			`module or1200_ic_fsm(`
84			`// Clock and reset`
85			`clk, rst,`
86
87			`// Internal i/f to top level IC`
88			`ic_en, icimmu_cyc_i, icimmu_stb_i, icimmu_ci_i, icpu_sel_i,`
89			`tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,`
90			`icram_we, biu_read, first_hit_ack, first_miss_ack, first_miss_err,`
91			`burst`
92			`);`
93
94			`//`
95			`// I/O`
96			`//`
97			`input clk;`
98			`input rst;`
99			`input ic_en;`
100			`input icimmu_cyc_i;`
101			`input icimmu_stb_i;`
102			`input icimmu_ci_i;`
103			`input [3:0] icpu_sel_i;`
104			`input tagcomp_miss;`
105			`input biudata_valid;`
106			`input biudata_error;`
107			`input [31:0] start_addr;`
108			`output [31:0] saved_addr;`
109			`output [3:0] icram_we;`
110			`output biu_read;`
111			`output first_hit_ack;`
112			`output first_miss_ack;`
113			`output first_miss_err;`
114			`output burst;`
115
116			`//`
117			`// Internal wires and regs`
118			`//`
119			`reg [31:0] saved_addr;`
120			`reg [2:0] state;`
121			`reg [2:0] cnt;`
122			`reg hitmiss_eval;`
123			`reg load;`
124
125			`//`
126			`// Generate of ICRAM write enables`
127			`//`
128			`assign icram_we = {4{load & biudata_valid}};`
129
130			`//`
131			`// BIU read and write`
132			`//`
133			`assign biu_read = (hitmiss_eval & tagcomp_miss) \| (!hitmiss_eval & load);`
134
135			`//`
136			`// Assert for cache hit first word ready`
137			`// Assert for cache miss first word stored/loaded OK`
138			`// Assert for cache miss first word stored/loaded with an error`
139			`//`
140			assign first_hit_ack = (state == `OR1200_ICFSM_DOLOAD) & hitmiss_eval & !tagcomp_miss & !icimmu_ci_i;
141			assign first_miss_ack = (state == `OR1200_ICFSM_DOLOAD) & (tagcomp_miss \| icimmu_ci_i) & biudata_valid;
142			assign first_miss_err = (state == `OR1200_ICFSM_DOLOAD) & (tagcomp_miss \| icimmu_ci_i) & biudata_error;
143
144			`//`
145			`// Assert burst when doing reload of complete cache line`
146			`//`
147			assign burst = (state == `OR1200_ICFSM_DOLOAD) & tagcomp_miss
148			\| (state == `OR1200_ICFSM_LREFILL3);
149
150			`//`
151			`// Main IC FSM`
152			`//`
153			`always @(posedge clk or posedge rst) begin`
154			`if (rst) begin`
155			state <= #1 `OR1200_ICFSM_IDLE;
156			`saved_addr <= #1 32'b0;`
157			`hitmiss_eval <= #1 1'b0;`
158			`load <= #1 1'b0;`
159			`cnt <= #1 3'b000;`
160			`end`
161			`else`
162			`case (state) // synopsys parallel_case`
163			`OR1200_ICFSM_IDLE :
164			`if (ic_en & icimmu_cyc_i & icimmu_stb_i) begin // load`
165			state <= #1 `OR1200_ICFSM_DOLOAD;
166			`saved_addr <= #1 start_addr;`
167			`hitmiss_eval <= #1 1'b1;`
168			`load <= #1 1'b1;`
169			`end`
170			`else begin // idle`
171			state <= #1 `OR1200_ICFSM_IDLE;
172			`hitmiss_eval <= #1 1'b0;`
173			`load <= #1 1'b0;`
174			`end`
175			`OR1200_ICFSM_DOLOAD:
176			`if (hitmiss_eval & !(icimmu_cyc_i & icimmu_stb_i)) begin // load aborted (usually caused by IMMU)`
177			state <= #1 `OR1200_ICFSM_IDLE;
178			`hitmiss_eval <= #1 1'b0;`
179			`load <= #1 1'b0;`
180			`end`
181			`else if (icimmu_ci_i & biudata_valid) begin // load from cache inhibit page`
182			state <= #1 `OR1200_ICFSM_IDLE;
183			`hitmiss_eval <= #1 1'b0;`
184			`load <= #1 1'b0;`
185			`end`
186			`else if (tagcomp_miss & biudata_valid) begin // load missed, finish current external load and refill`
187			state <= #1 `OR1200_ICFSM_LREFILL3;
188			`saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;`
189			`hitmiss_eval <= #1 1'b0;`
190			cnt <= #1 `OR1200_ICLS-2;
191			`end`
192			`else if (!tagcomp_miss & !icimmu_ci_i) begin // load hit and not cache inhibit, finish immediately`
193			state <= #1 `OR1200_ICFSM_DOLOAD;
194			`saved_addr <= #1 start_addr;`
195			`hitmiss_eval <= #1 1'b1;`
196			`load <= #1 1'b1;`
197			`end`
198	562	lampret	`else if (!icimmu_cyc_i \| !icimmu_stb_i) begin // load aborted (usually caused by exception)`
199			state <= #1 `OR1200_ICFSM_IDLE;
200			`hitmiss_eval <= #1 1'b0;`
201			`load <= #1 1'b0;`
202			`end`
203	504	lampret	`else // load in-progress`
204			`hitmiss_eval <= #1 1'b0;`
205			`OR1200_ICFSM_LREFILL3 : begin
206			`if (biudata_valid && (\|cnt)) begin // refill ack, more loads to come`
207			`cnt <= #1 cnt - 'd1;`
208			`saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;`
209			`end`
210			`else if (biudata_valid) begin // last load of line refill`
211			state <= #1 `OR1200_ICFSM_IDLE;
212			`saved_addr <= #1 start_addr;`
213			`hitmiss_eval <= #1 1'b0;`
214			`load <= #1 1'b0;`
215			`end`
216			`end`
217			`default:`
218			state <= #1 `OR1200_ICFSM_IDLE;
219			`endcase`
220			`end`
221
222			`endmodule`