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[/] [or1k/] [tags/] [rel_5/] [or1200/] [rtl/] [verilog/] [or1200_sprs.v] - Blame information for rev 504

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's interface to SPRs                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Decoding of SPR addresses and access to SPRs                ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12  2001/11/23 21:42:31  simons
// Program counter divided to PPC and NPC.
//
// Revision 1.11  2001/11/23 08:38:51  lampret
// Changed DSR/DRR behavior and exception detection.
//
// Revision 1.10  2001/11/12 01:45:41  lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/14 13:12:10  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.3  2001/08/13 03:36:20  lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:21  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_sprs(
                // Clk & Rst
                clk, rst,
 
                // Internal CPU interface
                flagforw, flag_we, flag, addrbase, addrofs, dat_i, alu_op, branch_op,
                epcr, eear, esr, except_start, except_started,
                to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr,
                spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
 
                // From/to other RISC units
                spr_dat_pic, spr_dat_tt, spr_dat_pm,
                spr_dat_dmmu, spr_dat_immu, spr_dat_du,
                spr_addr, spr_dataout, spr_cs, spr_we,
 
                du_addr, du_dat_du, du_read,
                du_write
 
);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O Ports
//
 
//
// Internal CPU interface
//
input                           clk;            // Clock
input                           rst;            // Reset
output                          flag;           // SR[F]
input                           flagforw;       // From ALU
input                           flag_we;        // From ALU
input   [width-1:0]              addrbase;       // SPR base address
input   [15:0]                   addrofs;        // SPR offset
input   [width-1:0]              dat_i;          // SPR write data
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;         // ALU operation
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;      // Branch operation
input   [width-1:0]              epcr;           // EPCR0
input   [width-1:0]              eear;           // EEAR0
input   [`OR1200_SR_WIDTH-1:0]   esr;            // ESR0
input                           except_start;   // Start of exception
input                           except_started; // Exception was started
output  [width-1:0]              to_wbmux;       // For l.mfspr
output                          epcr_we;        // EPCR0 write enable
output                          eear_we;        // EEAR0 write enable
output                          esr_we;         // ESR0 write enable
output                          pc_we;          // PC write enable
output  [`OR1200_SR_WIDTH-1:0]           sr;             // SR
input   [31:0]                   spr_dat_cfgr;   // Data from CFGR
input   [31:0]                   spr_dat_rf;     // Data from RF
input   [31:0]                   spr_dat_npc;    // Data from NPC
input   [31:0]                   spr_dat_ppc;    // Data from PPC   
input   [31:0]                   spr_dat_mac;    // Data from MAC
 
//
// To/from other RISC units
//
input   [31:0]                   spr_dat_pic;    // Data from PIC
input   [31:0]                   spr_dat_tt;     // Data from TT
input   [31:0]                   spr_dat_pm;     // Data from PM
input   [31:0]                   spr_dat_dmmu;   // Data from DMMU
input   [31:0]                   spr_dat_immu;   // Data from IMMU
input   [31:0]                   spr_dat_du;     // Data from DU
output  [31:0]                   spr_addr;       // SPR Address
output  [31:0]                   spr_dataout;    // Data to unit
output  [31:0]                   spr_cs;         // Unit select
output                          spr_we;         // SPR write enable
 
//
// To/from Debug Unit
//
input   [width-1:0]              du_addr;        // Address
input   [width-1:0]              du_dat_du;      // Data from DU to SPRS
input                           du_read;        // Read qualifier
input                           du_write;       // Write qualifier
 
//
// Internal regs & wires
//
reg     [`OR1200_SR_WIDTH-1:0]           sr;             // SR
reg                             write_spr;      // Write SPR
reg                             read_spr;       // Read SPR
reg     [width-1:0]              to_wbmux;       // For l.mfspr
wire                            sr_we;          // Write enable SR
wire                            cfgr_sel;       // Select for cfg regs
wire                            rf_sel;         // Select for RF
wire                            npc_sel;        // Select for NPC
wire                            ppc_sel;        // Select for PPC
wire                            sr_sel;         // Select for SR        
wire                            epcr_sel;       // Select for EPCR0
wire                            eear_sel;       // Select for EEAR0
wire                            esr_sel;        // Select for ESR0
wire    [31:0]                   sys_data;       // Read data from system SPRs
wire    [`OR1200_SR_WIDTH-1:0]           to_sr;          // Data to SR
wire                            du_access;      // Debug unit access
wire    [`OR1200_ALUOP_WIDTH-1:0]        sprs_op;        // ALU operation
reg     [31:0]                   unqualified_cs; // Unqualified chip selects
 
//
// Decide if it is debug unit access
//
assign du_access = du_read | du_write;
 
//
// Generate sprs opcode
//
assign sprs_op = du_write ? `OR1200_ALUOP_MTSR : du_read ? `OR1200_ALUOP_MFSR : alu_op;
 
//
// Generate SPR address from base address and offset
// OR from debug unit address
//
assign spr_addr = du_access ? du_addr : addrbase + {16'h0000, addrofs};
 
//
// SPR is written with dat_i from l.mtspr
// OR by debug unit
//
assign spr_dataout = du_write ? du_dat_du : du_read ? to_wbmux : dat_i;
 
//
// Write into SPRs when l.mtspr
//
assign spr_we = du_write | write_spr;
 
//
// Qualify chip selects
//
assign spr_cs = unqualified_cs & {32{read_spr | write_spr}};
 
//
// Decoding of groups
//
always @(spr_addr)
        case (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
                `OR1200_SPR_GROUP_WIDTH'd00: unqualified_cs = 32'b00000000_00000000_00000000_00000001;
                `OR1200_SPR_GROUP_WIDTH'd01: unqualified_cs = 32'b00000000_00000000_00000000_00000010;
                `OR1200_SPR_GROUP_WIDTH'd02: unqualified_cs = 32'b00000000_00000000_00000000_00000100;
                `OR1200_SPR_GROUP_WIDTH'd03: unqualified_cs = 32'b00000000_00000000_00000000_00001000;
                `OR1200_SPR_GROUP_WIDTH'd04: unqualified_cs = 32'b00000000_00000000_00000000_00010000;
                `OR1200_SPR_GROUP_WIDTH'd05: unqualified_cs = 32'b00000000_00000000_00000000_00100000;
                `OR1200_SPR_GROUP_WIDTH'd06: unqualified_cs = 32'b00000000_00000000_00000000_01000000;
                `OR1200_SPR_GROUP_WIDTH'd07: unqualified_cs = 32'b00000000_00000000_00000000_10000000;
                `OR1200_SPR_GROUP_WIDTH'd08: unqualified_cs = 32'b00000000_00000000_00000001_00000000;
                `OR1200_SPR_GROUP_WIDTH'd09: unqualified_cs = 32'b00000000_00000000_00000010_00000000;
                `OR1200_SPR_GROUP_WIDTH'd10: unqualified_cs = 32'b00000000_00000000_00000100_00000000;
                `OR1200_SPR_GROUP_WIDTH'd11: unqualified_cs = 32'b00000000_00000000_00001000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd12: unqualified_cs = 32'b00000000_00000000_00010000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd13: unqualified_cs = 32'b00000000_00000000_00100000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd14: unqualified_cs = 32'b00000000_00000000_01000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd15: unqualified_cs = 32'b00000000_00000000_10000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd16: unqualified_cs = 32'b00000000_00000001_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd17: unqualified_cs = 32'b00000000_00000010_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd18: unqualified_cs = 32'b00000000_00000100_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd19: unqualified_cs = 32'b00000000_00001000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd20: unqualified_cs = 32'b00000000_00010000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd21: unqualified_cs = 32'b00000000_00100000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd22: unqualified_cs = 32'b00000000_01000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd23: unqualified_cs = 32'b00000000_10000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd24: unqualified_cs = 32'b00000001_00000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd25: unqualified_cs = 32'b00000010_00000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd26: unqualified_cs = 32'b00000100_00000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd27: unqualified_cs = 32'b00001000_00000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd28: unqualified_cs = 32'b00010000_00000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd29: unqualified_cs = 32'b00100000_00000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd30: unqualified_cs = 32'b01000000_00000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd31: unqualified_cs = 32'b10000000_00000000_00000000_00000000;
        endcase
 
//
// SPRs System Group
//
 
//
// What to write into SR
//
assign to_sr = (branch_op == `OR1200_BRANCHOP_RFE) ? esr : spr_dataout[`OR1200_SR_WIDTH-1:0];
 
//
// Selects for system SPRs
//
assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR));
assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:5] == `OR1200_SPR_RF));
assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_NPC));
assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_PPC));
assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_SR));
assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EPCR));
assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EEAR));
assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
 
//
// Write enables for system SPRs
//
assign sr_we = (write_spr && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE);
assign pc_we = (write_spr && (npc_sel | ppc_sel));
assign epcr_we = (write_spr && epcr_sel);
assign eear_we = (write_spr && eear_sel);
assign esr_we = (write_spr && esr_sel);
 
//
// Output from system SPRs
//
assign sys_data = (spr_dat_cfgr & {32{read_spr & cfgr_sel}}) |
                  (spr_dat_rf & {32{read_spr & rf_sel}}) |
                  (spr_dat_npc & {32{read_spr & npc_sel}}) |
                  (spr_dat_ppc & {32{read_spr & ppc_sel}}) |
                  ({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{read_spr & sr_sel}}) |
                  (epcr & {32{read_spr & epcr_sel}}) |
                  (eear & {32{read_spr & eear_sel}}) |
                  ({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{read_spr & esr_sel}});
 
//
// Flag alias
//
assign flag = sr[`OR1200_SR_F];
 
//
// Supervision register
//
always @(posedge clk or posedge rst)
        if (rst)
                sr <= #1 `OR1200_SR_WIDTH'b011;
        else if (except_started) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                $display(" INFO: exception started. SR[SUPV] set and SR[EIR] cleared.");
// synopsys translate_on
`endif
                sr[`OR1200_SR_SUPV] <= #1 1'b1;
                sr[`OR1200_SR_EIR] <= #1 1'b0;
                sr[`OR1200_SR_DME] <= #1 1'b0;
                sr[`OR1200_SR_IME] <= #1 1'b0;
        end
        else if (sr_we) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                $display(" INFO: writing into SR register: %h", spr_dataout);
// synopsys translate_on
`endif
                sr <= #1 {to_sr[`OR1200_SR_WIDTH-1:2], 1'b1, to_sr[0]};
        end
        else if (flag_we) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                $display(" INFO: setting SR[F] bit: %b", flagforw);
// synopsys translate_on
`endif
                sr[`OR1200_SR_F] <= #1 flagforw;
        end
 
//
// MTSPR/MFSPR interface
//
always @(sprs_op or spr_addr or spr_dataout or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
        spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
        case (sprs_op)  // synopsys full_case parallel_case
                `OR1200_ALUOP_MTSR : begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: SPRS: mtspr (%h) <- %h", $time, spr_addr, spr_dataout);
// synopsys translate_on
`endif
                        write_spr = 1'b1;
                        read_spr = 1'b0;
                        to_wbmux = 32'b0;
                end
                `OR1200_ALUOP_MFSR : begin
                        casex (spr_addr[`OR1200_SPR_GROUP_BITS])
                                `OR1200_SPR_GROUP_TT:
                                        to_wbmux = spr_dat_tt;
                                `OR1200_SPR_GROUP_PIC:
                                        to_wbmux = spr_dat_pic;
                                `OR1200_SPR_GROUP_PM:
                                        to_wbmux = spr_dat_pm;
                                `OR1200_SPR_GROUP_DMMU:
                                        to_wbmux = spr_dat_dmmu;
                                `OR1200_SPR_GROUP_IMMU:
                                        to_wbmux = spr_dat_immu;
                                `OR1200_SPR_GROUP_MAC:
                                        to_wbmux = spr_dat_mac;
                                `OR1200_SPR_GROUP_DU:
                                        to_wbmux = spr_dat_du;
                                `OR1200_SPR_GROUP_SYS:
                                        to_wbmux = sys_data;
                                default:
                                        to_wbmux = 32'b0;
                        endcase
                        write_spr = 1'b0;
                        read_spr = 1'b1;
                end
                default : begin
                        write_spr = 1'b0;
                        read_spr = 1'b0;
                        to_wbmux = 32'b0;
                end
        endcase
end
 
endmodule

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[/] [or1k/] [tags/] [rel_5/] [or1200/] [rtl/] [verilog/] [or1200_sprs.v] - Blame information for rev 504

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's interface to SPRs ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Decoding of SPR addresses and access to SPRs ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.12 2001/11/23 21:42:31 simons`
48			`// Program counter divided to PPC and NPC.`
49			`//`
50			`// Revision 1.11 2001/11/23 08:38:51 lampret`
51			`// Changed DSR/DRR behavior and exception detection.`
52			`//`
53			`// Revision 1.10 2001/11/12 01:45:41 lampret`
54			`// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.`
55			`//`
56			`// Revision 1.9 2001/10/21 17:57:16 lampret`
57			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
58			`//`
59			`// Revision 1.8 2001/10/14 13:12:10 lampret`
60			`// MP3 version.`
61			`//`
62			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
63			`// no message`
64			`//`
65			`// Revision 1.3 2001/08/13 03:36:20 lampret`
66			`// Added cfg regs. Moved all defines into one defines.v file. More cleanup.`
67			`//`
68			`// Revision 1.2 2001/08/09 13:39:33 lampret`
69			`// Major clean-up.`
70			`//`
71			`// Revision 1.1 2001/07/20 00:46:21 lampret`
72			`// Development version of RTL. Libraries are missing.`
73			`//`
74			`//`
75
76			`// synopsys translate_off`
77			`include "timescale.v"
78			`// synopsys translate_on`
79			`include "or1200_defines.v"
80
81			`module or1200_sprs(`
82			`// Clk & Rst`
83			`clk, rst,`
84
85			`// Internal CPU interface`
86			`flagforw, flag_we, flag, addrbase, addrofs, dat_i, alu_op, branch_op,`
87			`epcr, eear, esr, except_start, except_started,`
88			`to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr,`
89			`spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,`
90
91			`// From/to other RISC units`
92			`spr_dat_pic, spr_dat_tt, spr_dat_pm,`
93			`spr_dat_dmmu, spr_dat_immu, spr_dat_du,`
94			`spr_addr, spr_dataout, spr_cs, spr_we,`
95
96			`du_addr, du_dat_du, du_read,`
97			`du_write`
98
99			`);`
100
101			parameter width = `OR1200_OPERAND_WIDTH;
102
103			`//`
104			`// I/O Ports`
105			`//`
106
107			`//`
108			`// Internal CPU interface`
109			`//`
110			`input clk; // Clock`
111			`input rst; // Reset`
112			`output flag; // SR[F]`
113			`input flagforw; // From ALU`
114			`input flag_we; // From ALU`
115			`input [width-1:0] addrbase; // SPR base address`
116			`input [15:0] addrofs; // SPR offset`
117			`input [width-1:0] dat_i; // SPR write data`
118			input [`OR1200_ALUOP_WIDTH-1:0] alu_op; // ALU operation
119			input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch operation
120			`input [width-1:0] epcr; // EPCR0`
121			`input [width-1:0] eear; // EEAR0`
122			input [`OR1200_SR_WIDTH-1:0] esr; // ESR0
123			`input except_start; // Start of exception`
124			`input except_started; // Exception was started`
125			`output [width-1:0] to_wbmux; // For l.mfspr`
126			`output epcr_we; // EPCR0 write enable`
127			`output eear_we; // EEAR0 write enable`
128			`output esr_we; // ESR0 write enable`
129			`output pc_we; // PC write enable`
130			output [`OR1200_SR_WIDTH-1:0] sr; // SR
131			`input [31:0] spr_dat_cfgr; // Data from CFGR`
132			`input [31:0] spr_dat_rf; // Data from RF`
133			`input [31:0] spr_dat_npc; // Data from NPC`
134			`input [31:0] spr_dat_ppc; // Data from PPC`
135			`input [31:0] spr_dat_mac; // Data from MAC`
136
137			`//`
138			`// To/from other RISC units`
139			`//`
140			`input [31:0] spr_dat_pic; // Data from PIC`
141			`input [31:0] spr_dat_tt; // Data from TT`
142			`input [31:0] spr_dat_pm; // Data from PM`
143			`input [31:0] spr_dat_dmmu; // Data from DMMU`
144			`input [31:0] spr_dat_immu; // Data from IMMU`
145			`input [31:0] spr_dat_du; // Data from DU`
146			`output [31:0] spr_addr; // SPR Address`
147			`output [31:0] spr_dataout; // Data to unit`
148			`output [31:0] spr_cs; // Unit select`
149			`output spr_we; // SPR write enable`
150
151			`//`
152			`// To/from Debug Unit`
153			`//`
154			`input [width-1:0] du_addr; // Address`
155			`input [width-1:0] du_dat_du; // Data from DU to SPRS`
156			`input du_read; // Read qualifier`
157			`input du_write; // Write qualifier`
158
159			`//`
160			`// Internal regs & wires`
161			`//`
162			reg [`OR1200_SR_WIDTH-1:0] sr; // SR
163			`reg write_spr; // Write SPR`
164			`reg read_spr; // Read SPR`
165			`reg [width-1:0] to_wbmux; // For l.mfspr`
166			`wire sr_we; // Write enable SR`
167			`wire cfgr_sel; // Select for cfg regs`
168			`wire rf_sel; // Select for RF`
169			`wire npc_sel; // Select for NPC`
170			`wire ppc_sel; // Select for PPC`
171			`wire sr_sel; // Select for SR`
172			`wire epcr_sel; // Select for EPCR0`
173			`wire eear_sel; // Select for EEAR0`
174			`wire esr_sel; // Select for ESR0`
175			`wire [31:0] sys_data; // Read data from system SPRs`
176			wire [`OR1200_SR_WIDTH-1:0] to_sr; // Data to SR
177			`wire du_access; // Debug unit access`
178			wire [`OR1200_ALUOP_WIDTH-1:0] sprs_op; // ALU operation
179			`reg [31:0] unqualified_cs; // Unqualified chip selects`
180
181			`//`
182			`// Decide if it is debug unit access`
183			`//`
184			`assign du_access = du_read \| du_write;`
185
186			`//`
187			`// Generate sprs opcode`
188			`//`
189			assign sprs_op = du_write ? `OR1200_ALUOP_MTSR : du_read ? `OR1200_ALUOP_MFSR : alu_op;
190
191			`//`
192			`// Generate SPR address from base address and offset`
193			`// OR from debug unit address`
194			`//`
195			`assign spr_addr = du_access ? du_addr : addrbase + {16'h0000, addrofs};`
196
197			`//`
198			`// SPR is written with dat_i from l.mtspr`
199			`// OR by debug unit`
200			`//`
201			`assign spr_dataout = du_write ? du_dat_du : du_read ? to_wbmux : dat_i;`
202
203			`//`
204			`// Write into SPRs when l.mtspr`
205			`//`
206			`assign spr_we = du_write \| write_spr;`
207
208			`//`
209			`// Qualify chip selects`
210			`//`
211			`assign spr_cs = unqualified_cs & {32{read_spr \| write_spr}};`
212
213			`//`
214			`// Decoding of groups`
215			`//`
216			`always @(spr_addr)`
217			case (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
218			`OR1200_SPR_GROUP_WIDTH'd00: unqualified_cs = 32'b00000000_00000000_00000000_00000001;
219			`OR1200_SPR_GROUP_WIDTH'd01: unqualified_cs = 32'b00000000_00000000_00000000_00000010;
220			`OR1200_SPR_GROUP_WIDTH'd02: unqualified_cs = 32'b00000000_00000000_00000000_00000100;
221			`OR1200_SPR_GROUP_WIDTH'd03: unqualified_cs = 32'b00000000_00000000_00000000_00001000;
222			`OR1200_SPR_GROUP_WIDTH'd04: unqualified_cs = 32'b00000000_00000000_00000000_00010000;
223			`OR1200_SPR_GROUP_WIDTH'd05: unqualified_cs = 32'b00000000_00000000_00000000_00100000;
224			`OR1200_SPR_GROUP_WIDTH'd06: unqualified_cs = 32'b00000000_00000000_00000000_01000000;
225			`OR1200_SPR_GROUP_WIDTH'd07: unqualified_cs = 32'b00000000_00000000_00000000_10000000;
226			`OR1200_SPR_GROUP_WIDTH'd08: unqualified_cs = 32'b00000000_00000000_00000001_00000000;
227			`OR1200_SPR_GROUP_WIDTH'd09: unqualified_cs = 32'b00000000_00000000_00000010_00000000;
228			`OR1200_SPR_GROUP_WIDTH'd10: unqualified_cs = 32'b00000000_00000000_00000100_00000000;
229			`OR1200_SPR_GROUP_WIDTH'd11: unqualified_cs = 32'b00000000_00000000_00001000_00000000;
230			`OR1200_SPR_GROUP_WIDTH'd12: unqualified_cs = 32'b00000000_00000000_00010000_00000000;
231			`OR1200_SPR_GROUP_WIDTH'd13: unqualified_cs = 32'b00000000_00000000_00100000_00000000;
232			`OR1200_SPR_GROUP_WIDTH'd14: unqualified_cs = 32'b00000000_00000000_01000000_00000000;
233			`OR1200_SPR_GROUP_WIDTH'd15: unqualified_cs = 32'b00000000_00000000_10000000_00000000;
234			`OR1200_SPR_GROUP_WIDTH'd16: unqualified_cs = 32'b00000000_00000001_00000000_00000000;
235			`OR1200_SPR_GROUP_WIDTH'd17: unqualified_cs = 32'b00000000_00000010_00000000_00000000;
236			`OR1200_SPR_GROUP_WIDTH'd18: unqualified_cs = 32'b00000000_00000100_00000000_00000000;
237			`OR1200_SPR_GROUP_WIDTH'd19: unqualified_cs = 32'b00000000_00001000_00000000_00000000;
238			`OR1200_SPR_GROUP_WIDTH'd20: unqualified_cs = 32'b00000000_00010000_00000000_00000000;
239			`OR1200_SPR_GROUP_WIDTH'd21: unqualified_cs = 32'b00000000_00100000_00000000_00000000;
240			`OR1200_SPR_GROUP_WIDTH'd22: unqualified_cs = 32'b00000000_01000000_00000000_00000000;
241			`OR1200_SPR_GROUP_WIDTH'd23: unqualified_cs = 32'b00000000_10000000_00000000_00000000;
242			`OR1200_SPR_GROUP_WIDTH'd24: unqualified_cs = 32'b00000001_00000000_00000000_00000000;
243			`OR1200_SPR_GROUP_WIDTH'd25: unqualified_cs = 32'b00000010_00000000_00000000_00000000;
244			`OR1200_SPR_GROUP_WIDTH'd26: unqualified_cs = 32'b00000100_00000000_00000000_00000000;
245			`OR1200_SPR_GROUP_WIDTH'd27: unqualified_cs = 32'b00001000_00000000_00000000_00000000;
246			`OR1200_SPR_GROUP_WIDTH'd28: unqualified_cs = 32'b00010000_00000000_00000000_00000000;
247			`OR1200_SPR_GROUP_WIDTH'd29: unqualified_cs = 32'b00100000_00000000_00000000_00000000;
248			`OR1200_SPR_GROUP_WIDTH'd30: unqualified_cs = 32'b01000000_00000000_00000000_00000000;
249			`OR1200_SPR_GROUP_WIDTH'd31: unqualified_cs = 32'b10000000_00000000_00000000_00000000;
250			`endcase`
251
252			`//`
253			`// SPRs System Group`
254			`//`
255
256			`//`
257			`// What to write into SR`
258			`//`
259			assign to_sr = (branch_op == `OR1200_BRANCHOP_RFE) ? esr : spr_dataout[`OR1200_SR_WIDTH-1:0];
260
261			`//`
262			`// Selects for system SPRs`
263			`//`
264			assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR));
265			assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:5] == `OR1200_SPR_RF));
266			assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_NPC));
267			assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_PPC));
268			assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_SR));
269			assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EPCR));
270			assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EEAR));
271			assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
272
273			`//`
274			`// Write enables for system SPRs`
275			`//`
276			assign sr_we = (write_spr && sr_sel) \| (branch_op == `OR1200_BRANCHOP_RFE);
277			`assign pc_we = (write_spr && (npc_sel \| ppc_sel));`
278			`assign epcr_we = (write_spr && epcr_sel);`
279			`assign eear_we = (write_spr && eear_sel);`
280			`assign esr_we = (write_spr && esr_sel);`
281
282			`//`
283			`// Output from system SPRs`
284			`//`
285			`assign sys_data = (spr_dat_cfgr & {32{read_spr & cfgr_sel}}) \|`
286			`(spr_dat_rf & {32{read_spr & rf_sel}}) \|`
287			`(spr_dat_npc & {32{read_spr & npc_sel}}) \|`
288			`(spr_dat_ppc & {32{read_spr & ppc_sel}}) \|`
289			({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{read_spr & sr_sel}}) \|
290			`(epcr & {32{read_spr & epcr_sel}}) \|`
291			`(eear & {32{read_spr & eear_sel}}) \|`
292			({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{read_spr & esr_sel}});
293
294			`//`
295			`// Flag alias`
296			`//`
297			assign flag = sr[`OR1200_SR_F];
298
299			`//`
300			`// Supervision register`
301			`//`
302			`always @(posedge clk or posedge rst)`
303			`if (rst)`
304			sr <= #1 `OR1200_SR_WIDTH'b011;
305			`else if (except_started) begin`
306			`ifdef OR1200_VERBOSE
307			`// synopsys translate_off`
308			`$display(" INFO: exception started. SR[SUPV] set and SR[EIR] cleared.");`
309			`// synopsys translate_on`
310			`endif
311			sr[`OR1200_SR_SUPV] <= #1 1'b1;
312			sr[`OR1200_SR_EIR] <= #1 1'b0;
313			sr[`OR1200_SR_DME] <= #1 1'b0;
314			sr[`OR1200_SR_IME] <= #1 1'b0;
315			`end`
316			`else if (sr_we) begin`
317			`ifdef OR1200_VERBOSE
318			`// synopsys translate_off`
319			`$display(" INFO: writing into SR register: %h", spr_dataout);`
320			`// synopsys translate_on`
321			`endif
322			sr <= #1 {to_sr[`OR1200_SR_WIDTH-1:2], 1'b1, to_sr[0]};
323			`end`
324			`else if (flag_we) begin`
325			`ifdef OR1200_VERBOSE
326			`// synopsys translate_off`
327			`$display(" INFO: setting SR[F] bit: %b", flagforw);`
328			`// synopsys translate_on`
329			`endif
330			sr[`OR1200_SR_F] <= #1 flagforw;
331			`end`
332
333			`//`
334			`// MTSPR/MFSPR interface`
335			`//`
336			`always @(sprs_op or spr_addr or spr_dataout or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or`
337			`spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin`
338			`case (sprs_op) // synopsys full_case parallel_case`
339			`OR1200_ALUOP_MTSR : begin
340			`ifdef OR1200_VERBOSE
341			`// synopsys translate_off`
342			`$display("%t: SPRS: mtspr (%h) <- %h", $time, spr_addr, spr_dataout);`
343			`// synopsys translate_on`
344			`endif
345			`write_spr = 1'b1;`
346			`read_spr = 1'b0;`
347			`to_wbmux = 32'b0;`
348			`end`
349			`OR1200_ALUOP_MFSR : begin
350			casex (spr_addr[`OR1200_SPR_GROUP_BITS])
351			`OR1200_SPR_GROUP_TT:
352			`to_wbmux = spr_dat_tt;`
353			`OR1200_SPR_GROUP_PIC:
354			`to_wbmux = spr_dat_pic;`
355			`OR1200_SPR_GROUP_PM:
356			`to_wbmux = spr_dat_pm;`
357			`OR1200_SPR_GROUP_DMMU:
358			`to_wbmux = spr_dat_dmmu;`
359			`OR1200_SPR_GROUP_IMMU:
360			`to_wbmux = spr_dat_immu;`
361			`OR1200_SPR_GROUP_MAC:
362			`to_wbmux = spr_dat_mac;`
363			`OR1200_SPR_GROUP_DU:
364			`to_wbmux = spr_dat_du;`
365			`OR1200_SPR_GROUP_SYS:
366			`to_wbmux = sys_data;`
367			`default:`
368			`to_wbmux = 32'b0;`
369			`endcase`
370			`write_spr = 1'b0;`
371			`read_spr = 1'b1;`
372			`end`
373			`default : begin`
374			`write_spr = 1'b0;`
375			`read_spr = 1'b0;`
376			`to_wbmux = 32'b0;`
377			`end`
378			`endcase`
379			`end`
380
381			`endmodule`