URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_6/] [or1200/] [rtl/] [verilog/] [or1200_alu.v] - Blame information for rev 1033

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's ALU                                                ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  ALU                                                         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2002/09/07 05:42:02  lampret
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
//
// Revision 1.7  2002/09/03 22:28:21  lampret
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
//
// Revision 1.6  2002/03/29 16:40:10  lampret
// Added a directive to ignore signed division variables that are only used in simulation.
//
// Revision 1.5  2002/03/29 16:33:59  lampret
// Added again just recently removed full_case directive
//
// Revision 1.4  2002/03/29 15:16:53  lampret
// Some of the warnings fixed.
//
// Revision 1.3  2002/01/28 01:15:59  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/12 01:45:40  lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:45  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_alu(
        a, b, mult_mac_result, macrc_op,
        alu_op, shrot_op, comp_op,
        result, flagforw, flag_we,
        cyforw, cy_we, carry
);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
input   [width-1:0]              a;
input   [width-1:0]              b;
input   [width-1:0]              mult_mac_result;
input                           macrc_op;
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
input   [`OR1200_SHROTOP_WIDTH-1:0]      shrot_op;
input   [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
output  [width-1:0]              result;
output                          flagforw;
output                          flag_we;
output                          cyforw;
output                          cy_we;
input                           carry;
 
//
// Internal wires and regs
//
reg     [width-1:0]              result;
reg     [width-1:0]              shifted_rotated;
reg                             flagforw;
reg                             flagcomp;
reg                             flag_we;
reg                             cy_we;
// synopsys translate_off
`ifdef OR1200_SIM_ALU_DIV
integer                         d1;
integer                         d2;
`endif
// synopsys translate_on
wire    [width-1:0]              comp_a;
wire    [width-1:0]              comp_b;
`ifdef OR1200_IMPL_ALU_COMP1
wire                            a_eq_b;
wire                            a_lt_b;
`endif
wire    [width-1:0]              result_sum;
`ifdef OR1200_IMPL_ADDC
wire    [width-1:0]              result_csum;
wire                            cy_csum;
`endif
wire    [width-1:0]              result_and;
wire                            cy_sum;
reg                             cyforw;
 
//
// Combinatorial logic
//
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
`ifdef OR1200_IMPL_ALU_COMP1
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
`endif
assign {cy_sum, result_sum} = a + b;
`ifdef OR1200_IMPL_ADDC
assign {cy_csum, result_csum} = a + b + carry;
`endif
assign result_and = a & b;
 
//
// Simulation check for bad ALU behavior
//
`ifdef OR1200_WARNINGS
// synopsys translate_off
always @(result) begin
        if (result === 32'bx)
                $display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
end
// synopsys translate_on
`endif
 
//
// Central part of the ALU
//
always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin
`ifdef OR1200_CASE_DEFAULT
        casex (alu_op)          // synopsys parallel_case
`else
        casex (alu_op)          // synopsys full_case parallel_case
`endif
                `OR1200_ALUOP_SHROT : begin
                                result = shifted_rotated;
                end
                `OR1200_ALUOP_ADD : begin
                                result = result_sum;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                                result = result_csum;
                end
`endif
                `OR1200_ALUOP_SUB : begin
                                result = a - b;
                end
                `OR1200_ALUOP_XOR : begin
                                result = a ^ b;
                end
                `OR1200_ALUOP_OR  : begin
                                result = a | b;
                end
                `OR1200_ALUOP_IMM : begin
                                result = b;
                end
                `OR1200_ALUOP_MOVHI : begin
                                if (macrc_op) begin
                                        result = mult_mac_result;
                                end
                                else begin
                                        result = b << 16;
                                end
                end
                `OR1200_ALUOP_MUL : begin
                                result = mult_mac_result;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: MUL operation: %h * %h = %h", $time, a, b, mult_mac_result);
// synopsys translate_on
`endif
                end
// synopsys translate_off
`ifdef OR1200_SIM_ALU_DIV
                `OR1200_ALUOP_DIV : begin
                                d1 = a;
                                d2 = b;
                                $display("DIV operation: %d / %d = %d", d1, d2, d1/d2);
                                if (d2)
                                        result = d1 / d2;
                                else
                                        result = 32'h00000000;
                end
`endif
`ifdef OR1200_SIM_ALU_DIVU
                `OR1200_ALUOP_DIVU : begin
                                if (b)
                                        result = a / b;
                                else
                                        result = 32'h00000000;
                end
`endif
// synopsys translate_on
`ifdef OR1200_CASE_DEFAULT
                default: begin
`else
                `OR1200_ALUOP_COMP, `OR1200_ALUOP_AND
`endif
                                result = result_and;
                end
        endcase
end
 
//
// Generate flag and flag write enable
//
always @(alu_op or result_sum or result_and or flagcomp) begin
        casex (alu_op)          // synopsys parallel_case
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
                `OR1200_ALUOP_ADD : begin
                        flagforw = (result_sum == 32'h0000_0000);
                        flag_we = 1'b1;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                        flagforw = (result_csum == 32'h0000_0000);
                        flag_we = 1'b1;
                end
`endif
                `OR1200_ALUOP_AND: begin
                        flagforw = (result_and == 32'h0000_0000);
                        flag_we = 1'b1;
                end
`endif
                `OR1200_ALUOP_COMP: begin
                        flagforw = flagcomp;
                        flag_we = 1'b1;
                end
                default: begin
                        flagforw = 1'b0;
                        flag_we = 1'b0;
                end
        endcase
end
 
//
// Generate SR[CY] write enable
//
always @(alu_op or cy_sum or cy_csum) begin
        casex (alu_op)          // synopsys parallel_case
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADD : begin
                        cyforw = cy_sum;
                        cy_we = 1'b1;
                end
                `OR1200_ALUOP_ADDC: begin
                        cyforw = cy_csum;
                        cy_we = 1'b1;
                end
`endif
                default: begin
                        cyforw = 1'b0;
                        cy_we = 1'b0;
                end
        endcase
end
 
//
// Shifts and rotation
//
always @(shrot_op or a or b) begin
        case (shrot_op)         // synopsys parallel_case
        `OR1200_SHROTOP_SLL :
                                shifted_rotated = (a << b[4:0]);
                `OR1200_SHROTOP_SRL :
                                shifted_rotated = (a >> b[4:0]);
 
`ifdef OR1200_IMPL_ALU_ROTATE
                `OR1200_SHROTOP_ROR :
                                shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
`endif
                default:
                                shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
        endcase
end
 
//
// First type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP1
always @(comp_op or a_eq_b or a_lt_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = a_eq_b;
                `OR1200_COP_SFNE:
                        flagcomp = ~a_eq_b;
                `OR1200_COP_SFGT:
                        flagcomp = ~(a_eq_b | a_lt_b);
                `OR1200_COP_SFGE:
                        flagcomp = ~a_lt_b;
                `OR1200_COP_SFLT:
                        flagcomp = a_lt_b;
                `OR1200_COP_SFLE:
                        flagcomp = a_eq_b | a_lt_b;
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
//
// Second type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP2
always @(comp_op or comp_a or comp_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = (comp_a == comp_b);
                `OR1200_COP_SFNE:
                        flagcomp = (comp_a != comp_b);
                `OR1200_COP_SFGT:
                        flagcomp = (comp_a > comp_b);
                `OR1200_COP_SFGE:
                        flagcomp = (comp_a >= comp_b);
                `OR1200_COP_SFLT:
                        flagcomp = (comp_a < comp_b);
                `OR1200_COP_SFLE:
                        flagcomp = (comp_a <= comp_b);
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's ALU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// ALU ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	1033	lampret	`// Revision 1.8 2002/09/07 05:42:02 lampret`
48			`// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.`
49			`//`
50	1032	lampret	`// Revision 1.7 2002/09/03 22:28:21 lampret`
51			`// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.`
52			`//`
53	1022	lampret	`// Revision 1.6 2002/03/29 16:40:10 lampret`
54			`// Added a directive to ignore signed division variables that are only used in simulation.`
55			`//`
56	795	lampret	`// Revision 1.5 2002/03/29 16:33:59 lampret`
57			`// Added again just recently removed full_case directive`
58			`//`
59	794	lampret	`// Revision 1.4 2002/03/29 15:16:53 lampret`
60			`// Some of the warnings fixed.`
61			`//`
62	788	lampret	`// Revision 1.3 2002/01/28 01:15:59 lampret`
63			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
64			`//`
65	617	lampret	`// Revision 1.2 2002/01/14 06:18:22 lampret`
66			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
67			`//`
68	562	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
69			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
70			`//`
71	504	lampret	`// Revision 1.10 2001/11/12 01:45:40 lampret`
72			`// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.`
73			`//`
74			`// Revision 1.9 2001/10/21 17:57:16 lampret`
75			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
76			`//`
77			`// Revision 1.8 2001/10/19 23:28:45 lampret`
78			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
79			`//`
80			`// Revision 1.7 2001/10/14 13:12:09 lampret`
81			`// MP3 version.`
82			`//`
83			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
84			`// no message`
85			`//`
86			`// Revision 1.2 2001/08/09 13:39:33 lampret`
87			`// Major clean-up.`
88			`//`
89			`// Revision 1.1 2001/07/20 00:46:03 lampret`
90			`// Development version of RTL. Libraries are missing.`
91			`//`
92			`//`
93
94			`// synopsys translate_off`
95			`include "timescale.v"
96			`// synopsys translate_on`
97			`include "or1200_defines.v"
98
99			`module or1200_alu(`
100			`a, b, mult_mac_result, macrc_op,`
101			`alu_op, shrot_op, comp_op,`
102	1032	lampret	`result, flagforw, flag_we,`
103			`cyforw, cy_we, carry`
104	504	lampret	`);`
105
106			parameter width = `OR1200_OPERAND_WIDTH;
107
108			`//`
109			`// I/O`
110			`//`
111			`input [width-1:0] a;`
112			`input [width-1:0] b;`
113			`input [width-1:0] mult_mac_result;`
114			`input macrc_op;`
115			input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
116			input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
117			input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
118			`output [width-1:0] result;`
119			`output flagforw;`
120			`output flag_we;`
121	1032	lampret	`output cyforw;`
122			`output cy_we;`
123			`input carry;`
124	504	lampret
125			`//`
126			`// Internal wires and regs`
127			`//`
128			`reg [width-1:0] result;`
129			`reg [width-1:0] shifted_rotated;`
130			`reg flagforw;`
131	617	lampret	`reg flagcomp;`
132	504	lampret	`reg flag_we;`
133	1032	lampret	`reg cy_we;`
134	795	lampret	`// synopsys translate_off`
135	788	lampret	`ifdef OR1200_SIM_ALU_DIV
136	504	lampret	`integer d1;`
137			`integer d2;`
138	788	lampret	`endif
139	795	lampret	`// synopsys translate_on`
140	504	lampret	`wire [width-1:0] comp_a;`
141			`wire [width-1:0] comp_b;`
142			`ifdef OR1200_IMPL_ALU_COMP1
143			`wire a_eq_b;`
144			`wire a_lt_b;`
145			`endif
146	617	lampret	`wire [width-1:0] result_sum;`
147	1032	lampret	`ifdef OR1200_IMPL_ADDC
148			`wire [width-1:0] result_csum;`
149	1033	lampret	`wire cy_csum;`
150	1032	lampret	`endif
151	617	lampret	`wire [width-1:0] result_and;`
152	1033	lampret	`wire cy_sum;`
153			`reg cyforw;`
154	504	lampret
155			`//`
156			`// Combinatorial logic`
157			`//`
158			`assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};`
159			`assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};`
160			`ifdef OR1200_IMPL_ALU_COMP1
161			`assign a_eq_b = (comp_a == comp_b);`
162			`assign a_lt_b = (comp_a < comp_b);`
163			`endif
164	1033	lampret	`assign {cy_sum, result_sum} = a + b;`
165	1032	lampret	`ifdef OR1200_IMPL_ADDC
166	1033	lampret	`assign {cy_csum, result_csum} = a + b + carry;`
167	1032	lampret	`endif
168	617	lampret	`assign result_and = a & b;`
169	504	lampret
170			`//`
171			`// Simulation check for bad ALU behavior`
172			`//`
173			`ifdef OR1200_WARNINGS
174			`// synopsys translate_off`
175			`always @(result) begin`
176			`if (result === 32'bx)`
177			`$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);`
178			`end`
179			`// synopsys translate_on`
180			`endif
181
182			`//`
183			`// Central part of the ALU`
184			`//`
185	617	lampret	`always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin`
186	1022	lampret	`ifdef OR1200_CASE_DEFAULT
187			`casex (alu_op) // synopsys parallel_case`
188			`else
189			`casex (alu_op) // synopsys full_case parallel_case`
190			`endif
191	504	lampret	`OR1200_ALUOP_SHROT : begin
192			`result = shifted_rotated;`
193			`end`
194			`OR1200_ALUOP_ADD : begin
195	617	lampret	`result = result_sum;`
196	504	lampret	`end`
197	1032	lampret	`ifdef OR1200_IMPL_ADDC
198			`OR1200_ALUOP_ADDC : begin
199			`result = result_csum;`
200			`end`
201			`endif
202	504	lampret	`OR1200_ALUOP_SUB : begin
203			`result = a - b;`
204			`end`
205			`OR1200_ALUOP_XOR : begin
206			`result = a ^ b;`
207			`end`
208			`OR1200_ALUOP_OR : begin
209			`result = a \| b;`
210			`end`
211			`OR1200_ALUOP_IMM : begin
212			`result = b;`
213			`end`
214			`OR1200_ALUOP_MOVHI : begin
215			`if (macrc_op) begin`
216			`result = mult_mac_result;`
217			`end`
218			`else begin`
219			`result = b << 16;`
220			`end`
221			`end`
222			`OR1200_ALUOP_MUL : begin
223			`result = mult_mac_result;`
224			`ifdef OR1200_VERBOSE
225			`// synopsys translate_off`
226			`$display("%t: MUL operation: %h * %h = %h", $time, a, b, mult_mac_result);`
227			`// synopsys translate_on`
228			`endif
229			`end`
230			`// synopsys translate_off`
231			`ifdef OR1200_SIM_ALU_DIV
232			`OR1200_ALUOP_DIV : begin
233			`d1 = a;`
234			`d2 = b;`
235			`$display("DIV operation: %d / %d = %d", d1, d2, d1/d2);`
236			`if (d2)`
237			`result = d1 / d2;`
238			`else`
239			`result = 32'h00000000;`
240			`end`
241			`endif
242			`ifdef OR1200_SIM_ALU_DIVU
243			`OR1200_ALUOP_DIVU : begin
244			`if (b)`
245			`result = a / b;`
246			`else`
247			`result = 32'h00000000;`
248			`end`
249			`endif
250			`// synopsys translate_on`
251	1022	lampret	`ifdef OR1200_CASE_DEFAULT
252			`default: begin`
253			`else
254			`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND
255			`endif
256	617	lampret	`result = result_and;`
257			`end`
258			`endcase`
259			`end`
260
261			`//`
262			`// Generate flag and flag write enable`
263			`//`
264			`always @(alu_op or result_sum or result_and or flagcomp) begin`
265	788	lampret	`casex (alu_op) // synopsys parallel_case`
266	1032	lampret	`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
267	617	lampret	`OR1200_ALUOP_ADD : begin
268			`flagforw = (result_sum == 32'h0000_0000);`
269	1032	lampret	`flag_we = 1'b1;`
270	617	lampret	`end`
271	1032	lampret	`ifdef OR1200_IMPL_ADDC
272			`OR1200_ALUOP_ADDC : begin
273			`flagforw = (result_csum == 32'h0000_0000);`
274			`flag_we = 1'b1;`
275			`end`
276			`endif
277	617	lampret	`OR1200_ALUOP_AND: begin
278			`flagforw = (result_and == 32'h0000_0000);`
279	1032	lampret	`flag_we = 1'b1;`
280	617	lampret	`end`
281	1032	lampret	`endif
282	504	lampret	`OR1200_ALUOP_COMP: begin
283	617	lampret	`flagforw = flagcomp;`
284			`flag_we = 1'b1;`
285	504	lampret	`end`
286	617	lampret	`default: begin`
287			`flagforw = 1'b0;`
288			`flag_we = 1'b0;`
289	504	lampret	`end`
290			`endcase`
291			`end`
292
293			`//`
294	1032	lampret	`// Generate SR[CY] write enable`
295			`//`
296	1033	lampret	`always @(alu_op or cy_sum or cy_csum) begin`
297	1032	lampret	`casex (alu_op) // synopsys parallel_case`
298			`ifdef OR1200_IMPL_ADDC
299	1033	lampret	`OR1200_ALUOP_ADD : begin
300			`cyforw = cy_sum;`
301	1032	lampret	`cy_we = 1'b1;`
302			`end`
303	1033	lampret	`OR1200_ALUOP_ADDC: begin
304			`cyforw = cy_csum;`
305			`cy_we = 1'b1;`
306			`end`
307	1032	lampret	`endif
308			`default: begin`
309	1033	lampret	`cyforw = 1'b0;`
310	1032	lampret	`cy_we = 1'b0;`
311			`end`
312			`endcase`
313			`end`
314
315			`//`
316	504	lampret	`// Shifts and rotation`
317			`//`
318			`always @(shrot_op or a or b) begin`
319			`case (shrot_op) // synopsys parallel_case`
320	562	lampret	`OR1200_SHROTOP_SLL :
321	504	lampret	`shifted_rotated = (a << b[4:0]);`
322			`OR1200_SHROTOP_SRL :
323			`shifted_rotated = (a >> b[4:0]);`
324	562	lampret
325	504	lampret	`ifdef OR1200_IMPL_ALU_ROTATE
326			`OR1200_SHROTOP_ROR :
327			`shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) \| (a >> b[4:0]);`
328			`endif
329			`default:`
330			`shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) \| a >> b[4:0];`
331			`endcase`
332			`end`
333
334			`//`
335			`// First type of compare implementation`
336			`//`
337			`ifdef OR1200_IMPL_ALU_COMP1
338			`always @(comp_op or a_eq_b or a_lt_b) begin`
339	788	lampret	`case(comp_op[2:0]) // synopsys parallel_case`
340	504	lampret	`OR1200_COP_SFEQ:
341	617	lampret	`flagcomp = a_eq_b;`
342	504	lampret	`OR1200_COP_SFNE:
343	617	lampret	`flagcomp = ~a_eq_b;`
344	504	lampret	`OR1200_COP_SFGT:
345	617	lampret	`flagcomp = ~(a_eq_b \| a_lt_b);`
346	504	lampret	`OR1200_COP_SFGE:
347	617	lampret	`flagcomp = ~a_lt_b;`
348	504	lampret	`OR1200_COP_SFLT:
349	617	lampret	`flagcomp = a_lt_b;`
350	504	lampret	`OR1200_COP_SFLE:
351	617	lampret	`flagcomp = a_eq_b \| a_lt_b;`
352	504	lampret	`default:`
353	617	lampret	`flagcomp = 1'b0;`
354	504	lampret	`endcase`
355			`end`
356			`endif
357
358			`//`
359			`// Second type of compare implementation`
360			`//`
361			`ifdef OR1200_IMPL_ALU_COMP2
362			`always @(comp_op or comp_a or comp_b) begin`
363	788	lampret	`case(comp_op[2:0]) // synopsys parallel_case`
364	504	lampret	`OR1200_COP_SFEQ:
365	617	lampret	`flagcomp = (comp_a == comp_b);`
366	504	lampret	`OR1200_COP_SFNE:
367	617	lampret	`flagcomp = (comp_a != comp_b);`
368	504	lampret	`OR1200_COP_SFGT:
369	617	lampret	`flagcomp = (comp_a > comp_b);`
370	504	lampret	`OR1200_COP_SFGE:
371	617	lampret	`flagcomp = (comp_a >= comp_b);`
372	504	lampret	`OR1200_COP_SFLT:
373	617	lampret	`flagcomp = (comp_a < comp_b);`
374	504	lampret	`OR1200_COP_SFLE:
375	617	lampret	`flagcomp = (comp_a <= comp_b);`
376	504	lampret	`default:`
377	617	lampret	`flagcomp = 1'b0;`
378	504	lampret	`endcase`
379			`end`
380			`endif
381
382			`endmodule`

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_6/] [or1200/] [rtl/] [verilog/] [or1200_alu.v] - Blame information for rev 1033