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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File_communication.v                                        ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/cores/DebugInterface/              ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000,2001 Authors                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2001/09/24 14:06:13  mohor
// Changes connected to the OpenRISC access (SPR read, SPR write).
//
// Revision 1.2  2001/09/20 10:10:30  mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
// Initial official release.
//
//
//
//
//
 
`ifdef DBG_IF_COMM
 
`include "dbg_timescale.v"
`include "dbg_defines.v"
//`include "dbg_tb_defines.v"
 
 
 
`define GDB_IN  "/projects/xess-damjan/sim/run/gdb_in.dat"
`define GDB_OUT "/projects/xess-damjan/sim/run/gdb_out.dat"
//`define GDB_IN        "/tmp/gdb_in.dat"
//`define GDB_OUT       "/tmp/gdb_out.dat"
//`define GDB_IN        "../src/gdb_in.dat"
//`define GDB_OUT       "../src/gdb_out.dat"
 
module dbg_comm2(P_TMS, P_TCK, P_TRST, P_TDI, P_TDO);
 
parameter Tp = 1;
parameter Tclk = 50;   // Clock half period (Clok period = 100 ns => 10 MHz)
 
output          P_TMS;
output          P_TCK;
output          P_TRST;
output          P_TDI;
input           P_TDO;
 
integer handle1, handle2;
reg [87:0] memory[0:0];
reg [87:0] file;
reg Mclk;
reg wb_rst_i;
 
reg alternator;
 
reg StartTesting;
reg P_TCK;
reg  P_TRST;
reg  P_TDI;
reg  P_TMS;
wire P_TDO;
 
reg transition_detected;
reg update_state;
reg latchedbit;
reg [31:0] data_out;
 
 
initial
begin
  P_TCK = 0;
  P_TMS = 0;
  P_TDI = 0;
  alternator = 0;
  StartTesting = 0;
  wb_rst_i = 0;
  P_TRST = 1;
  #500;
  wb_rst_i = 1;
  P_TRST = 0;
  #500;
  wb_rst_i = 0;
  P_TRST = 1;
 
  #2000;
  StartTesting = 1;
  $display("StartTesting = 1");
 
 
end
 
initial
begin
  wait(StartTesting);
  while(1)
  begin
//    while(~transition_detected)
//      begin
        #1000;
        $readmemh(`GDB_OUT, memory);
//        $readmemh(`GDB_OUT, file);
//      end
//    wait(update_state);
    handle1 = $fopen(`GDB_OUT);
//    $fwrite(handle1, "%h", memory[0]);  // To ack to jp1 that we read dgb_out.dat
    $fwrite(handle1, "%h", {Temp[15:1], 1'b1});  // To ack to jp1 that we read dgb_out.dat
    $fclose(handle1);
//    end
  end
end
 
//always alternator = #100 ~alternator;
 
//always @ (posedge P_TCK or alternator)
always @ (posedge Mclk)
begin
  handle2 = $fopen(`GDB_IN);
  wait(update_state);
  $fdisplay(handle2, "%h", data_out);  // Writing output data to file
  $fclose(handle2);
end
 
wire [87:0]word = memory[0];
 
always @ (posedge Mclk or posedge wb_rst_i)
begin
  if(wb_rst_i)
    begin
      transition_detected <= 1'b0;
    end
  else if(!word[0])
    begin
      file = word;
      transition_detected = 1'b1;
    end
  else
    transition_detected = 1'b0;
end
 
wire [87:0]Temp = file;
/*
always @ (posedge Mclk or posedge wb_rst_i)
begin
  if(wb_rst_i)
    begin
      transition_detected <= 1'b0;
      latchedbit <= 1'b0;
    end
  else
  if(~latchedbit & Temp[2])
    transition_detected = 1'b1;
  else
    transition_detected = 1'b0;
  latchedbit <= Temp[2];
end
*/
 
 
 
reg [3:0]  chain     ;
reg [7:0]  chain_crc ;
reg [31:0] address   ;
reg        rw        ;
reg [31:0] data      ;
reg [7:0]  data_crc  ;
 
always @ (posedge Mclk or posedge wb_rst_i)
begin
  if(wb_rst_i)
    begin
      chain     = 'h0;
      chain_crc = 'h0;
      address   = 'h0;
      rw        = 'h0;
      data      = 'h0;
      data_crc  = 'h0;
    end
  else
  if(transition_detected)
  begin
    chain     = Temp[87:84];
    chain_crc = Temp[83:76];
    address   = Temp[75:44];
    rw        = Temp[43];
    data      = Temp[42:11];
    data_crc  = Temp[10:3];
  end
end
 
 
 
 
// assign P_TCK  = Temp[0];
// assign P_TRST = Temp[1];
// assign P_TDI  = Temp[2];
// assign P_TMS  = Temp[3];
 
 
 
always @ (posedge Mclk or posedge wb_rst_i)
begin
  if(wb_rst_i)
    update_state <= 1'b0;
  else
  if(transition_detected)
    begin
      update_state <= 1'b0;
        begin
          SetInstruction(`CHAIN_SELECT);
          ChainSelect(chain, chain_crc);                  // {chain, crc}
          SetInstruction(`DEBUG);
          if(rw)
            begin
              WriteRISCRegister(data, address, data_crc);   // {data, addr, crc}
              update_state <= 1'b1;
            end
          else
            begin
              ReadRISCRegister(address, data_crc, data_out);          // {addr, crc, read_data}
              ReadRISCRegister(address, data_crc, data_out);          // {addr, crc, read_data}
              update_state <= 1'b1;
            end
        end
    end
end
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Generating master clock (RISC clock) 10 MHz
initial
begin
  Mclk<=#Tp 0;
  #1 forever #`RISC_CLOCK Mclk<=~Mclk;
end
 
// Generating random number for use in DATAOUT_RISC[31:0]
reg [31:0] RandNumb;
always @ (posedge Mclk or posedge wb_rst_i)
begin
  if(wb_rst_i)
    RandNumb[31:0]<=#Tp 0;
  else
    RandNumb[31:0]<=#Tp RandNumb[31:0] + 1;
end
 
wire [31:0] DataIn = RandNumb;
 
// Connecting dbgTAP module
`ifdef UNUSED
dbg_top dbg1  (.tms_pad_i(P_TMS), .tck_pad_i(P_TCK), .trst_pad_i(P_TRST), .tdi_pad_i(P_TDI), .tdo_pad_o(P_TDO),
               .wb_rst_i(wb_rst_i), .risc_clk_i(Mclk), .risc_addr_o(), .risc_data_i(DataIn),
               .risc_data_o(), .wp_i(11'h0), .bp_i(1'b0),
               .opselect_o(), .lsstatus_i(4'h0), .istatus_i(2'h0),
               .risc_stall_o(), .reset_o()
              );
`endif
 
 
 
// Generation of the TCLK signal
task GenClk;
  input [7:0] Number;
  integer i;
  begin
    for(i=0; i<Number; i=i+1)
      begin
        #Tclk P_TCK<=1;
        #Tclk P_TCK<=0;
      end
  end
endtask
 
 
 
// sets the instruction to the IR register and goes to the RunTestIdle state
task SetInstruction;
  input [3:0] Instr;
  integer i;
 
  begin
    P_TMS<=#Tp 1;
    GenClk(2);
    P_TMS<=#Tp 0;
    GenClk(2);  // we are in shiftIR
 
    for(i=0; i<`IR_LENGTH-1; i=i+1)   // error?
    begin
      P_TDI<=#Tp Instr[i];
      GenClk(1);
    end
 
    P_TDI<=#Tp Instr[i]; // last shift
    P_TMS<=#Tp 1;        // going out of shiftIR
    GenClk(1);
      P_TDI<=#Tp 'hz;    // tri-state
    GenClk(1);
    P_TMS<=#Tp 0;
    GenClk(1);       // we are in RunTestIdle
  end
endtask
 
 
// sets the selected scan chain and goes to the RunTestIdle state
task ChainSelect;
  input [3:0] Data;
  input [7:0] Crc;
  integer i;
 
  begin
    P_TMS<=#Tp 1;
    GenClk(1);
    P_TMS<=#Tp 0;
    GenClk(2);  // we are in shiftDR
 
    for(i=0; i<`CHAIN_ID_LENGTH; i=i+1)
    begin
      P_TDI<=#Tp Data[i];
      GenClk(1);
    end
 
    for(i=0; i<`CRC_LENGTH-1; i=i+1)
    begin
      P_TDI<=#Tp Crc[i];
      GenClk(1);
    end
 
    P_TDI<=#Tp Crc[i]; // last shift
    P_TMS<=#Tp 1;        // going out of shiftIR
    GenClk(1);
      P_TDI<=#Tp 'hz; // tri-state
    GenClk(1);
    P_TMS<=#Tp 0;
    GenClk(1);       // we are in RunTestIdle
  end
endtask
 
 
// Write the RISC register
task WriteRISCRegister;
  input [31:0] Data;
  input [31:0] Address;
  input [`CRC_LENGTH-1:0] Crc;
  integer i;
 
  begin
    P_TMS<=#Tp 1;
    GenClk(1);
    P_TMS<=#Tp 0;
    GenClk(2);  // we are in shiftDR
 
    for(i=0; i<32; i=i+1)
    begin
      P_TDI<=#Tp Address[i];  // Shifting address
      GenClk(1);
    end
 
    P_TDI<=#Tp 1;             // shifting RW bit = write
    GenClk(1);
 
    for(i=0; i<32; i=i+1)
    begin
      P_TDI<=#Tp Data[i];     // Shifting data
      GenClk(1);
    end
 
    for(i=0; i<`CRC_LENGTH-1; i=i+1)
    begin
      P_TDI<=#Tp Crc[i];     // Shifting CRC
      GenClk(1);
    end
 
    P_TDI<=#Tp Crc[i];        // shifting last bit of CRC
    P_TMS<=#Tp 1;        // going out of shiftIR
    GenClk(1);
      P_TDI<=#Tp 'hz;        // tristate TDI
    GenClk(1);
 
    P_TMS<=#Tp 0;
    GenClk(1);       // we are in RunTestIdle
 
    GenClk(10);      // Generating few clock cycles needed for the write operation to accomplish
  end
endtask
 
 
// Reads the RISC register and latches the data so it is ready for reading
task ReadRISCRegister;
  input [31:0] Address;
  input [7:0] Crc;
  output [31:0] read_data;
  integer i;
 
  begin
    P_TMS<=#Tp 1;
    GenClk(1);
    P_TMS<=#Tp 0;
    GenClk(2);  // we are in shiftDR
 
    for(i=0; i<32; i=i+1)
    begin
      P_TDI<=#Tp Address[i];  // Shifting address
      GenClk(1);
    end
 
    P_TDI<=#Tp 0;             // shifting RW bit = read
    GenClk(1);
 
    for(i=0; i<32; i=i+1)
    begin
      P_TDI<=#Tp 0;     // Shifting data. Data is not important in read cycle.
      read_data[i]<=#Tp P_TDO;    // Assembling data to read_data
      GenClk(1);
    end
 
    for(i=0; i<`CRC_LENGTH-1; i=i+1)
    begin
      P_TDI<=#Tp Crc[i];     // Shifting CRC.
      GenClk(1);
    end
 
    P_TDI<=#Tp Crc[i];   // Shifting last bit of CRC.
    P_TMS<=#Tp 1;        // going out of shiftIR
    GenClk(1);
      P_TDI<=#Tp 'hz;   // Tristate TDI.
    GenClk(1);
 
    P_TMS<=#Tp 0;
    GenClk(1);       // we are in RunTestIdle
  end
endtask
 
 
 
 
 
 
 
endmodule // TAP
 
`endif

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[/] [or1k/] [tags/] [stable/] [mp3/] [bench/] [verilog/] [dbg_comm2.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File_communication.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/cores/DebugInterface/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is avaliable in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000,2001 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48			`// Revision 1.3 2001/09/24 14:06:13 mohor`
49			`// Changes connected to the OpenRISC access (SPR read, SPR write).`
50			`//`
51			`// Revision 1.2 2001/09/20 10:10:30 mohor`
52			`// Working version. Few bugs fixed, comments added.`
53			`//`
54			`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`
55			`// Initial official release.`
56			`//`
57			`//`
58			`//`
59			`//`
60			`//`
61
62			`ifdef DBG_IF_COMM
63
64			`include "dbg_timescale.v"
65			`include "dbg_defines.v"
66			//`include "dbg_tb_defines.v"
67
68
69
70			`define GDB_IN "/projects/xess-damjan/sim/run/gdb_in.dat"
71			`define GDB_OUT "/projects/xess-damjan/sim/run/gdb_out.dat"
72			//`define GDB_IN "/tmp/gdb_in.dat"
73			//`define GDB_OUT "/tmp/gdb_out.dat"
74			//`define GDB_IN "../src/gdb_in.dat"
75			//`define GDB_OUT "../src/gdb_out.dat"
76
77			`module dbg_comm2(P_TMS, P_TCK, P_TRST, P_TDI, P_TDO);`
78
79			`parameter Tp = 1;`
80			`parameter Tclk = 50; // Clock half period (Clok period = 100 ns => 10 MHz)`
81
82			`output P_TMS;`
83			`output P_TCK;`
84			`output P_TRST;`
85			`output P_TDI;`
86			`input P_TDO;`
87
88			`integer handle1, handle2;`
89			`reg [87:0] memory[0:0];`
90			`reg [87:0] file;`
91			`reg Mclk;`
92			`reg wb_rst_i;`
93
94			`reg alternator;`
95
96			`reg StartTesting;`
97			`reg P_TCK;`
98			`reg P_TRST;`
99			`reg P_TDI;`
100			`reg P_TMS;`
101			`wire P_TDO;`
102
103			`reg transition_detected;`
104			`reg update_state;`
105			`reg latchedbit;`
106			`reg [31:0] data_out;`
107
108
109			`initial`
110			`begin`
111			`P_TCK = 0;`
112			`P_TMS = 0;`
113			`P_TDI = 0;`
114			`alternator = 0;`
115			`StartTesting = 0;`
116			`wb_rst_i = 0;`
117			`P_TRST = 1;`
118			`#500;`
119			`wb_rst_i = 1;`
120			`P_TRST = 0;`
121			`#500;`
122			`wb_rst_i = 0;`
123			`P_TRST = 1;`
124
125			`#2000;`
126			`StartTesting = 1;`
127			`$display("StartTesting = 1");`
128
129
130			`end`
131
132			`initial`
133			`begin`
134			`wait(StartTesting);`
135			`while(1)`
136			`begin`
137			`// while(~transition_detected)`
138			`// begin`
139			`#1000;`
140			$readmemh(`GDB_OUT, memory);
141			// $readmemh(`GDB_OUT, file);
142			`// end`
143			`// wait(update_state);`
144			handle1 = $fopen(`GDB_OUT);
145			`// $fwrite(handle1, "%h", memory[0]); // To ack to jp1 that we read dgb_out.dat`
146			`$fwrite(handle1, "%h", {Temp[15:1], 1'b1}); // To ack to jp1 that we read dgb_out.dat`
147			`$fclose(handle1);`
148			`// end`
149			`end`
150			`end`
151
152			`//always alternator = #100 ~alternator;`
153
154			`//always @ (posedge P_TCK or alternator)`
155			`always @ (posedge Mclk)`
156			`begin`
157			handle2 = $fopen(`GDB_IN);
158			`wait(update_state);`
159			`$fdisplay(handle2, "%h", data_out); // Writing output data to file`
160			`$fclose(handle2);`
161			`end`
162
163			`wire [87:0]word = memory[0];`
164
165			`always @ (posedge Mclk or posedge wb_rst_i)`
166			`begin`
167			`if(wb_rst_i)`
168			`begin`
169			`transition_detected <= 1'b0;`
170			`end`
171			`else if(!word[0])`
172			`begin`
173			`file = word;`
174			`transition_detected = 1'b1;`
175			`end`
176			`else`
177			`transition_detected = 1'b0;`
178			`end`
179
180			`wire [87:0]Temp = file;`
181			`/*`
182			`always @ (posedge Mclk or posedge wb_rst_i)`
183			`begin`
184			`if(wb_rst_i)`
185			`begin`
186			`transition_detected <= 1'b0;`
187			`latchedbit <= 1'b0;`
188			`end`
189			`else`
190			`if(~latchedbit & Temp[2])`
191			`transition_detected = 1'b1;`
192			`else`
193			`transition_detected = 1'b0;`
194			`latchedbit <= Temp[2];`
195			`end`
196			`*/`
197
198
199
200			`reg [3:0] chain ;`
201			`reg [7:0] chain_crc ;`
202			`reg [31:0] address ;`
203			`reg rw ;`
204			`reg [31:0] data ;`
205			`reg [7:0] data_crc ;`
206
207			`always @ (posedge Mclk or posedge wb_rst_i)`
208			`begin`
209			`if(wb_rst_i)`
210			`begin`
211			`chain = 'h0;`
212			`chain_crc = 'h0;`
213			`address = 'h0;`
214			`rw = 'h0;`
215			`data = 'h0;`
216			`data_crc = 'h0;`
217			`end`
218			`else`
219			`if(transition_detected)`
220			`begin`
221			`chain = Temp[87:84];`
222			`chain_crc = Temp[83:76];`
223			`address = Temp[75:44];`
224			`rw = Temp[43];`
225			`data = Temp[42:11];`
226			`data_crc = Temp[10:3];`
227			`end`
228			`end`
229
230
231
232
233			`// assign P_TCK = Temp[0];`
234			`// assign P_TRST = Temp[1];`
235			`// assign P_TDI = Temp[2];`
236			`// assign P_TMS = Temp[3];`
237
238
239
240			`always @ (posedge Mclk or posedge wb_rst_i)`
241			`begin`
242			`if(wb_rst_i)`
243			`update_state <= 1'b0;`
244			`else`
245			`if(transition_detected)`
246			`begin`
247			`update_state <= 1'b0;`
248			`begin`
249			SetInstruction(`CHAIN_SELECT);
250			`ChainSelect(chain, chain_crc); // {chain, crc}`
251			SetInstruction(`DEBUG);
252			`if(rw)`
253			`begin`
254			`WriteRISCRegister(data, address, data_crc); // {data, addr, crc}`
255			`update_state <= 1'b1;`
256			`end`
257			`else`
258			`begin`
259			`ReadRISCRegister(address, data_crc, data_out); // {addr, crc, read_data}`
260			`ReadRISCRegister(address, data_crc, data_out); // {addr, crc, read_data}`
261			`update_state <= 1'b1;`
262			`end`
263			`end`
264			`end`
265			`end`
266
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291
292			`// Generating master clock (RISC clock) 10 MHz`
293			`initial`
294			`begin`
295			`Mclk<=#Tp 0;`
296			#1 forever #`RISC_CLOCK Mclk<=~Mclk;
297			`end`
298
299			`// Generating random number for use in DATAOUT_RISC[31:0]`
300			`reg [31:0] RandNumb;`
301			`always @ (posedge Mclk or posedge wb_rst_i)`
302			`begin`
303			`if(wb_rst_i)`
304			`RandNumb[31:0]<=#Tp 0;`
305			`else`
306			`RandNumb[31:0]<=#Tp RandNumb[31:0] + 1;`
307			`end`
308
309			`wire [31:0] DataIn = RandNumb;`
310
311			`// Connecting dbgTAP module`
312			`ifdef UNUSED
313			`dbg_top dbg1 (.tms_pad_i(P_TMS), .tck_pad_i(P_TCK), .trst_pad_i(P_TRST), .tdi_pad_i(P_TDI), .tdo_pad_o(P_TDO),`
314			`.wb_rst_i(wb_rst_i), .risc_clk_i(Mclk), .risc_addr_o(), .risc_data_i(DataIn),`
315			`.risc_data_o(), .wp_i(11'h0), .bp_i(1'b0),`
316			`.opselect_o(), .lsstatus_i(4'h0), .istatus_i(2'h0),`
317			`.risc_stall_o(), .reset_o()`
318			`);`
319			`endif
320
321
322
323			`// Generation of the TCLK signal`
324			`task GenClk;`
325			`input [7:0] Number;`
326			`integer i;`
327			`begin`
328			`for(i=0; i<Number; i=i+1)`
329			`begin`
330			`#Tclk P_TCK<=1;`
331			`#Tclk P_TCK<=0;`
332			`end`
333			`end`
334			`endtask`
335
336
337
338			`// sets the instruction to the IR register and goes to the RunTestIdle state`
339			`task SetInstruction;`
340			`input [3:0] Instr;`
341			`integer i;`
342
343			`begin`
344			`P_TMS<=#Tp 1;`
345			`GenClk(2);`
346			`P_TMS<=#Tp 0;`
347			`GenClk(2); // we are in shiftIR`
348
349			for(i=0; i<`IR_LENGTH-1; i=i+1) // error?
350			`begin`
351			`P_TDI<=#Tp Instr[i];`
352			`GenClk(1);`
353			`end`
354
355			`P_TDI<=#Tp Instr[i]; // last shift`
356			`P_TMS<=#Tp 1; // going out of shiftIR`
357			`GenClk(1);`
358			`P_TDI<=#Tp 'hz; // tri-state`
359			`GenClk(1);`
360			`P_TMS<=#Tp 0;`
361			`GenClk(1); // we are in RunTestIdle`
362			`end`
363			`endtask`
364
365
366			`// sets the selected scan chain and goes to the RunTestIdle state`
367			`task ChainSelect;`
368			`input [3:0] Data;`
369			`input [7:0] Crc;`
370			`integer i;`
371
372			`begin`
373			`P_TMS<=#Tp 1;`
374			`GenClk(1);`
375			`P_TMS<=#Tp 0;`
376			`GenClk(2); // we are in shiftDR`
377
378			for(i=0; i<`CHAIN_ID_LENGTH; i=i+1)
379			`begin`
380			`P_TDI<=#Tp Data[i];`
381			`GenClk(1);`
382			`end`
383
384			for(i=0; i<`CRC_LENGTH-1; i=i+1)
385			`begin`
386			`P_TDI<=#Tp Crc[i];`
387			`GenClk(1);`
388			`end`
389
390			`P_TDI<=#Tp Crc[i]; // last shift`
391			`P_TMS<=#Tp 1; // going out of shiftIR`
392			`GenClk(1);`
393			`P_TDI<=#Tp 'hz; // tri-state`
394			`GenClk(1);`
395			`P_TMS<=#Tp 0;`
396			`GenClk(1); // we are in RunTestIdle`
397			`end`
398			`endtask`
399
400
401			`// Write the RISC register`
402			`task WriteRISCRegister;`
403			`input [31:0] Data;`
404			`input [31:0] Address;`
405			input [`CRC_LENGTH-1:0] Crc;
406			`integer i;`
407
408			`begin`
409			`P_TMS<=#Tp 1;`
410			`GenClk(1);`
411			`P_TMS<=#Tp 0;`
412			`GenClk(2); // we are in shiftDR`
413
414			`for(i=0; i<32; i=i+1)`
415			`begin`
416			`P_TDI<=#Tp Address[i]; // Shifting address`
417			`GenClk(1);`
418			`end`
419
420			`P_TDI<=#Tp 1; // shifting RW bit = write`
421			`GenClk(1);`
422
423			`for(i=0; i<32; i=i+1)`
424			`begin`
425			`P_TDI<=#Tp Data[i]; // Shifting data`
426			`GenClk(1);`
427			`end`
428
429			for(i=0; i<`CRC_LENGTH-1; i=i+1)
430			`begin`
431			`P_TDI<=#Tp Crc[i]; // Shifting CRC`
432			`GenClk(1);`
433			`end`
434
435			`P_TDI<=#Tp Crc[i]; // shifting last bit of CRC`
436			`P_TMS<=#Tp 1; // going out of shiftIR`
437			`GenClk(1);`
438			`P_TDI<=#Tp 'hz; // tristate TDI`
439			`GenClk(1);`
440
441			`P_TMS<=#Tp 0;`
442			`GenClk(1); // we are in RunTestIdle`
443
444			`GenClk(10); // Generating few clock cycles needed for the write operation to accomplish`
445			`end`
446			`endtask`
447
448
449			`// Reads the RISC register and latches the data so it is ready for reading`
450			`task ReadRISCRegister;`
451			`input [31:0] Address;`
452			`input [7:0] Crc;`
453			`output [31:0] read_data;`
454			`integer i;`
455
456			`begin`
457			`P_TMS<=#Tp 1;`
458			`GenClk(1);`
459			`P_TMS<=#Tp 0;`
460			`GenClk(2); // we are in shiftDR`
461
462			`for(i=0; i<32; i=i+1)`
463			`begin`
464			`P_TDI<=#Tp Address[i]; // Shifting address`
465			`GenClk(1);`
466			`end`
467
468			`P_TDI<=#Tp 0; // shifting RW bit = read`
469			`GenClk(1);`
470
471			`for(i=0; i<32; i=i+1)`
472			`begin`
473			`P_TDI<=#Tp 0; // Shifting data. Data is not important in read cycle.`
474			`read_data[i]<=#Tp P_TDO; // Assembling data to read_data`
475			`GenClk(1);`
476			`end`
477
478			for(i=0; i<`CRC_LENGTH-1; i=i+1)
479			`begin`
480			`P_TDI<=#Tp Crc[i]; // Shifting CRC.`
481			`GenClk(1);`
482			`end`
483
484			`P_TDI<=#Tp Crc[i]; // Shifting last bit of CRC.`
485			`P_TMS<=#Tp 1; // going out of shiftIR`
486			`GenClk(1);`
487			`P_TDI<=#Tp 'hz; // Tristate TDI.`
488			`GenClk(1);`
489
490			`P_TMS<=#Tp 0;`
491			`GenClk(1); // we are in RunTestIdle`
492			`end`
493			`endtask`
494
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500
501			`endmodule // TAP`
502
503			`endif