1 |
266 |
lampret |
//////////////////////////////////////////////////////////////////////
|
2 |
|
|
//// ////
|
3 |
|
|
//// OR1200's simulation monitor ////
|
4 |
|
|
//// ////
|
5 |
|
|
//// This file is part of the OpenRISC 1200 project ////
|
6 |
|
|
//// http://www.opencores.org/cores/or1k/ ////
|
7 |
|
|
//// ////
|
8 |
|
|
//// Description ////
|
9 |
|
|
//// Simulation monitor ////
|
10 |
|
|
//// ////
|
11 |
|
|
//// To Do: ////
|
12 |
|
|
//// - move it to bench ////
|
13 |
|
|
//// ////
|
14 |
|
|
//// Author(s): ////
|
15 |
|
|
//// - Damjan Lampret, lampret@opencores.org ////
|
16 |
|
|
//// ////
|
17 |
|
|
//////////////////////////////////////////////////////////////////////
|
18 |
|
|
//// ////
|
19 |
|
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
20 |
|
|
//// ////
|
21 |
|
|
//// This source file may be used and distributed without ////
|
22 |
|
|
//// restriction provided that this copyright statement is not ////
|
23 |
|
|
//// removed from the file and that any derivative work contains ////
|
24 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
25 |
|
|
//// ////
|
26 |
|
|
//// This source file is free software; you can redistribute it ////
|
27 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
28 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
29 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
30 |
|
|
//// later version. ////
|
31 |
|
|
//// ////
|
32 |
|
|
//// This source is distributed in the hope that it will be ////
|
33 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
34 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
35 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
36 |
|
|
//// details. ////
|
37 |
|
|
//// ////
|
38 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
39 |
|
|
//// Public License along with this source; if not, download it ////
|
40 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
41 |
|
|
//// ////
|
42 |
|
|
//////////////////////////////////////////////////////////////////////
|
43 |
|
|
//
|
44 |
|
|
// CVS Revision History
|
45 |
|
|
//
|
46 |
|
|
// $Log: not supported by cvs2svn $
|
47 |
|
|
// Revision 1.1 2001/08/20 18:17:52 damjan
|
48 |
|
|
// Initial revision
|
49 |
|
|
//
|
50 |
|
|
// Revision 1.1 2001/08/13 03:37:07 lampret
|
51 |
|
|
// Added monitor.v and timescale.v
|
52 |
|
|
//
|
53 |
|
|
// Revision 1.1 2001/07/20 00:46:03 lampret
|
54 |
|
|
// Development version of RTL. Libraries are missing.
|
55 |
|
|
//
|
56 |
|
|
//
|
57 |
|
|
|
58 |
|
|
`include "defines.v"
|
59 |
|
|
|
60 |
|
|
// Enable debug_mem task. Only affects simulation.
|
61 |
|
|
`define enable_debug_mem
|
62 |
|
|
|
63 |
|
|
// Enable display_arch_state task. Only affects simulation.
|
64 |
|
|
`define enable_display_arch_state
|
65 |
|
|
|
66 |
|
|
module or1200_monitor;
|
67 |
|
|
|
68 |
|
|
task monitortask;
|
69 |
|
|
begin
|
70 |
|
|
end
|
71 |
|
|
endtask
|
72 |
|
|
|
73 |
|
|
integer fexe;
|
74 |
|
|
reg [23:0] ref;
|
75 |
|
|
|
76 |
|
|
initial begin
|
77 |
|
|
ref = 0;
|
78 |
|
|
fexe = $fopen("executed.log");
|
79 |
|
|
$timeformat (-9, 2, " ns", 12);
|
80 |
|
|
end
|
81 |
|
|
|
82 |
|
|
task finish_simulation;
|
83 |
|
|
begin
|
84 |
|
|
$fclose(fexe);
|
85 |
|
|
display_arch_state;
|
86 |
|
|
display_memory(0, 8191);
|
87 |
|
|
$shm_save;
|
88 |
|
|
$shm_close;
|
89 |
|
|
$dumpflush;
|
90 |
|
|
$finish;
|
91 |
|
|
end
|
92 |
|
|
endtask
|
93 |
|
|
|
94 |
|
|
task caught_sys203;
|
95 |
|
|
begin
|
96 |
|
|
$display("simulation terminated due to l.sys 203");
|
97 |
|
|
finish_simulation;
|
98 |
|
|
end
|
99 |
|
|
endtask
|
100 |
|
|
|
101 |
|
|
task display_arch_state;
|
102 |
|
|
reg [5:0] i;
|
103 |
|
|
reg [31:0] r;
|
104 |
|
|
integer j;
|
105 |
|
|
begin
|
106 |
|
|
`ifdef enable_display_arch_state
|
107 |
|
|
ref = ref + 1;
|
108 |
|
|
// if (ref == 17890) begin
|
109 |
|
|
// $dumpfile("dump.vcd");
|
110 |
|
|
// $dumpvars(20,tb_or1200);
|
111 |
|
|
// end
|
112 |
|
|
$fwrite(fexe, "\nEXECUTED(): %h: %h", xess_top.i_xess_fpga.risc.cpu.except.wb_pc, xess_top.i_xess_fpga.risc.cpu.id.wb_insn);
|
113 |
|
|
for(i = 0; i < 32; i = i + 1) begin
|
114 |
|
|
if (i % 4 == 0)
|
115 |
|
|
$fdisplay(fexe);
|
116 |
|
|
`ifdef XILINX_RAMB4
|
117 |
|
|
r = 32'h0000_0000;
|
118 |
|
|
for(j = 0; j < 16; j = j + 1) begin
|
119 |
|
|
r[j] = xess_top.i_xess_fpga.risc.cpu.rf.rf_a.ramb4_s16_0.mem[i*16+j];
|
120 |
|
|
end
|
121 |
|
|
for(j = 0; j < 16; j = j + 1) begin
|
122 |
|
|
r[j+16] = xess_top.i_xess_fpga.risc.cpu.rf.rf_a.ramb4_s16_1.mem[i*16+j];
|
123 |
|
|
end
|
124 |
|
|
$fwrite(fexe, "GPR%d: %h ", i, r);
|
125 |
|
|
`else
|
126 |
|
|
`ifdef XILINX_RAM32X1D
|
127 |
|
|
`else
|
128 |
|
|
`ifdef ARTISAN_SDP
|
129 |
|
|
`else
|
130 |
|
|
$fwrite(fexe, "GPR%d: %h ", i, xess_top.i_xess_fpga.risc.cpu.rf.rf_a.mem[i]);
|
131 |
|
|
`endif
|
132 |
|
|
`endif
|
133 |
|
|
`endif
|
134 |
|
|
end
|
135 |
|
|
$fdisplay(fexe);
|
136 |
|
|
r = xess_top.i_xess_fpga.risc.cpu.sprs.sr;
|
137 |
|
|
$fwrite(fexe, "SR : %h ", r);
|
138 |
|
|
r = xess_top.i_xess_fpga.risc.cpu.sprs.epcr;
|
139 |
|
|
$fwrite(fexe, "EPCR0: %h ", r);
|
140 |
|
|
r = xess_top.i_xess_fpga.risc.cpu.sprs.eear;
|
141 |
|
|
$fwrite(fexe, "EEAR0: %h ", r);
|
142 |
|
|
r = xess_top.i_xess_fpga.risc.cpu.sprs.esr;
|
143 |
|
|
$fdisplay(fexe, "ESR0 : %h", r);
|
144 |
|
|
// $fdisplay(fexe);
|
145 |
|
|
`endif
|
146 |
|
|
end
|
147 |
|
|
endtask
|
148 |
|
|
|
149 |
|
|
task display_memory;
|
150 |
|
|
input [31:0] from;
|
151 |
|
|
input [31:0] to;
|
152 |
|
|
integer i;
|
153 |
|
|
begin
|
154 |
|
|
// for(i = from; i < to; i = i + 4)
|
155 |
|
|
// $display("mem[%h] = %h mem[%h] = %h mem[%h] = %h mem[%h] = %h ",
|
156 |
|
|
// i, sram2.ramCore[i], i+4, sram2.ramCore[i+1], i+8, sram2.ramCore[i+2], i+12, sram2.ramCore[i+3]); //zSramX32
|
157 |
|
|
// i<<2, sram2.mem[i], (i<<2)+4, sram2.mem[i+1], (i<<2)+8, sram2.mem[i+2], (i<<2)+12, sram2.mem[i+3]); //sram32kx32
|
158 |
|
|
end
|
159 |
|
|
endtask
|
160 |
|
|
|
161 |
|
|
task debug_mem;
|
162 |
|
|
input [79:0] device;
|
163 |
|
|
input write;
|
164 |
|
|
input [31:0] addr;
|
165 |
|
|
input [31:0] data;
|
166 |
|
|
input [3:0] bs;
|
167 |
|
|
begin
|
168 |
|
|
`ifdef enable_debug_mem
|
169 |
|
|
if (write)
|
170 |
|
|
$display( "%t: WRITE to %s addr 0x%h with a value of 0x%h using byte enables of 'b%b", $time, device, addr, data, bs);
|
171 |
|
|
else
|
172 |
|
|
$display( "%t: READ from %s addr 0x%h which contains a value of 0x%h using byte enables of 'b%b", $time, device, addr, data, bs);
|
173 |
|
|
`endif
|
174 |
|
|
end
|
175 |
|
|
endtask
|
176 |
|
|
|
177 |
|
|
always @(posedge xess_top.i_xess_fpga.risc.cpu.id.clk)
|
178 |
|
|
if (!xess_top.i_xess_fpga.risc.cpu.id.wb_freeze) begin
|
179 |
|
|
#2;
|
180 |
|
|
if ((xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h1500ffff) && (xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h14000000)
|
181 |
|
|
&& (xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h14004444))
|
182 |
|
|
display_arch_state;
|
183 |
|
|
if (xess_top.i_xess_fpga.risc.cpu.id.ex_insn == 32'h200000cb) // small hack to stop simulation (l.sys 203)
|
184 |
|
|
caught_sys203;
|
185 |
|
|
end
|
186 |
|
|
|
187 |
|
|
endmodule
|
188 |
|
|
|
189 |
|
|
|