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[/] [or1k/] [tags/] [stable/] [mp3/] [lib/] [xilinx/] [unisims/] [OR16.v] - Blame information for rev 1765

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1 266 lampret
// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/OR16.v,v 1.1.1.1 2001-11-04 18:59:50 lampret Exp $
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/*
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FUNCTION        : 16-INPUT OR GATE
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*/
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`timescale  100 ps / 10 ps
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`celldefine
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module OR16 (O, I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15);
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    parameter cds_action = "ignore";
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    output O;
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    input  I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;
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    or O1 (O, I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15);
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    specify
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        (I0 *> O) = (1, 1);
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        (I1 *> O) = (1, 1);
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        (I2 *> O) = (1, 1);
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        (I3 *> O) = (1, 1);
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        (I4 *> O) = (1, 1);
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        (I5 *> O) = (1, 1);
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        (I6 *> O) = (1, 1);
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        (I7 *> O) = (1, 1);
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        (I8 *> O) = (1, 1);
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        (I9 *> O) = (1, 1);
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        (I10 *> O) = (1, 1);
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        (I11 *> O) = (1, 1);
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        (I12 *> O) = (1, 1);
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        (I13 *> O) = (1, 1);
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        (I14 *> O) = (1, 1);
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        (I15 *> O) = (1, 1);
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    endspecify
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endmodule
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`endcelldefine

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