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[/] [or1k/] [tags/] [stable/] [mp3/] [lib/] [xilinx/] [unisims/] [RAMB16_S9_S18.v] - Blame information for rev 1765

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1 266 lampret 
// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/RAMB16_S9_S18.v,v 1.1.1.1 2001-11-04 18:59:57 lampret Exp $
2 
 
3 
/*
4 
 
5 
FUNCTION        : 16x9x18 Block RAM with synchronous write capability
6 
 
7 
*/
8 
 
9 
`timescale  100 ps / 10 ps
10 
 
11 
`celldefine
12 
 
13 
module RAMB16_S9_S18 (DOA, DOPA, DOB, DOPB, ADDRA, CLKA, DIA, DIPA, ENA, SSRA, WEA, ADDRB, CLKB, DIB, DIPB, ENB, SSRB, WEB);
14 
    parameter cds_action = "ignore";
15 
    parameter INIT_A = 9'h0;
16 
    parameter INIT_B = 18'h0;
17 
    parameter SRVAL_A = 9'h0;
18 
    parameter SRVAL_B = 18'h0;
19 
    parameter WRITE_MODE_A = "WRITE_FIRST";
20 
    parameter WRITE_MODE_B = "WRITE_FIRST";
21 
 
22 
    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
23 
    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
24 
    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
25 
    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
26 
    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
27 
    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
31 
    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
32 
    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
41 
    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
43 
    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
44 
    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
46 
    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
47 
    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
48 
    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
49 
    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
50 
    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
51 
    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
52 
    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
53 
    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
54 
    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
55 
    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
56 
    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
57 
    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
58 
    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
59 
    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
60 
    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
61 
    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
62 
    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
64 
    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
67 
    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
69 
    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
71 
    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
80 
    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
81 
    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
82 
    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
83 
    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
84 
    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
85 
    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
87 
    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
88 
    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
89 
    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
90 
    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
91 
    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
92 
    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
93 
    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
94 
 
95 
    output [7:0] DOA;
96 
    output [0:0] DOPA;
97 
    reg [7:0] doa_out;
98 
    reg [0:0] dopa_out;
99 
    wire doa_out0, doa_out1, doa_out2, doa_out3, doa_out4, doa_out5, doa_out6, doa_out7;
100 
    wire dopa0_out;
101 
 
102 
    input [10:0] ADDRA;
103 
    input [7:0] DIA;
104 
    input [0:0] DIPA;
105 
    input ENA, CLKA, WEA, SSRA;
106 
 
107 
    output [15:0] DOB;
108 
    output [1:0] DOPB;
109 
    reg [15:0] dob_out;
110 
    reg [1:0] dopb_out;
111 
    wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15;
112 
    wire dopb0_out, dopb1_out;
113 
 
114 
    input [9:0] ADDRB;
115 
    input [15:0] DIB;
116 
    input [1:0] DIPB;
117 
    input ENB, CLKB, WEB, SSRB;
118 
 
119 
    reg [18431:0] mem;
120 
    reg [8:0] count;
121 
    reg [1:0] wr_mode_a, wr_mode_b;
122 
 
123 
    reg [5:0] ci, cj;
124 
    reg [5:0] dmi, dmj, dni, dnj, doi, doj, dai, daj, dbi, dbj, dci, dcj, ddi, ddj;
125 
    reg [5:0] pmi, pmj, pni, pnj, poi, poj, pai, paj, pbi, pbj, pci, pcj, pdi, pdj;
126 
 
127 
    wire [10:0] addra_int;
128 
    wire [7:0] dia_int;
129 
    wire [0:0] dipa_int;
130 
    wire ena_int, clka_int, wea_int, ssra_int;
131 
    wire [9:0] addrb_int;
132 
    wire [15:0] dib_int;
133 
    wire [1:0] dipb_int;
134 
    wire enb_int, clkb_int, web_int, ssrb_int;
135 
 
136 
    reg recovery_a, recovery_b;
137 
    reg address_collision;
138 
 
139 
    wire clka_enable = ena_int && wea_int && enb_int && address_collision;
140 
    wire clkb_enable = enb_int && web_int && ena_int && address_collision;
141 
    wire collision = clka_enable || clkb_enable;
142 
 
143 
    tri0 GSR = glbl.GSR;
144 
 
145 
    always @(GSR)
146 
        if (GSR) begin
147 
            assign doa_out = INIT_A[7:0];
148 
            assign dopa_out = INIT_A[8:8];
149 
            assign dob_out = INIT_B[15:0];
150 
            assign dopb_out = INIT_B[17:16];
151 
        end
152 
        else begin
153 
            deassign doa_out;
154 
            deassign dopa_out;
155 
            deassign dob_out;
156 
            deassign dopb_out;
157 
        end
158 
 
159 
    buf b_doa_out0 (doa_out0, doa_out[0]);
160 
    buf b_doa_out1 (doa_out1, doa_out[1]);
161 
    buf b_doa_out2 (doa_out2, doa_out[2]);
162 
    buf b_doa_out3 (doa_out3, doa_out[3]);
163 
    buf b_doa_out4 (doa_out4, doa_out[4]);
164 
    buf b_doa_out5 (doa_out5, doa_out[5]);
165 
    buf b_doa_out6 (doa_out6, doa_out[6]);
166 
    buf b_doa_out7 (doa_out7, doa_out[7]);
167 
    buf b_dopa_out0 (dopa_out0, dopa_out[0]);
168 
    buf b_dob_out0 (dob_out0, dob_out[0]);
169 
    buf b_dob_out1 (dob_out1, dob_out[1]);
170 
    buf b_dob_out2 (dob_out2, dob_out[2]);
171 
    buf b_dob_out3 (dob_out3, dob_out[3]);
172 
    buf b_dob_out4 (dob_out4, dob_out[4]);
173 
    buf b_dob_out5 (dob_out5, dob_out[5]);
174 
    buf b_dob_out6 (dob_out6, dob_out[6]);
175 
    buf b_dob_out7 (dob_out7, dob_out[7]);
176 
    buf b_dob_out8 (dob_out8, dob_out[8]);
177 
    buf b_dob_out9 (dob_out9, dob_out[9]);
178 
    buf b_dob_out10 (dob_out10, dob_out[10]);
179 
    buf b_dob_out11 (dob_out11, dob_out[11]);
180 
    buf b_dob_out12 (dob_out12, dob_out[12]);
181 
    buf b_dob_out13 (dob_out13, dob_out[13]);
182 
    buf b_dob_out14 (dob_out14, dob_out[14]);
183 
    buf b_dob_out15 (dob_out15, dob_out[15]);
184 
    buf b_dopb_out0 (dopb_out0, dopb_out[0]);
185 
    buf b_dopb_out1 (dopb_out1, dopb_out[1]);
186 
 
187 
    buf b_doa0 (DOA[0], doa_out0);
188 
    buf b_doa1 (DOA[1], doa_out1);
189 
    buf b_doa2 (DOA[2], doa_out2);
190 
    buf b_doa3 (DOA[3], doa_out3);
191 
    buf b_doa4 (DOA[4], doa_out4);
192 
    buf b_doa5 (DOA[5], doa_out5);
193 
    buf b_doa6 (DOA[6], doa_out6);
194 
    buf b_doa7 (DOA[7], doa_out7);
195 
    buf b_dopa0 (DOPA[0], dopa_out0);
196 
    buf b_dob0 (DOB[0], dob_out0);
197 
    buf b_dob1 (DOB[1], dob_out1);
198 
    buf b_dob2 (DOB[2], dob_out2);
199 
    buf b_dob3 (DOB[3], dob_out3);
200 
    buf b_dob4 (DOB[4], dob_out4);
201 
    buf b_dob5 (DOB[5], dob_out5);
202 
    buf b_dob6 (DOB[6], dob_out6);
203 
    buf b_dob7 (DOB[7], dob_out7);
204 
    buf b_dob8 (DOB[8], dob_out8);
205 
    buf b_dob9 (DOB[9], dob_out9);
206 
    buf b_dob10 (DOB[10], dob_out10);
207 
    buf b_dob11 (DOB[11], dob_out11);
208 
    buf b_dob12 (DOB[12], dob_out12);
209 
    buf b_dob13 (DOB[13], dob_out13);
210 
    buf b_dob14 (DOB[14], dob_out14);
211 
    buf b_dob15 (DOB[15], dob_out15);
212 
    buf b_dopb0 (DOPB[0], dopb_out0);
213 
    buf b_dopb1 (DOPB[1], dopb_out1);
214 
 
215 
    buf b_addra_0 (addra_int[0], ADDRA[0]);
216 
    buf b_addra_1 (addra_int[1], ADDRA[1]);
217 
    buf b_addra_2 (addra_int[2], ADDRA[2]);
218 
    buf b_addra_3 (addra_int[3], ADDRA[3]);
219 
    buf b_addra_4 (addra_int[4], ADDRA[4]);
220 
    buf b_addra_5 (addra_int[5], ADDRA[5]);
221 
    buf b_addra_6 (addra_int[6], ADDRA[6]);
222 
    buf b_addra_7 (addra_int[7], ADDRA[7]);
223 
    buf b_addra_8 (addra_int[8], ADDRA[8]);
224 
    buf b_addra_9 (addra_int[9], ADDRA[9]);
225 
    buf b_addra_10 (addra_int[10], ADDRA[10]);
226 
    buf b_dia_0 (dia_int[0], DIA[0]);
227 
    buf b_dia_1 (dia_int[1], DIA[1]);
228 
    buf b_dia_2 (dia_int[2], DIA[2]);
229 
    buf b_dia_3 (dia_int[3], DIA[3]);
230 
    buf b_dia_4 (dia_int[4], DIA[4]);
231 
    buf b_dia_5 (dia_int[5], DIA[5]);
232 
    buf b_dia_6 (dia_int[6], DIA[6]);
233 
    buf b_dia_7 (dia_int[7], DIA[7]);
234 
    buf b_dipa_0 (dipa_int[0], DIPA[0]);
235 
    buf b_ena (ena_int, ENA);
236 
    buf b_clka (clka_int, CLKA);
237 
    buf b_ssra (ssra_int, SSRA);
238 
    buf b_wea (wea_int, WEA);
239 
    buf b_addrb_0 (addrb_int[0], ADDRB[0]);
240 
    buf b_addrb_1 (addrb_int[1], ADDRB[1]);
241 
    buf b_addrb_2 (addrb_int[2], ADDRB[2]);
242 
    buf b_addrb_3 (addrb_int[3], ADDRB[3]);
243 
    buf b_addrb_4 (addrb_int[4], ADDRB[4]);
244 
    buf b_addrb_5 (addrb_int[5], ADDRB[5]);
245 
    buf b_addrb_6 (addrb_int[6], ADDRB[6]);
246 
    buf b_addrb_7 (addrb_int[7], ADDRB[7]);
247 
    buf b_addrb_8 (addrb_int[8], ADDRB[8]);
248 
    buf b_addrb_9 (addrb_int[9], ADDRB[9]);
249 
    buf b_dib_0 (dib_int[0], DIB[0]);
250 
    buf b_dib_1 (dib_int[1], DIB[1]);
251 
    buf b_dib_2 (dib_int[2], DIB[2]);
252 
    buf b_dib_3 (dib_int[3], DIB[3]);
253 
    buf b_dib_4 (dib_int[4], DIB[4]);
254 
    buf b_dib_5 (dib_int[5], DIB[5]);
255 
    buf b_dib_6 (dib_int[6], DIB[6]);
256 
    buf b_dib_7 (dib_int[7], DIB[7]);
257 
    buf b_dib_8 (dib_int[8], DIB[8]);
258 
    buf b_dib_9 (dib_int[9], DIB[9]);
259 
    buf b_dib_10 (dib_int[10], DIB[10]);
260 
    buf b_dib_11 (dib_int[11], DIB[11]);
261 
    buf b_dib_12 (dib_int[12], DIB[12]);
262 
    buf b_dib_13 (dib_int[13], DIB[13]);
263 
    buf b_dib_14 (dib_int[14], DIB[14]);
264 
    buf b_dib_15 (dib_int[15], DIB[15]);
265 
    buf b_dipb_0 (dipb_int[0], DIPB[0]);
266 
    buf b_dipb_1 (dipb_int[1], DIPB[1]);
267 
    buf b_enb (enb_int, ENB);
268 
    buf b_clkb (clkb_int, CLKB);
269 
    buf b_ssrb (ssrb_int, SSRB);
270 
    buf b_web (web_int, WEB);
271 
 
272 
    initial begin
273 
        for (count = 0; count < 256; count = count + 1) begin
274 
            mem[count]            <= INIT_00[count];
275 
            mem[256 * 1 + count]  <= INIT_01[count];
276 
            mem[256 * 2 + count]  <= INIT_02[count];
277 
            mem[256 * 3 + count]  <= INIT_03[count];
278 
            mem[256 * 4 + count]  <= INIT_04[count];
279 
            mem[256 * 5 + count]  <= INIT_05[count];
280 
            mem[256 * 6 + count]  <= INIT_06[count];
281 
            mem[256 * 7 + count]  <= INIT_07[count];
282 
            mem[256 * 8 + count]  <= INIT_08[count];
283 
            mem[256 * 9 + count]  <= INIT_09[count];
284 
            mem[256 * 10 + count] <= INIT_0A[count];
285 
            mem[256 * 11 + count] <= INIT_0B[count];
286 
            mem[256 * 12 + count] <= INIT_0C[count];
287 
            mem[256 * 13 + count] <= INIT_0D[count];
288 
            mem[256 * 14 + count] <= INIT_0E[count];
289 
            mem[256 * 15 + count] <= INIT_0F[count];
290 
            mem[256 * 16 + count] <= INIT_10[count];
291 
            mem[256 * 17 + count] <= INIT_11[count];
292 
            mem[256 * 18 + count] <= INIT_12[count];
293 
            mem[256 * 19 + count] <= INIT_13[count];
294 
            mem[256 * 20 + count] <= INIT_14[count];
295 
            mem[256 * 21 + count] <= INIT_15[count];
296 
            mem[256 * 22 + count] <= INIT_16[count];
297 
            mem[256 * 23 + count] <= INIT_17[count];
298 
            mem[256 * 24 + count] <= INIT_18[count];
299 
            mem[256 * 25 + count] <= INIT_19[count];
300 
            mem[256 * 26 + count] <= INIT_1A[count];
301 
            mem[256 * 27 + count] <= INIT_1B[count];
302 
            mem[256 * 28 + count] <= INIT_1C[count];
303 
            mem[256 * 29 + count] <= INIT_1D[count];
304 
            mem[256 * 30 + count] <= INIT_1E[count];
305 
            mem[256 * 31 + count] <= INIT_1F[count];
306 
            mem[256 * 32 + count] <= INIT_20[count];
307 
            mem[256 * 33 + count] <= INIT_21[count];
308 
            mem[256 * 34 + count] <= INIT_22[count];
309 
            mem[256 * 35 + count] <= INIT_23[count];
310 
            mem[256 * 36 + count] <= INIT_24[count];
311 
            mem[256 * 37 + count] <= INIT_25[count];
312 
            mem[256 * 38 + count] <= INIT_26[count];
313 
            mem[256 * 39 + count] <= INIT_27[count];
314 
            mem[256 * 40 + count] <= INIT_28[count];
315 
            mem[256 * 41 + count] <= INIT_29[count];
316 
            mem[256 * 42 + count] <= INIT_2A[count];
317 
            mem[256 * 43 + count] <= INIT_2B[count];
318 
            mem[256 * 44 + count] <= INIT_2C[count];
319 
            mem[256 * 45 + count] <= INIT_2D[count];
320 
            mem[256 * 46 + count] <= INIT_2E[count];
321 
            mem[256 * 47 + count] <= INIT_2F[count];
322 
            mem[256 * 48 + count] <= INIT_30[count];
323 
            mem[256 * 49 + count] <= INIT_31[count];
324 
            mem[256 * 50 + count] <= INIT_32[count];
325 
            mem[256 * 51 + count] <= INIT_33[count];
326 
            mem[256 * 52 + count] <= INIT_34[count];
327 
            mem[256 * 53 + count] <= INIT_35[count];
328 
            mem[256 * 54 + count] <= INIT_36[count];
329 
            mem[256 * 55 + count] <= INIT_37[count];
330 
            mem[256 * 56 + count] <= INIT_38[count];
331 
            mem[256 * 57 + count] <= INIT_39[count];
332 
            mem[256 * 58 + count] <= INIT_3A[count];
333 
            mem[256 * 59 + count] <= INIT_3B[count];
334 
            mem[256 * 60 + count] <= INIT_3C[count];
335 
            mem[256 * 61 + count] <= INIT_3D[count];
336 
            mem[256 * 62 + count] <= INIT_3E[count];
337 
            mem[256 * 63 + count] <= INIT_3F[count];
338 
            mem[256 * 64 + count] <= INITP_00[count];
339 
            mem[256 * 65 + count] <= INITP_01[count];
340 
            mem[256 * 66 + count] <= INITP_02[count];
341 
            mem[256 * 67 + count] <= INITP_03[count];
342 
            mem[256 * 68 + count] <= INITP_04[count];
343 
            mem[256 * 69 + count] <= INITP_05[count];
344 
            mem[256 * 70 + count] <= INITP_06[count];
345 
            mem[256 * 71 + count] <= INITP_07[count];
346 
        end
347 
    end
348 
 
349 
    always @(addra_int or addrb_int) begin
350 
        address_collision <= 1'b0;
351 
        for (ci = 0; ci < 8; ci = ci + 1) begin
352 
            for (cj = 0; cj < 16; cj = cj + 1) begin
353 
                if ((addra_int * 8 + ci) == (addrb_int * 16 + cj)) begin
354 
                    address_collision <= 1'b1;
355 
                end
356 
            end
357 
        end
358 
    end
359 
 
360 
    // Data
361 
    always @(posedge recovery_a or posedge recovery_b) begin
362 
        if (((wr_mode_a == 2'b01) && (wr_mode_b == 2'b01)) ||
363 
            ((wr_mode_a != 2'b01) && (wr_mode_b != 2'b01))) begin
364 
            if (wea_int == 1 && web_int == 1) begin
365 
                for (dmi = 0; dmi < 8; dmi = dmi + 1) begin
366 
                    for (dmj = 0; dmj < 16; dmj = dmj + 1) begin
367 
                        if ((addra_int * 8 + dmi) == (addrb_int * 16 + dmj)) begin
368 
                            mem[addra_int * 8 + dmi] <= 1'bX;
369 
                        end
370 
                    end
371 
                end
372 
            end
373 
        end
374 
        recovery_a <= 0;
375 
        recovery_b <= 0;
376 
    end
377 
 
378 
    always @(posedge recovery_a or posedge recovery_b) begin
379 
        if ((wr_mode_a == 2'b01) && (wr_mode_b != 2'b01)) begin
380 
            if (wea_int == 1 && web_int == 1) begin
381 
                for (dni = 0; dni < 8; dni = dni + 1) begin
382 
                    for (dnj = 0; dnj < 16; dnj = dnj + 1) begin
383 
                        if ((addra_int * 8 + dni) == (addrb_int * 16 + dnj)) begin
384 
                            mem[addra_int * 8 + dni] <= dia_int[dni];
385 
                        end
386 
                    end
387 
                end
388 
            end
389 
        end
390 
    end
391 
 
392 
    always @(posedge recovery_a or posedge recovery_b) begin
393 
        if ((wr_mode_a != 2'b01) && (wr_mode_b == 2'b01)) begin
394 
            if (wea_int == 1 && web_int == 1) begin
395 
                for (doi = 0; doi < 8; doi = doi + 1) begin
396 
                    for (doj = 0; doj < 16; doj = doj + 1) begin
397 
                        if ((addra_int * 8 + doi) == (addrb_int * 16 + doj)) begin
398 
                            mem[addrb_int * 16 + doj] <= dib_int[doj];
399 
                        end
400 
                    end
401 
                end
402 
            end
403 
        end
404 
    end
405 
 
406 
    always @(posedge recovery_a or posedge recovery_b) begin
407 
        if ((wr_mode_b == 2'b00) || (wr_mode_b == 2'b10)) begin
408 
            if ((wea_int == 0) && (web_int == 1) && (ssra_int == 0)) begin
409 
                for (dai = 0; dai < 8; dai = dai + 1) begin
410 
                    for (daj = 0; daj < 16; daj = daj + 1) begin
411 
                        if ((addra_int * 8 + dai) == (addrb_int * 16 + daj)) begin
412 
                            doa_out[dai] <= 1'bX;
413 
                        end
414 
                    end
415 
                end
416 
            end
417 
        end
418 
    end
419 
 
420 
    always @(posedge recovery_a or posedge recovery_b) begin
421 
        if ((wr_mode_a == 2'b00) || (wr_mode_a == 2'b10)) begin
422 
            if ((wea_int == 1) && (web_int == 0) && (ssrb_int == 0)) begin
423 
                for (dbi = 0; dbi < 8; dbi = dbi + 1) begin
424 
                    for (dbj = 0; dbj < 16; dbj = dbj + 1) begin
425 
                        if ((addra_int * 8 + dbi) == (addrb_int * 16 + dbj)) begin
426 
                            dob_out[dbj] <= 1'bX;
427 
                        end
428 
                    end
429 
                end
430 
            end
431 
        end
432 
    end
433 
 
434 
    always @(posedge recovery_a or posedge recovery_b) begin
435 
        if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) ||
436 
            (wr_mode_b == 2'b10) ||
437 
            ((wr_mode_a == 2'b01) && (wr_mode_b == 2'b00))) begin
438 
            if ((wea_int == 1) && (web_int == 1) && (ssra_int == 0)) begin
439 
                for (dci = 0; dci < 8; dci = dci + 1) begin
440 
                    for (dcj = 0; dcj < 16; dcj = dcj + 1) begin
441 
                        if ((addra_int * 8 + dci) == (addrb_int * 16 + dcj)) begin
442 
                            doa_out[dci] <= 1'bX;
443 
                        end
444 
                    end
445 
                end
446 
            end
447 
        end
448 
    end
449 
 
450 
    always @(posedge recovery_a or posedge recovery_b) begin
451 
        if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) ||
452 
            (wr_mode_a == 2'b10) ||
453 
            ((wr_mode_a == 2'b00) && (wr_mode_b == 2'b01))) begin
454 
            if ((wea_int == 1) && (web_int == 1) && (ssrb_int == 0)) begin
455 
                for (ddi = 0; ddi < 8; ddi = ddi + 1) begin
456 
                    for (ddj = 0; ddj < 16; ddj = ddj + 1) begin
457 
                        if ((addra_int * 8 + ddi) == (addrb_int * 16 + ddj)) begin
458 
                            dob_out[ddj] <= 1'bX;
459 
                        end
460 
                    end
461 
                end
462 
            end
463 
        end
464 
    end
465 
 
466 
    // Parity
467 
    always @(posedge recovery_a or posedge recovery_b) begin
468 
        if (((wr_mode_a == 2'b01) && (wr_mode_b == 2'b01)) ||
469 
            ((wr_mode_a != 2'b01) && (wr_mode_b != 2'b01))) begin
470 
            if (wea_int == 1 && web_int == 1) begin
471 
                for (pmi = 0; pmi < 1; pmi = pmi + 1) begin
472 
                    for (pmj = 0; pmj < 2; pmj = pmj + 1) begin
473 
                        if ((addra_int * 1 + pmi) == (addrb_int * 2 + pmj)) begin
474 
                            mem[16384 + addra_int * 1 + pmi] <= 1'bX;
475 
                        end
476 
                    end
477 
                end
478 
            end
479 
        end
480 
        recovery_a <= 0;
481 
        recovery_b <= 0;
482 
    end
483 
 
484 
    always @(posedge recovery_a or posedge recovery_b) begin
485 
        if ((wr_mode_a == 2'b01) && (wr_mode_b != 2'b01)) begin
486 
            if (wea_int == 1 && web_int == 1) begin
487 
                for (pni = 0; pni < 1; pni = pni + 1) begin
488 
                    for (pnj = 0; pnj < 2; pnj = pnj + 1) begin
489 
                        if ((addra_int * 1 + pni) == (addrb_int * 2 + pnj)) begin
490 
                            mem[16384 + addra_int * 1 + pni] <= dipa_int[pni];
491 
                        end
492 
                    end
493 
                end
494 
            end
495 
        end
496 
    end
497 
 
498 
    always @(posedge recovery_a or posedge recovery_b) begin
499 
        if ((wr_mode_a != 2'b01) && (wr_mode_b == 2'b01)) begin
500 
            if (wea_int == 1 && web_int == 1) begin
501 
                for (poi = 0; poi < 1; poi = poi + 1) begin
502 
                    for (poj = 0; poj < 2; poj = poj + 1) begin
503 
                        if ((addra_int * 1 + poi) == (addrb_int * 2 + poj)) begin
504 
                            mem[16384 + addrb_int * 2 + poj] <= dipb_int[poj];
505 
                        end
506 
                    end
507 
                end
508 
            end
509 
        end
510 
    end
511 
 
512 
    always @(posedge recovery_a or posedge recovery_b) begin
513 
        if ((wr_mode_b == 2'b00) || (wr_mode_b == 2'b10)) begin
514 
            if ((wea_int == 0) && (web_int == 1) && (ssra_int == 0)) begin
515 
                for (pai = 0; pai < 1; pai = pai + 1) begin
516 
                    for (paj = 0; paj < 2; paj = paj + 1) begin
517 
                        if ((addra_int * 1 + pai) == (addrb_int * 2 + paj)) begin
518 
                            dopa_out[pai] <= 1'bX;
519 
                        end
520 
                    end
521 
                end
522 
            end
523 
        end
524 
    end
525 
 
526 
    always @(posedge recovery_a or posedge recovery_b) begin
527 
        if ((wr_mode_a == 2'b00) || (wr_mode_a == 2'b10)) begin
528 
            if ((wea_int == 1) && (web_int == 0) && (ssrb_int == 0)) begin
529 
                for (pbi = 0; pbi < 1; pbi = pbi + 1) begin
530 
                    for (pbj = 0; pbj < 2; pbj = pbj + 1) begin
531 
                        if ((addra_int * 1 + pbi) == (addrb_int * 2 + pbj)) begin
532 
                            dopb_out[pbj] <= 1'bX;
533 
                        end
534 
                    end
535 
                end
536 
            end
537 
        end
538 
    end
539 
 
540 
    always @(posedge recovery_a or posedge recovery_b) begin
541 
        if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) ||
542 
            (wr_mode_b == 2'b10) ||
543 
            ((wr_mode_a == 2'b01) && (wr_mode_b == 2'b00))) begin
544 
            if ((wea_int == 1) && (web_int == 1) && (ssra_int == 0)) begin
545 
                for (pci = 0; pci < 1; pci = pci + 1) begin
546 
                    for (pcj = 0; pcj < 2; pcj = pcj + 1) begin
547 
                        if ((addra_int * 1 + pci) == (addrb_int * 2 + pcj)) begin
548 
                            dopa_out[pci] <= 1'bX;
549 
                        end
550 
                    end
551 
                end
552 
            end
553 
        end
554 
    end
555 
 
556 
    always @(posedge recovery_a or posedge recovery_b) begin
557 
        if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) ||
558 
            (wr_mode_a == 2'b10) ||
559 
            ((wr_mode_a == 2'b00) && (wr_mode_b == 2'b01))) begin
560 
            if ((wea_int == 1) && (web_int == 1) && (ssrb_int == 0)) begin
561 
                for (pdi = 0; pdi < 1; pdi = pdi + 1) begin
562 
                    for (pdj = 0; pdj < 2; pdj = pdj + 1) begin
563 
                        if ((addra_int * 1 + pdi) == (addrb_int * 2 + pdj)) begin
564 
                            dopb_out[pdj] <= 1'bX;
565 
                        end
566 
                    end
567 
                end
568 
            end
569 
        end
570 
    end
571 
 
572 
    initial begin
573 
        case (WRITE_MODE_A)
574 
            "WRITE_FIRST" : wr_mode_a <= 2'b00;
575 
            "READ_FIRST"  : wr_mode_a <= 2'b01;
576 
            "NO_CHANGE"   : wr_mode_a <= 2'b10;
577 
            default       : begin
578 
                                $display("Error : WRITE_MODE_A = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
579 
                                $finish;
580 
                            end
581 
        endcase
582 
    end
583 
 
584 
    initial begin
585 
        case (WRITE_MODE_B)
586 
            "WRITE_FIRST" : wr_mode_b <= 2'b00;
587 
            "READ_FIRST"  : wr_mode_b <= 2'b01;
588 
            "NO_CHANGE"   : wr_mode_b <= 2'b10;
589 
            default       : begin
590 
                                $display("Error : WRITE_MODE_B = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
591 
                                $finish;
592 
                            end
593 
        endcase
594 
    end
595 
 
596 
    // Port A
597 
    always @(posedge clka_int) begin
598 
        if (ena_int == 1'b1) begin
599 
            if (ssra_int == 1'b1) begin
600 
                doa_out[0] <= SRVAL_A[0];
601 
                doa_out[1] <= SRVAL_A[1];
602 
                doa_out[2] <= SRVAL_A[2];
603 
                doa_out[3] <= SRVAL_A[3];
604 
                doa_out[4] <= SRVAL_A[4];
605 
                doa_out[5] <= SRVAL_A[5];
606 
                doa_out[6] <= SRVAL_A[6];
607 
                doa_out[7] <= SRVAL_A[7];
608 
                dopa_out[0] <= SRVAL_A[8];
609 
            end
610 
            else begin
611 
                if (wea_int == 1'b1) begin
612 
                    if (wr_mode_a == 2'b00) begin
613 
                        doa_out[0] <= dia_int[0];
614 
                        doa_out[1] <= dia_int[1];
615 
                        doa_out[2] <= dia_int[2];
616 
                        doa_out[3] <= dia_int[3];
617 
                        doa_out[4] <= dia_int[4];
618 
                        doa_out[5] <= dia_int[5];
619 
                        doa_out[6] <= dia_int[6];
620 
                        doa_out[7] <= dia_int[7];
621 
                        dopa_out[0] <= dipa_int[0];
622 
                    end
623 
                    else if (wr_mode_a == 2'b01) begin
624 
                        doa_out[0] <= mem[addra_int * 8 + 0];
625 
                        doa_out[1] <= mem[addra_int * 8 + 1];
626 
                        doa_out[2] <= mem[addra_int * 8 + 2];
627 
                        doa_out[3] <= mem[addra_int * 8 + 3];
628 
                        doa_out[4] <= mem[addra_int * 8 + 4];
629 
                        doa_out[5] <= mem[addra_int * 8 + 5];
630 
                        doa_out[6] <= mem[addra_int * 8 + 6];
631 
                        doa_out[7] <= mem[addra_int * 8 + 7];
632 
                        dopa_out[0] <= mem[16384 + addra_int * 1 + 0];
633 
                    end
634 
                    else begin
635 
                        doa_out[0] <= doa_out[0];
636 
                        doa_out[1] <= doa_out[1];
637 
                        doa_out[2] <= doa_out[2];
638 
                        doa_out[3] <= doa_out[3];
639 
                        doa_out[4] <= doa_out[4];
640 
                        doa_out[5] <= doa_out[5];
641 
                        doa_out[6] <= doa_out[6];
642 
                        doa_out[7] <= doa_out[7];
643 
                        dopa_out[0] <= dopa_out[0];
644 
                    end
645 
                end
646 
                else begin
647 
                    doa_out[0] <= mem[addra_int * 8 + 0];
648 
                    doa_out[1] <= mem[addra_int * 8 + 1];
649 
                    doa_out[2] <= mem[addra_int * 8 + 2];
650 
                    doa_out[3] <= mem[addra_int * 8 + 3];
651 
                    doa_out[4] <= mem[addra_int * 8 + 4];
652 
                    doa_out[5] <= mem[addra_int * 8 + 5];
653 
                    doa_out[6] <= mem[addra_int * 8 + 6];
654 
                    doa_out[7] <= mem[addra_int * 8 + 7];
655 
                    dopa_out[0] <= mem[16384 + addra_int * 1 + 0];
656 
                end
657 
            end
658 
        end
659 
    end
660 
 
661 
    always @(posedge clka_int) begin
662 
        if (ena_int == 1'b1 && wea_int == 1'b1) begin
663 
            mem[addra_int * 8 + 0] <= dia_int[0];
664 
            mem[addra_int * 8 + 1] <= dia_int[1];
665 
            mem[addra_int * 8 + 2] <= dia_int[2];
666 
            mem[addra_int * 8 + 3] <= dia_int[3];
667 
            mem[addra_int * 8 + 4] <= dia_int[4];
668 
            mem[addra_int * 8 + 5] <= dia_int[5];
669 
            mem[addra_int * 8 + 6] <= dia_int[6];
670 
            mem[addra_int * 8 + 7] <= dia_int[7];
671 
            mem[16384 + addra_int * 1 + 0] <= dipa_int[0];
672 
        end
673 
    end
674 
 
675 
    // Port B
676 
    always @(posedge clkb_int) begin
677 
        if (enb_int == 1'b1) begin
678 
            if (ssrb_int == 1'b1) begin
679 
                dob_out[0] <= SRVAL_B[0];
680 
                dob_out[1] <= SRVAL_B[1];
681 
                dob_out[2] <= SRVAL_B[2];
682 
                dob_out[3] <= SRVAL_B[3];
683 
                dob_out[4] <= SRVAL_B[4];
684 
                dob_out[5] <= SRVAL_B[5];
685 
                dob_out[6] <= SRVAL_B[6];
686 
                dob_out[7] <= SRVAL_B[7];
687 
                dob_out[8] <= SRVAL_B[8];
688 
                dob_out[9] <= SRVAL_B[9];
689 
                dob_out[10] <= SRVAL_B[10];
690 
                dob_out[11] <= SRVAL_B[11];
691 
                dob_out[12] <= SRVAL_B[12];
692 
                dob_out[13] <= SRVAL_B[13];
693 
                dob_out[14] <= SRVAL_B[14];
694 
                dob_out[15] <= SRVAL_B[15];
695 
                dopb_out[0] <= SRVAL_B[16];
696 
                dopb_out[1] <= SRVAL_B[17];
697 
            end
698 
            else begin
699 
                if (web_int == 1'b1) begin
700 
                    if (wr_mode_b == 2'b00) begin
701 
                        dob_out[0] <= dib_int[0];
702 
                        dob_out[1] <= dib_int[1];
703 
                        dob_out[2] <= dib_int[2];
704 
                        dob_out[3] <= dib_int[3];
705 
                        dob_out[4] <= dib_int[4];
706 
                        dob_out[5] <= dib_int[5];
707 
                        dob_out[6] <= dib_int[6];
708 
                        dob_out[7] <= dib_int[7];
709 
                        dob_out[8] <= dib_int[8];
710 
                        dob_out[9] <= dib_int[9];
711 
                        dob_out[10] <= dib_int[10];
712 
                        dob_out[11] <= dib_int[11];
713 
                        dob_out[12] <= dib_int[12];
714 
                        dob_out[13] <= dib_int[13];
715 
                        dob_out[14] <= dib_int[14];
716 
                        dob_out[15] <= dib_int[15];
717 
                        dopb_out[0] <= dipb_int[0];
718 
                        dopb_out[1] <= dipb_int[1];
719 
                    end
720 
                    else if (wr_mode_b == 2'b01) begin
721 
                        dob_out[0] <= mem[addrb_int * 16 + 0];
722 
                        dob_out[1] <= mem[addrb_int * 16 + 1];
723 
                        dob_out[2] <= mem[addrb_int * 16 + 2];
724 
                        dob_out[3] <= mem[addrb_int * 16 + 3];
725 
                        dob_out[4] <= mem[addrb_int * 16 + 4];
726 
                        dob_out[5] <= mem[addrb_int * 16 + 5];
727 
                        dob_out[6] <= mem[addrb_int * 16 + 6];
728 
                        dob_out[7] <= mem[addrb_int * 16 + 7];
729 
                        dob_out[8] <= mem[addrb_int * 16 + 8];
730 
                        dob_out[9] <= mem[addrb_int * 16 + 9];
731 
                        dob_out[10] <= mem[addrb_int * 16 + 10];
732 
                        dob_out[11] <= mem[addrb_int * 16 + 11];
733 
                        dob_out[12] <= mem[addrb_int * 16 + 12];
734 
                        dob_out[13] <= mem[addrb_int * 16 + 13];
735 
                        dob_out[14] <= mem[addrb_int * 16 + 14];
736 
                        dob_out[15] <= mem[addrb_int * 16 + 15];
737 
                        dopb_out[0] <= mem[16384 + addrb_int * 2 + 0];
738 
                        dopb_out[1] <= mem[16384 + addrb_int * 2 + 1];
739 
                    end
740 
                    else begin
741 
                        dob_out[0] <= dob_out[0];
742 
                        dob_out[1] <= dob_out[1];
743 
                        dob_out[2] <= dob_out[2];
744 
                        dob_out[3] <= dob_out[3];
745 
                        dob_out[4] <= dob_out[4];
746 
                        dob_out[5] <= dob_out[5];
747 
                        dob_out[6] <= dob_out[6];
748 
                        dob_out[7] <= dob_out[7];
749 
                        dob_out[8] <= dob_out[8];
750 
                        dob_out[9] <= dob_out[9];
751 
                        dob_out[10] <= dob_out[10];
752 
                        dob_out[11] <= dob_out[11];
753 
                        dob_out[12] <= dob_out[12];
754 
                        dob_out[13] <= dob_out[13];
755 
                        dob_out[14] <= dob_out[14];
756 
                        dob_out[15] <= dob_out[15];
757 
                        dopb_out[0] <= dopb_out[0];
758 
                        dopb_out[1] <= dopb_out[1];
759 
                    end
760 
                end
761 
                else begin
762 
                    dob_out[0] <= mem[addrb_int * 16 + 0];
763 
                    dob_out[1] <= mem[addrb_int * 16 + 1];
764 
                    dob_out[2] <= mem[addrb_int * 16 + 2];
765 
                    dob_out[3] <= mem[addrb_int * 16 + 3];
766 
                    dob_out[4] <= mem[addrb_int * 16 + 4];
767 
                    dob_out[5] <= mem[addrb_int * 16 + 5];
768 
                    dob_out[6] <= mem[addrb_int * 16 + 6];
769 
                    dob_out[7] <= mem[addrb_int * 16 + 7];
770 
                    dob_out[8] <= mem[addrb_int * 16 + 8];
771 
                    dob_out[9] <= mem[addrb_int * 16 + 9];
772 
                    dob_out[10] <= mem[addrb_int * 16 + 10];
773 
                    dob_out[11] <= mem[addrb_int * 16 + 11];
774 
                    dob_out[12] <= mem[addrb_int * 16 + 12];
775 
                    dob_out[13] <= mem[addrb_int * 16 + 13];
776 
                    dob_out[14] <= mem[addrb_int * 16 + 14];
777 
                    dob_out[15] <= mem[addrb_int * 16 + 15];
778 
                    dopb_out[0] <= mem[16384 + addrb_int * 2 + 0];
779 
                    dopb_out[1] <= mem[16384 + addrb_int * 2 + 1];
780 
                end
781 
            end
782 
        end
783 
    end
784 
 
785 
    always @(posedge clkb_int) begin
786 
        if (enb_int == 1'b1 && web_int == 1'b1) begin
787 
            mem[addrb_int * 16 + 0] <= dib_int[0];
788 
            mem[addrb_int * 16 + 1] <= dib_int[1];
789 
            mem[addrb_int * 16 + 2] <= dib_int[2];
790 
            mem[addrb_int * 16 + 3] <= dib_int[3];
791 
            mem[addrb_int * 16 + 4] <= dib_int[4];
792 
            mem[addrb_int * 16 + 5] <= dib_int[5];
793 
            mem[addrb_int * 16 + 6] <= dib_int[6];
794 
            mem[addrb_int * 16 + 7] <= dib_int[7];
795 
            mem[addrb_int * 16 + 8] <= dib_int[8];
796 
            mem[addrb_int * 16 + 9] <= dib_int[9];
797 
            mem[addrb_int * 16 + 10] <= dib_int[10];
798 
            mem[addrb_int * 16 + 11] <= dib_int[11];
799 
            mem[addrb_int * 16 + 12] <= dib_int[12];
800 
            mem[addrb_int * 16 + 13] <= dib_int[13];
801 
            mem[addrb_int * 16 + 14] <= dib_int[14];
802 
            mem[addrb_int * 16 + 15] <= dib_int[15];
803 
            mem[16384 + addrb_int * 2 + 0] <= dipb_int[0];
804 
            mem[16384 + addrb_int * 2 + 1] <= dipb_int[1];
805 
        end
806 
    end
807 
 
808 
    specify
809 
        (CLKA *> DOA) = (1, 1);
810 
        (CLKA *> DOPA) = (1, 1);
811 
        (CLKB *> DOB) = (1, 1);
812 
        (CLKB *> DOPB) = (1, 1);
813 
        $recovery (posedge CLKB, posedge CLKA &&& collision, 1, recovery_b);
814 
        $recovery (posedge CLKA, posedge CLKB &&& collision, 1, recovery_a);
815 
    endspecify
816 
 
817 
endmodule
818 
 
819 
`endcelldefine

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