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// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/RAMB4_S4.v,v 1.1.1.1 2001-11-04 18:59:59 lampret Exp $
 
/*
 
FUNCTION        : 4x4 Block RAM with synchronous write capability
 
*/
 
`timescale  100 ps / 10 ps
 
`celldefine
 
module RAMB4_S4 (DO, ADDR, DI, EN, CLK, WE, RST);
 
    parameter cds_action = "ignore";
 
    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 
    output [3:0] DO;
    reg d0_out, d1_out, d2_out, d3_out;
 
    input [9:0] ADDR;
    input [3:0] DI;
    input EN, CLK, WE, RST;
 
    reg [4095:0] mem;
    reg [8:0] count;
 
    wire [9:0] addr_int;
    wire [3:0] di_int;
    wire en_int, clk_int, we_int, rst_int;
 
    tri0 GSR = glbl.GSR;
 
    always @(GSR)
        if (GSR)
            begin
                assign d0_out = 0;
                assign d1_out = 0;
                assign d2_out = 0;
                assign d3_out = 0;
            end
        else
            begin
                deassign d0_out;
                deassign d1_out;
                deassign d2_out;
                deassign d3_out;
            end
 
    buf b_do_out0 (DO[0], d0_out);
    buf b_do_out1 (DO[1], d1_out);
    buf b_do_out2 (DO[2], d2_out);
    buf b_do_out3 (DO[3], d3_out);
    buf b_addr_0 (addr_int[0], ADDR[0]);
    buf b_addr_1 (addr_int[1], ADDR[1]);
    buf b_addr_2 (addr_int[2], ADDR[2]);
    buf b_addr_3 (addr_int[3], ADDR[3]);
    buf b_addr_4 (addr_int[4], ADDR[4]);
    buf b_addr_5 (addr_int[5], ADDR[5]);
    buf b_addr_6 (addr_int[6], ADDR[6]);
    buf b_addr_7 (addr_int[7], ADDR[7]);
    buf b_addr_8 (addr_int[8], ADDR[8]);
    buf b_addr_9 (addr_int[9], ADDR[9]);
    buf b_di_0 (di_int[0], DI[0]);
    buf b_di_1 (di_int[1], DI[1]);
    buf b_di_2 (di_int[2], DI[2]);
    buf b_di_3 (di_int[3], DI[3]);
    buf b_en (en_int, EN);
    buf b_clk (clk_int, CLK);
    buf b_we (we_int, WE);
    buf b_rst (rst_int, RST);
 
    initial
    begin
        for (count = 0; count < 256; count = count + 1)
        begin
            mem[count]            <= INIT_00[count];
            mem[256 * 1 + count]  <= INIT_01[count];
            mem[256 * 2 + count]  <= INIT_02[count];
            mem[256 * 3 + count]  <= INIT_03[count];
            mem[256 * 4 + count]  <= INIT_04[count];
            mem[256 * 5 + count]  <= INIT_05[count];
            mem[256 * 6 + count]  <= INIT_06[count];
            mem[256 * 7 + count]  <= INIT_07[count];
            mem[256 * 8 + count]  <= INIT_08[count];
            mem[256 * 9 + count]  <= INIT_09[count];
            mem[256 * 10 + count] <= INIT_0A[count];
            mem[256 * 11 + count] <= INIT_0B[count];
            mem[256 * 12 + count] <= INIT_0C[count];
            mem[256 * 13 + count] <= INIT_0D[count];
            mem[256 * 14 + count] <= INIT_0E[count];
            mem[256 * 15 + count] <= INIT_0F[count];
        end
    end
 
    always @(posedge clk_int)
    begin
        if (en_int == 1'b1)
            if (rst_int == 1'b1)
                begin
                    d0_out <= 0;
                    d1_out <= 0;
                    d2_out <= 0;
                    d3_out <= 0;
                end
            else
                if (we_int == 1'b1)
                    begin
                        d0_out <= di_int[0];
                        d1_out <= di_int[1];
                        d2_out <= di_int[2];
                        d3_out <= di_int[3];
                    end
                else
                    begin
                        d0_out <= mem[addr_int * 4];
                        d1_out <= mem[addr_int * 4 + 1];
                        d2_out <= mem[addr_int * 4 + 2];
                        d3_out <= mem[addr_int * 4 + 3];
                    end
    end
 
    always @(posedge clk_int)
    begin
        if (en_int == 1'b1 && we_int == 1'b1)
            begin
                mem[addr_int * 4] <= di_int[0];
                mem[addr_int * 4 + 1] <= di_int[1];
                mem[addr_int * 4 + 2] <= di_int[2];
                mem[addr_int * 4 + 3] <= di_int[3];
            end
    end
 
    specify
        (CLK => DO) = (1, 1);
    endspecify
 
endmodule
 
`endcelldefine

Line No.	Rev	Author	Line
1	266	lampret	`// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/RAMB4_S4.v,v 1.1.1.1 2001-11-04 18:59:59 lampret Exp $`
2
3			`/*`
4
5			`FUNCTION : 4x4 Block RAM with synchronous write capability`
6
7			`*/`
8
9			`timescale 100 ps / 10 ps
10
11			`celldefine
12
13			`module RAMB4_S4 (DO, ADDR, DI, EN, CLK, WE, RST);`
14
15			`parameter cds_action = "ignore";`
16
17			`parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
18			`parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
19			`parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
20			`parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
21			`parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
22			`parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
23			`parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
24			`parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
25			`parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
26			`parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
27			`parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
28			`parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
29			`parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
30			`parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
31			`parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
32			`parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
33
34			`output [3:0] DO;`
35			`reg d0_out, d1_out, d2_out, d3_out;`
36
37			`input [9:0] ADDR;`
38			`input [3:0] DI;`
39			`input EN, CLK, WE, RST;`
40
41			`reg [4095:0] mem;`
42			`reg [8:0] count;`
43
44			`wire [9:0] addr_int;`
45			`wire [3:0] di_int;`
46			`wire en_int, clk_int, we_int, rst_int;`
47
48			`tri0 GSR = glbl.GSR;`
49
50			`always @(GSR)`
51			`if (GSR)`
52			`begin`
53			`assign d0_out = 0;`
54			`assign d1_out = 0;`
55			`assign d2_out = 0;`
56			`assign d3_out = 0;`
57			`end`
58			`else`
59			`begin`
60			`deassign d0_out;`
61			`deassign d1_out;`
62			`deassign d2_out;`
63			`deassign d3_out;`
64			`end`
65
66			`buf b_do_out0 (DO[0], d0_out);`
67			`buf b_do_out1 (DO[1], d1_out);`
68			`buf b_do_out2 (DO[2], d2_out);`
69			`buf b_do_out3 (DO[3], d3_out);`
70			`buf b_addr_0 (addr_int[0], ADDR[0]);`
71			`buf b_addr_1 (addr_int[1], ADDR[1]);`
72			`buf b_addr_2 (addr_int[2], ADDR[2]);`
73			`buf b_addr_3 (addr_int[3], ADDR[3]);`
74			`buf b_addr_4 (addr_int[4], ADDR[4]);`
75			`buf b_addr_5 (addr_int[5], ADDR[5]);`
76			`buf b_addr_6 (addr_int[6], ADDR[6]);`
77			`buf b_addr_7 (addr_int[7], ADDR[7]);`
78			`buf b_addr_8 (addr_int[8], ADDR[8]);`
79			`buf b_addr_9 (addr_int[9], ADDR[9]);`
80			`buf b_di_0 (di_int[0], DI[0]);`
81			`buf b_di_1 (di_int[1], DI[1]);`
82			`buf b_di_2 (di_int[2], DI[2]);`
83			`buf b_di_3 (di_int[3], DI[3]);`
84			`buf b_en (en_int, EN);`
85			`buf b_clk (clk_int, CLK);`
86			`buf b_we (we_int, WE);`
87			`buf b_rst (rst_int, RST);`
88
89			`initial`
90			`begin`
91			`for (count = 0; count < 256; count = count + 1)`
92			`begin`
93			`mem[count] <= INIT_00[count];`
94			`mem[256 * 1 + count] <= INIT_01[count];`
95			`mem[256 * 2 + count] <= INIT_02[count];`
96			`mem[256 * 3 + count] <= INIT_03[count];`
97			`mem[256 * 4 + count] <= INIT_04[count];`
98			`mem[256 * 5 + count] <= INIT_05[count];`
99			`mem[256 * 6 + count] <= INIT_06[count];`
100			`mem[256 * 7 + count] <= INIT_07[count];`
101			`mem[256 * 8 + count] <= INIT_08[count];`
102			`mem[256 * 9 + count] <= INIT_09[count];`
103			`mem[256 * 10 + count] <= INIT_0A[count];`
104			`mem[256 * 11 + count] <= INIT_0B[count];`
105			`mem[256 * 12 + count] <= INIT_0C[count];`
106			`mem[256 * 13 + count] <= INIT_0D[count];`
107			`mem[256 * 14 + count] <= INIT_0E[count];`
108			`mem[256 * 15 + count] <= INIT_0F[count];`
109			`end`
110			`end`
111
112			`always @(posedge clk_int)`
113			`begin`
114			`if (en_int == 1'b1)`
115			`if (rst_int == 1'b1)`
116			`begin`
117			`d0_out <= 0;`
118			`d1_out <= 0;`
119			`d2_out <= 0;`
120			`d3_out <= 0;`
121			`end`
122			`else`
123			`if (we_int == 1'b1)`
124			`begin`
125			`d0_out <= di_int[0];`
126			`d1_out <= di_int[1];`
127			`d2_out <= di_int[2];`
128			`d3_out <= di_int[3];`
129			`end`
130			`else`
131			`begin`
132			`d0_out <= mem[addr_int * 4];`
133			`d1_out <= mem[addr_int * 4 + 1];`
134			`d2_out <= mem[addr_int * 4 + 2];`
135			`d3_out <= mem[addr_int * 4 + 3];`
136			`end`
137			`end`
138
139			`always @(posedge clk_int)`
140			`begin`
141			`if (en_int == 1'b1 && we_int == 1'b1)`
142			`begin`
143			`mem[addr_int * 4] <= di_int[0];`
144			`mem[addr_int * 4 + 1] <= di_int[1];`
145			`mem[addr_int * 4 + 2] <= di_int[2];`
146			`mem[addr_int * 4 + 3] <= di_int[3];`
147			`end`
148			`end`
149
150			`specify`
151			`(CLK => DO) = (1, 1);`
152			`endspecify`
153
154			`endmodule`
155
156			`endcelldefine

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[/] [or1k/] [tags/] [stable/] [mp3/] [lib/] [xilinx/] [unisims/] [RAMB4_S4.v] - Blame information for rev 1765