OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable/] [mp3/] [rtl/] [verilog/] [xfpga_defines.v] - Blame information for rev 1765

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 266 lampret
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  MP3 demo Definitions                                        ////
4
////                                                              ////
5
////  This file is part of the MP3 demo application               ////
6
////  http://www.opencores.org/cores/or1k/mp3/                    ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  DEfine target technology etc. Right now FIFOs are available ////
10
////  only for Xilinx Virtex FPGAs. (TARGET_VIRTEX)               ////
11
////                                                              ////
12
////  To Do:                                                      ////
13
////   - nothing really                                           ////
14
////                                                              ////
15
////  Author(s):                                                  ////
16
////      - Damjan Lampret, damjan.lampret@opencores.org          ////
17
////                                                              ////
18
//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20
//// Copyright (C) 2001 Authors                                   ////
21
////                                                              ////
22
//// This source file may be used and distributed without         ////
23
//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
26
////                                                              ////
27
//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
32
////                                                              ////
33
//// This source is distributed in the hope that it will be       ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
38
////                                                              ////
39
//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44
//
45
// CVS Revision History
46
//
47
// $Log: not supported by cvs2svn $
48
 
49
//
50
// Define to target to Xilinx Virtex
51
//
52
`define TARGET_VIRTEX

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.