| 1 |
282 |
simons |
+libext+.v
|
| 2 |
|
|
+access+wr
|
| 3 |
|
|
+overwrite
|
| 4 |
|
|
+mess
|
| 5 |
|
|
+max_err_count+2
|
| 6 |
|
|
|
| 7 |
|
|
+incdir+../../../bench/verilog
|
| 8 |
|
|
../../../bench/verilog/xess_top.v
|
| 9 |
|
|
../../../bench/verilog/or1200_monitor.v
|
| 10 |
|
|
../../../bench/verilog/sram_init.v
|
| 11 |
|
|
../../../bench/verilog/dbg_comm.v
|
| 12 |
|
|
|
| 13 |
|
|
../../../bench/models/512Kx8.v
|
| 14 |
|
|
../../../bench/models/vga_model.v
|
| 15 |
|
|
../../../bench/models/codec_model.v
|
| 16 |
|
|
+incdir+../../../bench/models/28f016s3
|
| 17 |
|
|
../../../bench/models/28f016s3/bwsvff.v
|
| 18 |
|
|
|
| 19 |
|
|
+incdir+../../../rtl/verilog
|
| 20 |
|
|
../../../rtl/verilog/xfpga_top.v
|
| 21 |
|
|
../../../rtl/verilog/tcop_top.v
|
| 22 |
|
|
../../../rtl/verilog/audio/audio_codec_if.v
|
| 23 |
|
|
../../../rtl/verilog/audio/audio_top.v
|
| 24 |
|
|
../../../rtl/verilog/audio/audio_wb_if.v
|
| 25 |
|
|
../../../rtl/verilog/audio/fifo_4095_16.v
|
| 26 |
|
|
../../../rtl/verilog/mem_if/flash_top.v
|
| 27 |
|
|
../../../rtl/verilog/mem_if/sram_top.v
|
| 28 |
|
|
|
| 29 |
|
|
+incdir+../../../lib/xilinx/coregen/
|
| 30 |
|
|
../../../lib/xilinx/coregen/XilinxCoreLib/async_fifo_v3_0.v
|
| 31 |
|
|
../../../lib/xilinx/unisims/RAMB4_S16.v
|
| 32 |
|
|
../../../lib/xilinx/unisims/RAMB4_S4.v
|
| 33 |
|
|
../../../lib/xilinx/unisims/RAMB4_S2.v
|
| 34 |
|
|
../../../lib/xilinx/unisims/RAMB4_S16_S16.v
|
| 35 |
|
|
../../../lib/xilinx/unisims/RAM32X1D.v
|
| 36 |
|
|
../../../lib/xilinx/unisims/RAMB4_S8_S16.v
|
| 37 |
|
|
../../../lib/xilinx/unisims/IBUFG.v
|
| 38 |
|
|
../../../lib/xilinx/unisims/BUFG.v
|
| 39 |
|
|
../../../lib/xilinx/unisims/CLKDLL.v
|
| 40 |
|
|
../../../lib/xilinx/unisims/glbl.v
|
| 41 |
|
|
|
| 42 |
|
|
+incdir+../../../rtl/verilog/ssvga
|
| 43 |
|
|
../../../rtl/verilog/ssvga/crtc_iob.v
|
| 44 |
|
|
../../../rtl/verilog/ssvga/ssvga_crtc.v
|
| 45 |
|
|
../../../rtl/verilog/ssvga/ssvga_defines.v
|
| 46 |
|
|
../../../rtl/verilog/ssvga/ssvga_fifo.v
|
| 47 |
|
|
../../../rtl/verilog/ssvga/ssvga_top.v
|
| 48 |
|
|
../../../rtl/verilog/ssvga/ssvga_wbm_if.v
|
| 49 |
|
|
../../../rtl/verilog/ssvga/ssvga_wbs_if.v
|
| 50 |
|
|
|
| 51 |
|
|
|
| 52 |
|
|
+incdir+../../../rtl/verilog/or1200
|
| 53 |
|
|
../../../rtl/verilog/or1200/wb_biu.v
|
| 54 |
|
|
../../../rtl/verilog/or1200/id.v
|
| 55 |
|
|
../../../rtl/verilog/or1200/cpu.v
|
| 56 |
|
|
../../../rtl/verilog/or1200/rf.v
|
| 57 |
|
|
../../../rtl/verilog/or1200/alu.v
|
| 58 |
|
|
../../../rtl/verilog/or1200/lsu.v
|
| 59 |
|
|
../../../rtl/verilog/or1200/operandmuxes.v
|
| 60 |
|
|
../../../rtl/verilog/or1200/wbmux.v
|
| 61 |
|
|
../../../rtl/verilog/or1200/ifetch.v
|
| 62 |
|
|
../../../rtl/verilog/or1200/frz_logic.v
|
| 63 |
|
|
../../../rtl/verilog/or1200/sprs.v
|
| 64 |
|
|
../../../rtl/verilog/or1200/or1200.v
|
| 65 |
|
|
../../../rtl/verilog/or1200/pic.v
|
| 66 |
|
|
../../../rtl/verilog/or1200/pm.v
|
| 67 |
|
|
../../../rtl/verilog/or1200/tt.v
|
| 68 |
|
|
../../../rtl/verilog/or1200/except.v
|
| 69 |
|
|
../../../rtl/verilog/or1200/dc.v
|
| 70 |
|
|
../../../rtl/verilog/or1200/dc_fsm.v
|
| 71 |
|
|
../../../rtl/verilog/or1200/reg2mem.v
|
| 72 |
|
|
../../../rtl/verilog/or1200/mem2reg.v
|
| 73 |
|
|
../../../rtl/verilog/or1200/dc_tag.v
|
| 74 |
|
|
../../../rtl/verilog/or1200/dc_ram.v
|
| 75 |
|
|
../../../rtl/verilog/or1200/ic.v
|
| 76 |
|
|
../../../rtl/verilog/or1200/ic_fsm.v
|
| 77 |
|
|
../../../rtl/verilog/or1200/ic_tag.v
|
| 78 |
|
|
../../../rtl/verilog/or1200/ic_ram.v
|
| 79 |
|
|
../../../rtl/verilog/or1200/immu.v
|
| 80 |
|
|
../../../rtl/verilog/or1200/itlb.v
|
| 81 |
|
|
../../../rtl/verilog/or1200/dmmu.v
|
| 82 |
|
|
../../../rtl/verilog/or1200/dtlb.v
|
| 83 |
|
|
../../../rtl/verilog/or1200/generic_multp2_32x32.v
|
| 84 |
|
|
../../../rtl/verilog/or1200/cfgr.v
|
| 85 |
|
|
../../../rtl/verilog/or1200/du.v
|
| 86 |
|
|
../../../rtl/verilog/or1200/mult_mac.v
|
| 87 |
|
|
../../../rtl/verilog/or1200/generic_dpram_32x32.v
|
| 88 |
|
|
../../../rtl/verilog/or1200/generic_spram_2048x32.v
|
| 89 |
|
|
../../../rtl/verilog/or1200/generic_spram_2048x8.v
|
| 90 |
|
|
../../../rtl/verilog/or1200/generic_spram_512x20.v
|
| 91 |
|
|
../../../rtl/verilog/or1200/generic_spram_64x14.v
|
| 92 |
|
|
../../../rtl/verilog/or1200/generic_spram_64x21.v
|
| 93 |
|
|
../../../rtl/verilog/or1200/generic_spram_64x23.v
|
| 94 |
|
|
../../../rtl/verilog/or1200/xcv_ram32x8d.v
|
| 95 |
|
|
|
| 96 |
|
|
+incdir+../../../rtl/verilog/dbg_interface
|
| 97 |
|
|
../../../rtl/verilog/dbg_interface/dbg_crc8_d1.v
|
| 98 |
|
|
../../../rtl/verilog/dbg_interface/dbg_defines.v
|
| 99 |
|
|
../../../rtl/verilog/dbg_interface/dbg_register.v
|
| 100 |
|
|
../../../rtl/verilog/dbg_interface/dbg_registers.v
|
| 101 |
|
|
../../../rtl/verilog/dbg_interface/dbg_sync_clk1_clk2.v
|
| 102 |
|
|
../../../rtl/verilog/dbg_interface/dbg_top.v
|
| 103 |
|
|
../../../rtl/verilog/dbg_interface/dbg_trace.v
|
