OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable/] [mp3/] [sw/] [mad-xess/] [reset.S] - Blame information for rev 291

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 291 simons
        .section .reset
2
        .extern _main
3
        .extern _src_beg
4
        .extern _dst_beg
5
        .extern _dst_end
6
        .extern _main
7
        .extern _c_reset
8
 
9
_reset:
10
        l.nop
11
        l.nop
12
        l.movhi r0, 0x0
13
        l.slli  r0,r0,16
14
        l.addi  r1,r0,0x0
15
        l.addi  r2,r0,0x0
16
        l.addi  r3,r0,0x0
17
        l.addi  r4,r0,0x0
18
        l.addi  r5,r0,0x0
19
        l.addi  r6,r0,0x0
20
        l.addi  r7,r0,0x0
21
        l.addi  r8,r0,0x0
22
        l.addi  r9,r0,0x1234
23
        l.addi  r10,r0,0x0
24
        l.addi  r11,r0,0x0
25
        l.addi  r12,r0,0x0
26
        l.addi  r13,r0,0x0
27
        l.addi  r14,r0,0x0
28
        l.addi  r15,r0,0x0
29
        l.addi  r16,r0,0x0
30
        l.addi  r17,r0,0x0
31
        l.addi  r18,r0,0x0
32
        l.addi  r19,r0,0x0
33
        l.addi  r20,r0,0x0
34
        l.addi  r21,r0,0x0
35
        l.addi  r22,r0,0x0
36
        l.addi  r23,r0,0x0
37
        l.addi  r24,r0,0x0
38
        l.addi  r25,r0,0x0
39
        l.addi  r26,r0,0x0
40
        l.addi  r27,r0,0x0
41
        l.addi  r28,r0,0x0
42
        l.addi  r29,r0,0x0
43
        l.addi  r30,r0,0x0
44
        l.addi  r31,r0,0x0
45
 
46
        /* Copy form flash to sram */
47
 
48
        l.movhi r3,hi(_src_beg)
49
        l.ori   r3,r3,lo(_src_beg)
50
        l.movhi r4,hi(_dst_beg)
51
        l.ori   r4,r4,lo(_dst_beg)
52
        l.movhi r5,hi(_dst_end)
53
        l.ori   r5,r5,lo(_dst_end)
54
        l.sub   r5,r5,r4
55
        l.sfeqi r5,0
56
        l.bf    2f
57
        l.nop
58
1:      l.lwz   r6,0(r3)
59
        l.sw    0(r4),r6
60
        l.addi  r3,r3,4
61
        l.addi  r4,r4,4
62
        l.addi  r5,r5,-4
63
        l.sfgtsi r5,0
64
        l.bf    1b
65
        l.nop
66
 
67
2:
68
 
69
        /* Verify sram data */
70
/*      l.movhi r3,hi(_src_beg)
71
        l.ori   r3,r3,lo(_src_beg)
72
        l.addi  r3,r3,4
73
        l.movhi r4,hi(_dst_beg)
74
        l.ori   r4,r4,lo(_dst_beg)
75
        l.addi  r4,r4,4
76
        l.movhi r5,hi(_dst_end)
77
        l.ori   r5,r5,lo(_dst_end)
78
        l.sub   r5,r5,r4
79
        l.sfeqi r5,0
80
        l.bf    2f
81
        l.nop
82
1:      l.lwz   r6,0(r3)
83
        l.lwz   r7,0(r4)
84
        l.sfeq  r6,r7
85
        l.bnf   img_err
86
        l.nop
87
        l.addi  r3,r3,4
88
        l.addi  r4,r4,4
89
        l.addi  r5,r5,-4
90
        l.sfgtsi r5,0
91
        l.bf    1b
92
        l.nop
93
2:
94
*/
95
        l.movhi r1,hi(0x80200000)
96
        l.addi  r1,r1,lo(0x80200000)
97
        l.addi  r1,r1,-4
98
 
99
        l.movhi r2,hi(_main)
100
        l.ori   r2,r2,lo(_main)
101
        l.jr    r2
102
        l.addi  r2,r0,0
103
 
104
img_err:
105
        l.movhi r15,hi(0x80000000)
106
        l.addi  r15,r15,lo(0x80000000)
107
 
108
        l.addi  r8,r6,0
109
        l.addi  r9,r7,0
110
        l.addi  r10,r3,0
111
        l.addi  r11,r4,0
112
 
113
        l.sw    0(r15),r8
114
 
115
        l.srli  r8,r8,8
116
        l.sw    0(r15),r8
117
 
118
        l.srli  r8,r8,8
119
        l.sw    0(r15),r8
120
 
121
        l.srli  r8,r8,8
122
        l.sw    0(r15),r8
123
 
124
        l.sw    0(r15),r10
125
 
126
        l.srli  r10,r10,8
127
        l.sw    0(r15),r10
128
 
129
        l.srli  r10,r10,8
130
        l.sw    0(r15),r10
131
 
132
        l.srli  r10,r10,8
133
        l.sw    0(r15),r10
134
 
135
 
136
        l.sw    0(r15),r9
137
 
138
        l.srli  r9,r9,8
139
        l.sw    0(r15),r9
140
 
141
        l.srli  r9,r9,8
142
        l.sw    0(r15),r9
143
 
144
        l.srli  r9,r9,8
145
        l.sw    0(r15),r9
146
 
147
        l.sw    0(r15),r11
148
 
149
        l.srli  r11,r11,8
150
        l.sw    0(r15),r11
151
 
152
        l.srli  r11,r11,8
153
        l.sw    0(r15),r11
154
 
155
        l.srli  r11,r11,8
156
        l.sw    0(r15),r11
157
 
158
        l.addi  r8,r0,0xee
159
        l.sw    0(r15),r8
160
 
161
        l.j     img_err
162
        l.nop

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.