OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable/] [mp3/] [syn/] [design_compiler/] [bin/] [read_design.inc] - Blame information for rev 1765

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 268 lampret
/* Set search path for verilog include files */
2
search_path = search_path + RTL_PATH + { GATE_PATH }
3
 
4
/* Read verilog files of the RTC IP core */
5
if (TOPLEVEL == "xfpga_top") {
6
        read -f verilog tcop_top.v
7
        read -f verilog xfpga_top.v
8
 
9
        read -f verilog audio_codec_if.v
10
        read -f verilog audio_top.v
11
        read -f verilog audio_wb_if.v
12
        read -f verilog fifo_4095_16.v
13
        read -f verilog fifo_empty_16.v
14
 
15
        read -f verilog dbg_crc8_d1.v
16
        read -f verilog dbg_defines.v
17
        read -f verilog dbg_register.v
18
        read -f verilog dbg_registers.v
19
        read -f verilog dbg_sync_clk1_clk2.v
20
        read -f verilog dbg_timescale.v
21
        read -f verilog dbg_top.v
22
        read -f verilog dbg_trace.v
23
 
24
        read -f verilog flash_top.v
25
        read -f verilog sram_top.v
26
 
27
        read -f verilog alu.v
28
        read -f verilog cfgr.v
29
        read -f verilog cpu.v
30
        read -f verilog dc.v
31
        read -f verilog dc_fsm.v
32
        read -f verilog dc_ram.v
33
        read -f verilog dc_tag.v
34
        read -f verilog defines.v
35
        read -f verilog dmmu.v
36
        read -f verilog dtlb.v
37
        read -f verilog du.v
38
        read -f verilog except.v
39
        read -f verilog frz_logic.v
40
        read -f verilog generic_dpram_32x32.v
41
        read -f verilog generic_multp2_32x32.v
42
        read -f verilog generic_spram_2048x32.v
43
        read -f verilog generic_spram_2048x8.v
44
        read -f verilog generic_spram_512x19.v
45
        read -f verilog generic_spram_512x20.v
46
        read -f verilog generic_spram_64x14.v
47
        read -f verilog generic_spram_64x21.v
48
        read -f verilog generic_spram_64x23.v
49
        read -f verilog generic_spram_64x37.v
50
        read -f verilog generic_tpram_32x32.v
51
        read -f verilog ic.v
52
        read -f verilog ic_fsm.v
53
        read -f verilog ic_ram.v
54
        read -f verilog ic_tag.v
55
        read -f verilog id.v
56
        read -f verilog ifetch.v
57
        read -f verilog immu.v
58
        read -f verilog itlb.v
59
        read -f verilog lsu.v
60
        read -f verilog mem2reg.v
61
        read -f verilog mult_mac.v
62
        read -f verilog operandmuxes.v
63
        read -f verilog or1200.v
64
        read -f verilog pic.v
65
        read -f verilog pm.v
66
        read -f verilog reg2mem.v
67
        read -f verilog rf.v
68
        read -f verilog sprs.v
69
        read -f verilog tt.v
70
        read -f verilog wb_biu.v
71
        read -f verilog wbmux.v
72
 
73
        read -f verilog xcv_ram32x8d.v
74
 
75
        read -f verilog crtc_iob.v
76
        read -f verilog ssvga_crtc.v
77
        read -f verilog ssvga_defines.v
78
        read -f verilog ssvga_fifo.v
79
        read -f verilog ssvga_top.v
80
        read -f verilog ssvga_wbm_if.v
81
        read -f verilog ssvga_wbs_if.v
82
 
83
} else {
84
        echo "Non-existing top level."
85
        exit
86
}
87
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.