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[/] [or1k/] [tags/] [stable/] [mp3/] [syn/] [design_compiler/] [bin/] [set_env.inc] - Blame information for rev 392

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/* Enable Verilog HDL preprocessor */
hdlin_enable_vpp = true
 
/* Set log path */
LOG_PATH = "../log/"
 
/* Set gate-level netlist path */
GATE_PATH = "../out/"
 
/* Set RAMS_PATH */
RAMS_PATH = "../../../lib/"
 
/* Set RTL source path */
RTL_PATH = { "../../../rtl/verilog/", "../../../rtl/verilog/audio/", \
        "../../../rtl/verilog/dbg_interface/", "../../../rtl/verilog/or1200/", \
        "../../../rtl/verilog/mem_if/", "../../../rtl/verilog/ssvga/" }
 
/* Optimize adders */
synlib_model_map_effort = high
hlo_share_effort = medium

Line No.	Rev	Author	Line
1	268	lampret	`/* Enable Verilog HDL preprocessor */`
2			`hdlin_enable_vpp = true`
3
4			`/* Set log path */`
5			`LOG_PATH = "../log/"`
6
7			`/* Set gate-level netlist path */`
8			`GATE_PATH = "../out/"`
9
10			`/* Set RAMS_PATH */`
11			`RAMS_PATH = "../../../lib/"`
12
13			`/* Set RTL source path */`
14			`RTL_PATH = { "../../../rtl/verilog/", "../../../rtl/verilog/audio/", \`
15			`"../../../rtl/verilog/dbg_interface/", "../../../rtl/verilog/or1200/", \`
16			`"../../../rtl/verilog/mem_if/", "../../../rtl/verilog/ssvga/" }`
17
18			`/* Optimize adders */`
19			`synlib_model_map_effort = high`
20			`hlo_share_effort = medium`

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[/] [or1k/] [tags/] [stable/] [mp3/] [syn/] [design_compiler/] [bin/] [set_env.inc] - Blame information for rev 392