Subversion Repositories or1k

#-- Synplicity, Inc.

#-- Version 7.0 Beta3

#-- Project file G:\mp3\simon\or1k\mp3\syn\synplify\xfpga_top.prj

#-- Written on Mon Nov 05 10:27:17 2001

#add_file options

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/xfpga_top.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/xfpga_defines.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/tcop_top.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/dc_fsm.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/alu.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/cfgr.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/cpu.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/dc.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/dc_ram.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/dc_tag.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/defines.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/dmmu.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/dtlb.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/du.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/except.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/frz_logic.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/generic_dpram_32x32.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/generic_multp2_32x32.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/generic_spram_2048x32.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/generic_spram_2048x8.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/generic_spram_512x19.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/generic_spram_512x20.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/generic_spram_64x14.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/generic_spram_64x21.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/generic_spram_64x23.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/generic_spram_64x37.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/generic_tpram_32x32.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/ic.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/ic_fsm.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/ic_ram.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/ic_tag.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/id.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/ifetch.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/immu.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/itlb.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/lsu.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/mem2reg.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/mult_mac.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/operandmuxes.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/or1200.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/pic.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/pm.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/reg2mem.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/rf.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/sprs.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/tt.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/wb_biu.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/wbmux.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/or1200/xcv_ram32x8d.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/mem_if/flash_top.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/mem_if/sram_top.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/audio/audio_codec_if.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/audio/audio_top.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/audio/audio_wb_if.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/audio/fifo_4095_16.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/audio/fifo_empty_16.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/dbg_interface/dbg_crc8_d1.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/dbg_interface/dbg_defines.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/dbg_interface/dbg_register.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/dbg_interface/dbg_registers.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/dbg_interface/dbg_sync_clk1_clk2.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/dbg_interface/dbg_timescale.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/dbg_interface/dbg_top.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/dbg_interface/dbg_trace.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/dbg_interface/timescale.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/ssvga/crtc_iob.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/ssvga/ssvga_crtc.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/ssvga/ssvga_defines.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/ssvga/ssvga_fifo.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/ssvga/ssvga_top.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/ssvga/ssvga_wbm_if.v"

add_file -verilog "G:/mp3/simon/or1k/mp3/rtl/verilog/ssvga/ssvga_wbs_if.v"

add_file -verilog "$LIB/xilinx/virtex.v"

#reporting options

#implementation: "rev_1"

impl -add rev_1

#device options

set_option -technology VIRTEX

set_option -part XCV800

set_option -package HQ240

set_option -speed_grade -6

#compilation/mapping options

set_option -default_enum_encoding default

set_option -symbolic_fsm_compiler 1

set_option -resource_sharing 1

set_option -top_module "xfpga_top"

#map options

set_option -frequency 25.000

set_option -fanout_limit 100

set_option -disable_io_insertion 0

set_option -pipe 1

set_option -modular 0

set_option -retiming 1

#simulation options

set_option -write_verilog 0

set_option -write_vhdl 0

#automatic place and route (vendor) options

set_option -write_apr_constraint 1

#set result format/file last

project -result_file "rev_1/xfpga_top.edf"

set_option -include_path "G:/mp3/simon/or1k/mp3/rtl/verilog/dbg_interface/"

impl -active "rev_1"