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/* 16450.c -- Simulation of 8250/16450 serial UART
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
/* This is functional simulation of 8250/16450 UARTs. Since we RX/TX data
   via file streams, we can't simulate modem control lines coming from the
   DCE and similar details of communication with the DCE.
 
   This simulated UART device is intended for basic UART device driver
   verification. From device driver perspective this device looks like a
   regular UART but never reports and modem control lines changes (the
   only DCE responses are incoming characters from the file stream).
*/
 
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
 
#include "config.h"
 
#ifdef HAVE_INTTYPES_H
#include <inttypes.h>
#endif
 
#include "port.h"
#include "arch.h"
#include "abstract.h"
#include "16450.h"
#include "sim-config.h"
#include "pic.h"
#include "vapi.h"
#include "sched.h"
#include "channel.h"
#include "debug.h"
 
#define MIN(a,b) ((a) < (b) ? (a) : (b))
 
static struct dev_16450 uarts[MAX_UARTS];                       /* simulation info */
static struct channel * channels[MAX_UARTS] = { NULL, };        /* emulation info */
 
/* Number of clock cycles (one clock cycle is one call to the uart_clock())
   before a single character is transmitted or received. */
static unsigned long char_clks(int dll, int dlh, int lcr)
{
  float bauds_per_char = 1.;
  unsigned long char_clks = ((dlh << 8) + dll);
 
  if (lcr & UART_LCR_PARITY)
    bauds_per_char = bauds_per_char + 1.;
 
  /* stop bits 1 or two */
  if (lcr & UART_LCR_STOP)
    bauds_per_char = bauds_per_char + 2.;
  else
    if ((lcr & 0x3) != 0)
      bauds_per_char = bauds_per_char + 1.;
    else
      bauds_per_char = bauds_per_char + 1.5;
 
  bauds_per_char = bauds_per_char + (5. + (lcr & 0x3));
 
  return char_clks * bauds_per_char;
}
 
/* Set a specific UART register with value. */
void uart_write_byte(oraddr_t addr, uint32_t value)
{
  int chipsel;
 
  debug(4, "uart_write_byte(%"PRIxADDR",%02"PRIx32")\n", addr, value);
 
  for(chipsel = 0; chipsel < MAX_UARTS; chipsel++)
    if ((addr & ~(UART_ADDR_SPACE-1)) == config.uarts[chipsel].baseaddr)
      break;
  if (chipsel >= MAX_UARTS) return;
 
  if (uarts[chipsel].regs.lcr & UART_LCR_DLAB) {
    switch (addr % UART_ADDR_SPACE) {
      case UART_DLL:
        uarts[chipsel].regs.dll = value;
        uarts[chipsel].char_clks = char_clks(uarts[chipsel].regs.dll, uarts[chipsel].regs.dlh, uarts[chipsel].regs.lcr);
        return;
      case UART_DLH:
        uarts[chipsel].regs.dlh = value;
        return;
    }
  }
 
  switch (addr % UART_ADDR_SPACE) {
    case UART_TXBUF:
      if (uarts[chipsel].istat.txbuf_full < uarts[chipsel].fifo_len) {
        uarts[chipsel].istat.txbuf_full++;
        uarts[chipsel].regs.txbuf[uarts[chipsel].istat.txbuf_head] = value;
        uarts[chipsel].istat.txbuf_head = (uarts[chipsel].istat.txbuf_head + 1) % uarts[chipsel].fifo_len;
      } else
        uarts[chipsel].regs.txbuf[uarts[chipsel].istat.txbuf_head] = value;
 
      uarts[chipsel].regs.lsr &= ~(UART_LSR_TXSERE | UART_LSR_TXBUFE);
      if (uarts[chipsel].regs.iir & UART_IIR_THRI)
        uarts[chipsel].istat.thre_int = 0;
      break;
    case UART_FCR:
      uarts[chipsel].regs.fcr = value & UART_VALID_FCR;
      if (uarts[chipsel].fifo_len == 1 && (value & UART_FCR_FIE)
       || uarts[chipsel].fifo_len != 1 && !(value & UART_FCR_FIE))
        value |= UART_FCR_RRXFI | UART_FCR_RTXFI;
      uarts[chipsel].fifo_len = (value & UART_FCR_FIE) ? 16 : 1;
      if (value & UART_FCR_RTXFI) {
        uarts[chipsel].istat.txbuf_head = uarts[chipsel].istat.txbuf_tail = 0;
        uarts[chipsel].istat.txbuf_full = 0;
        uarts[chipsel].regs.lsr |= UART_LSR_TXBUFE;
 
        // For FIFO-mode only, THRE interrupt is set when THR and FIFO are empty
        uarts[chipsel].istat.thre_int = (uarts[chipsel].fifo_len == 16);
      }
      if (value & UART_FCR_RRXFI) {
        uarts[chipsel].istat.rxbuf_head = uarts[chipsel].istat.rxbuf_tail = 0;
        uarts[chipsel].istat.rxbuf_full = 0;
        uarts[chipsel].regs.lsr &= ~UART_LSR_RDRDY;
      }
      break;
    case UART_IER:
      uarts[chipsel].regs.ier = value & UART_VALID_IER;
      break;
    case UART_LCR:
      uarts[chipsel].regs.lcr = value & UART_VALID_LCR;
      uarts[chipsel].char_clks = char_clks(uarts[chipsel].regs.dll, uarts[chipsel].regs.dlh, uarts[chipsel].regs.lcr);
      break;
    case UART_MCR:
      uarts[chipsel].regs.mcr = value & UART_VALID_MCR;
      break;
    case UART_SCR:
      uarts[chipsel].regs.scr = value;
      break;
    default:
      debug(1, "write out of range (addr %x)\n", addr);
  }
}
 
/* Read a specific UART register. */
uint32_t uart_read_byte(oraddr_t addr)
{
  uint8_t value = 0;
  int chipsel;
 
  debug(4, "uart_read_byte(%"PRIxADDR")", addr);
 
  for(chipsel = 0; chipsel < MAX_UARTS; chipsel++)
    if ((addr & ~(UART_ADDR_SPACE-1)) == config.uarts[chipsel].baseaddr)
      break;
 
  if (chipsel >= MAX_UARTS)
    return 0;
 
  if (uarts[chipsel].regs.lcr & UART_LCR_DLAB) {
    switch (addr % UART_ADDR_SPACE) {
      case UART_DLL:
        value = uarts[chipsel].regs.dll;
        debug(4, "= %"PRIx8"\n", value);
        return value;
      case UART_DLH:
        value = uarts[chipsel].regs.dlh;
        debug(4, "= %"PRIx8"\n", value);
        return value;
    }
  }
 
  switch (addr % UART_ADDR_SPACE) {
    case UART_RXBUF:
      { /* Print out FIFO for debugging */
        int i;
        debug(4, "(%i/%i,%i,%i:", uarts[chipsel].istat.rxbuf_full, uarts[chipsel].fifo_len,
                  uarts[chipsel].istat.rxbuf_head, uarts[chipsel].istat.rxbuf_tail);
        for (i = 0; i < uarts[chipsel].istat.rxbuf_full; i++)
          debug(4, "%02x ", uarts[chipsel].regs.rxbuf[(uarts[chipsel].istat.rxbuf_tail + i) % uarts[chipsel].fifo_len]);
        debug(4, ")");
      }
      if (uarts[chipsel].istat.rxbuf_full) {
        value = uarts[chipsel].regs.rxbuf[uarts[chipsel].istat.rxbuf_tail];
        uarts[chipsel].istat.rxbuf_tail = (uarts[chipsel].istat.rxbuf_tail + 1) % uarts[chipsel].fifo_len;
        uarts[chipsel].istat.rxbuf_full--;
      }
 
      if (uarts[chipsel].istat.rxbuf_full)
        uarts[chipsel].regs.lsr |= UART_LSR_RDRDY;
      else
        uarts[chipsel].regs.lsr &= ~UART_LSR_RDRDY;
 
      uarts[chipsel].istat.timeout_count = 0;
      break;
    case UART_IER:
      value = uarts[chipsel].regs.ier & UART_VALID_IER;
      break;
    case UART_IIR:
      value = (uarts[chipsel].regs.iir & UART_VALID_IIR) | 0xc0;
      if (uarts[chipsel].regs.iir & UART_IIR_THRI)
        uarts[chipsel].istat.thre_int = 0;
      break;
    case UART_LCR:
      value = uarts[chipsel].regs.lcr & UART_VALID_LCR;
      break;
    case UART_MCR:
      value = 0;
      break;
    case UART_LSR:
      value = uarts[chipsel].regs.lsr & UART_VALID_LSR;
      uarts[chipsel].regs.lsr &=
        ~(UART_LSR_OVRRUN | UART_LSR_BREAK | UART_LSR_PARITY
         | UART_LSR_FRAME | UART_LSR_RXERR);
      break;
    case UART_MSR:
      value = uarts[chipsel].regs.msr & UART_VALID_MSR;
      uarts[chipsel].regs.msr = 0;
      break;
    case UART_SCR:
      value = uarts[chipsel].regs.scr;
      break;
    default:
      debug(1, "read out of range (addr %"PRIxADDR")\n", addr);
  }
  debug(4, " = %"PRIx8"\n", value);
  return value;
}
 
/* Function that handles incoming VAPI data.  */
void uart_vapi_read (unsigned long id, unsigned long data)
{
  int uart;
  debug(4, "UART: id %08lx, data %08lx\n", id, data);
  uart = id & VAPI_DEVICE_ID;
  uarts[uart].vapi_buf[uarts[uart].vapi_buf_head_ptr] = data;
  uarts[uart].vapi_buf_head_ptr = (uarts[uart].vapi_buf_head_ptr + 1) % UART_VAPI_BUF_LEN;
  if (uarts[uart].vapi_buf_tail_ptr == uarts[uart].vapi_buf_head_ptr) {
    fprintf (stderr, "FATAL: uart VAPI buffer to small.\n");
    exit (1);
  }
}
 
static void send_char (int uart, int bits_send)
{
  PRINTF ("%c", (char)uarts[uart].iregs.txser);
  debug(4, "TX \'%c\' via UART%d...\n", (char)uarts[uart].iregs.txser, uart);
  if (uarts[uart].regs.mcr & UART_MCR_LOOP)
    uarts[uart].iregs.loopback = uarts[uart].iregs.txser;
  else {
    /* Send to either VAPI or to file */
    if (config.uarts[uart].vapi_id) {
      int par, pe, fe, nbits;
      int j, data;
      unsigned long packet = 0;
 
      nbits = MIN (bits_send, (uarts[uart].regs.lcr & UART_LCR_WLEN8) + 5);
      /* Encode a packet */
      packet = uarts[uart].iregs.txser & ((1 << nbits) - 1);
 
      /* Calculate parity */
      for (j = 0, par = 0; j < nbits; j++)
        par ^= (packet >> j) & 1;
 
      if (uarts[uart].regs.lcr & UART_LCR_PARITY) {
        if (uarts[uart].regs.lcr & UART_LCR_SPAR) {
          packet |= 1 << nbits;
        } else {
          if (uarts[uart].regs.lcr & UART_LCR_EPAR)
            packet |= par << nbits;
          else
            packet |= (par ^ 1) << nbits;
        }
        nbits++;
      }
      packet |= 1 << (nbits++);
      if (uarts[uart].regs.lcr & UART_LCR_STOP)
        packet |= 1 << (nbits++);
 
      /* Decode a packet */
      nbits = (uarts[uart].vapi.lcr & UART_LCR_WLEN8) + 5;
      data = packet & ((1 << nbits) - 1);
 
      /* Calculate parity, including parity bit */
      for (j = 0, par = 0; j < nbits + 1; j++)
        par ^= (packet >> j) & 1;
 
      if (uarts[uart].vapi.lcr & UART_LCR_PARITY) {
        if (uarts[uart].vapi.lcr & UART_LCR_SPAR) {
          pe = !((packet >> nbits) & 1);
        } else {
          if (uarts[uart].vapi.lcr & UART_LCR_EPAR)
            pe = par != 0;
          else
            pe = par != 1;
        }
        nbits++;
      } else
        pe = 0;
 
      fe = ((packet >> (nbits++)) & 1) ^ 1;
      if (uarts[uart].vapi.lcr & UART_LCR_STOP)
        fe |= ((packet >> (nbits++)) & 1) ^ 1;
 
      debug (4, "lcr vapi %02x, uart %02x\n", uarts[uart].vapi.lcr, uarts[uart].regs.lcr);
      data |= (uarts[uart].vapi.lcr << 8) | (pe << 16) | (fe << 17) | (uarts[uart].vapi.lcr << 8);
      PRINTF ("vapi_send (%08lx, %08x)\n", config.uarts[uart].vapi_id, data);
      debug (4, "vapi_send (%08lx, %08x)\n", config.uarts[uart].vapi_id, data);
      vapi_send (config.uarts[uart].vapi_id, data);
    } else {
      char buffer[1] = { uarts[uart].iregs.txser & 0xFF };
      channel_write(channels[uart], buffer, 1);
    }
  }
  uarts[uart].istat.txser_full = 0;
  uarts[uart].istat.txser_clks = 0;
}
 
/* Adds a character to the FIFO */
 
void uart_add_char (int uart, int ch)
{
  if (uarts[uart].istat.rxbuf_full + 1 > uarts[uart].fifo_len)
    uarts[uart].regs.lsr |= UART_LSR_OVRRUN | UART_LSR_RXERR;
  else {
    debug(4, "add %02x\n", ch);
    uarts[uart].regs.rxbuf[uarts[uart].istat.rxbuf_head] = ch;
    uarts[uart].istat.rxbuf_head = (uarts[uart].istat.rxbuf_head + 1) % uarts[uart].fifo_len;
    uarts[uart].istat.rxbuf_full++;
  }
  uarts[uart].regs.lsr |= UART_LSR_RDRDY;
  uarts[uart].istat.timeout_count = 0;
}
 
/* Simulation hook. Must be called every clock cycle to simulate all UART
   devices. It does internal functional UART simulation. */
void uart_clock16 (int i)
{
  int retval;
 
  /* Schedule for later */
  SCHED_ADD (uart_clock16, i, runtime.sim.cycles + UART_CLOCK_DIVIDER);
 
  /* If VAPI is not selected, UART communicates with two file streams;
     if VAPI is selected, we use VAPI streams.  */
  /* if txfs is corrupted, skip this uart. */
  if (!config.uarts[i].vapi_id && !channel_ok(channels[i])) return;
 
  if (uarts[i].vapi.next_break_cnt >= 0)
    if (--uarts[i].vapi.next_break_cnt < 0) {
      if (!(uarts[i].vapi.cur_break = uarts[i].vapi.next_break))
        uarts[i].istat.break_set = 0;
    }
 
  /***************** Transmit *****************/
  if (!uarts[i].istat.txser_full) {
//      uarts[i].regs.lsr |= UART_LSR_TXBUFE;
    if (uarts[i].istat.txbuf_full) {
      uarts[i].iregs.txser = uarts[i].regs.txbuf[uarts[i].istat.txbuf_tail];
      uarts[i].istat.txbuf_tail = (uarts[i].istat.txbuf_tail + 1) % uarts[i].fifo_len;
      uarts[i].istat.txser_full = 1;
      uarts[i].istat.txbuf_full--;
      uarts[i].regs.lsr &= ~UART_LSR_TXSERE;
 
      // When UART is in either character mode, i.e. 16450 emulation mode, or FIFO mode,
      // the THRE interrupt is raised when THR transitions from full to empty.
      if (!uarts[i].istat.txbuf_full) {
        uarts[i].istat.thre_int = 1;
        uarts[i].regs.lsr |= UART_LSR_TXBUFE;
      }
    } else {
      uarts[i].regs.lsr |= UART_LSR_TXSERE;
    }
  } else if (uarts[i].char_clks <= uarts[i].istat.txser_clks++) {
    send_char(i, (uarts[i].regs.lcr & UART_LCR_WLEN8) + 5); /* We've sent all bits */
  } else {
    /* We are still sending char here*/
 
    /* Check if we set the break bit */
    if (uarts[i].regs.lcr & UART_LCR_SBC) {
      if (!uarts[i].vapi.break_sent) {
#if 0
        /* Send broken frame */
        int nbits_sent = ((uarts[i].regs.lcr & UART_LCR_WLEN8) + 5) * (uarts[i].istat.txser_clks - 1) / uarts[i].char_clks;
        send_char(i, nbits_sent);
#endif
        /* Send one break signal */
        vapi_send (config.uarts[i].vapi_id, UART_LCR_SBC << 8);
        uarts[i].vapi.break_sent = 1;
      }
      /* mark as character was sent */
      uarts[i].istat.txser_full = 0;
      uarts[i].istat.txser_clks = 0;
    } else
      uarts[i].vapi.break_sent = 0;
 
  }
 
  /***************** Receive *****************/
 
  /* Is there a break? */
  if (uarts[i].vapi.cur_break) {
    uarts[i].vapi.cur_break_cnt++;
    if (uarts[i].vapi.cur_break_cnt > UART_BREAK_COUNT * uarts[i].vapi.char_clks) {
      if (!uarts[i].istat.break_set) {
        unsigned lsr;
        uarts[i].istat.break_set = 1;
        lsr = UART_LSR_BREAK | UART_LSR_RXERR | UART_LSR_RDRDY;
        PRINTF ("[%x]\n", uarts[i].regs.lsr);
        uarts[i].istat.rxser_full = 0;
        uarts[i].istat.rxser_clks = 0;
        uart_add_char (i, lsr << 8);
      } else
        uarts[i].vapi.cur_break_cnt = 0;
    }
    if (uarts[i].istat.rxser_full) {
      uarts[i].istat.rxser_full = 0;
      uarts[i].istat.rxser_clks = 0;
    }
  } else {
    if (uarts[i].istat.rxser_full) {
      if (uarts[i].char_clks <= uarts[i].istat.rxser_clks++) {
        /* Set unused character bits to zero and allow lsr register in fifo */
        uarts[i].iregs.rxser &= ((1 << ((uarts[i].regs.lcr & 3) + 5)) - 1) | 0xff00;
        debug(4, "Receiving 0x%02lx'%c' via UART%d...\n", uarts[i].iregs.rxser,
              (char)uarts[i].iregs.rxser, i);
        PRINTF ("%c", (char)uarts[i].iregs.rxser);
        uarts[i].istat.rxser_full = 0;
        uarts[i].istat.rxser_clks = 0;
        uart_add_char (i, uarts[i].iregs.rxser);
      }
    }
  }
 
  /* Check if there is something waiting, and put it into rxser */
  if (uarts[i].regs.mcr & UART_MCR_LOOP) {
    uarts[i].iregs.rxser = uarts[i].iregs.loopback;
    uarts[i].istat.rxser_full = 1;
  } else {
    if (!config.uarts[i].vapi_id) {
      if(uarts[i].istat.rxser_full == 0) {
        if (uarts[i].slowdown)
          uarts[i].slowdown--;
        else {
          char buffer[1];
          retval = channel_read(channels[i], buffer, 1);
          if(retval < 0)
                  perror(config.uarts[i].channel);
          else if(retval > 0) {
            uarts[i].iregs.rxser = (unsigned char)buffer[0];
            uarts[i].istat.rxser_full = 1;
          } else
            uarts[i].slowdown = UART_FGETC_SLOWDOWN;
        }
      }
    } else { /* VAPI */
      int received = 0;
      /* do not handle commands while receiving */
      if (uarts[i].istat.rxser_full) return;
      while (!received) {
        if (uarts[i].vapi_buf_head_ptr != uarts[i].vapi_buf_tail_ptr) {
          unsigned long data = uarts[i].vapi_buf[uarts[i].vapi_buf_tail_ptr];
          debug(4, "Handling: %08lx (%i,%i)\n", data, uarts[i].vapi_buf_head_ptr, uarts[i].vapi_buf_tail_ptr);
          uarts[i].vapi_buf_tail_ptr = (uarts[i].vapi_buf_tail_ptr + 1) % UART_VAPI_BUF_LEN;
          switch (data >> 24) {
            case 0x00:
              uarts[i].vapi.lcr = (data >> 8) & 0xff;
              /* Put data into rx fifo */
              uarts[i].iregs.rxser = data & 0xff;
              uarts[i].vapi.char_clks = char_clks (uarts[i].vapi.dll, uarts[i].vapi.dlh, uarts[i].vapi.lcr);
              if ((uarts[i].vapi.lcr & ~UART_LCR_SBC) != (uarts[i].regs.lcr & ~UART_LCR_SBC)
               || uarts[i].vapi.char_clks != uarts[i].char_clks
               || uarts[i].vapi.skew < -MAX_SKEW || uarts[i].vapi.skew > MAX_SKEW) {
                debug (3, "WARNING: unmatched VAPI (%02x) and uart (%02x) modes.\n",
                      uarts[i].vapi.lcr & ~UART_LCR_SBC, uarts[i].regs.lcr & ~UART_LCR_SBC);
                /* Set error bits */
                uarts[i].iregs.rxser |= (UART_LSR_FRAME | UART_LSR_RXERR) << 8;
                if (uarts[i].regs.lcr & UART_LCR_PARITY) uarts[i].iregs.rxser |= UART_LSR_PARITY << 8;
              }
              uarts[i].istat.rxser_full = 1;
              received = 1;
              break;
            case 0x01:
              uarts[i].vapi.dll = (data >> 0) & 0xff;
              uarts[i].vapi.dlh = (data >> 8) & 0xff;
              break;
            case 0x02:
              uarts[i].vapi.lcr = (data >> 8) & 0xff;
              break;
            case 0x03:
              uarts[i].vapi.skew = (signed short)(data & 0xffff);
              break;
            case 0x04:
              uarts[i].vapi.next_break_cnt = data & 0xffff;
              uarts[i].vapi.next_break = (data >> 16) & 1;
              break;
            default:
              debug (0, "WARNING: Invalid vapi command %02lx\n", data >> 24);
              break;
          }
        } else break;
      }
    }
  }
 
  /***************** Loopback *****************/
  if (uarts[i].regs.mcr & UART_MCR_LOOP) {
    debug(5, "uart_clock: Loopback\n");
    if ((uarts[i].regs.mcr & UART_MCR_AUX2) !=
        ((uarts[i].regs.msr & UART_MSR_DCD) >> 4))
      uarts[i].regs.msr |= UART_MSR_DDCD;
    if ((uarts[i].regs.mcr & UART_MCR_AUX1) <
        ((uarts[i].regs.msr & UART_MSR_RI) >> 4))
      uarts[i].regs.msr |= UART_MSR_TERI;
    if ((uarts[i].regs.mcr & UART_MCR_RTS) !=
        ((uarts[i].regs.msr & UART_MSR_CTS) >> 3))
      uarts[i].regs.msr |= UART_MSR_DCTS;
    if ((uarts[i].regs.mcr & UART_MCR_DTR) !=
        ((uarts[i].regs.msr & UART_MSR_DSR) >> 5))
      uarts[i].regs.msr |= UART_MSR_DDSR;
    uarts[i].regs.msr &= ~(UART_MSR_DCD | UART_MSR_RI
              | UART_MSR_DSR | UART_MSR_CTS);
    uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_AUX2) << 4);
    uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_AUX1) << 4);
    uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_RTS) << 3);
    uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_DTR) << 5);
  }
 
  if (uarts[i].regs.lsr & UART_LSR_RDRDY)
    uarts[i].istat.timeout_count++;
 
  /* Update LSR error bits from the ones from rx FIFO */
  if (uarts[i].istat.rxbuf_full) {
    uarts[i].regs.lsr |= uarts[i].regs.rxbuf[uarts[i].istat.rxbuf_tail] >> 8;
    /* we must delete the lsr status, so that we can clear it from lsr */
    uarts[i].regs.rxbuf[uarts[i].istat.rxbuf_tail] &= 0xff;
  }
 
  /* Interrupt detection in proper priority order. */
  uarts[i].regs.iir = UART_IIR_NO_INT;
  if (uarts[i].regs.ier & UART_IER_RLSI &&                    /* Receiver LS */
      uarts[i].regs.lsr & (UART_LSR_OVRRUN | UART_LSR_PARITY
        | UART_LSR_FRAME | UART_LSR_BREAK)) {
    uarts[i].regs.iir = UART_IIR_RLSI;
  } else if ((uarts[i].regs.ier & UART_IER_RDI)               /* RD available */
      && (uarts[i].istat.rxbuf_full >= UART_FIFO_TRIGGER(uarts[i].regs.fcr >> 6))
      && (uarts[i].regs.lsr & UART_LSR_RDRDY)) {
    uarts[i].regs.iir = UART_IIR_RDI;
  } else if ((uarts[i].regs.ier & UART_IER_RDI)               /* timeout */
      && (uarts[i].istat.timeout_count >= UART_CHAR_TIMEOUT * uarts[i].char_clks)
      && (uarts[i].istat.rxbuf_head != uarts[i].istat.rxbuf_tail)) {
    uarts[i].regs.iir = UART_IIR_CTI;
  } else if (uarts[i].regs.ier & UART_IER_THRI &&             /* Transm. empty */
      uarts[i].istat.thre_int == 1) {
    uarts[i].regs.iir = UART_IIR_THRI;
  } else if (uarts[i].regs.ier & UART_IER_MSI &&              /* Modem status */
      uarts[i].regs.msr & (UART_MSR_DCTS | UART_MSR_DDSR
        | UART_MSR_TERI | UART_MSR_DDCD)) {
    uarts[i].regs.iir = UART_IIR_MSI;
  }
  if (!(uarts[i].regs.iir & UART_IIR_NO_INT)) {
    debug (4, "uarts[i].regs.iir = %i\t", uarts[i].regs.iir);
    report_interrupt(config.uarts[i].irq);
  }
}
 
/* Reset.  It initializes all registers of all UART devices to zero values,
   (re)opens all RX/TX file streams and places devices in memory address
   space.  */
void uart_reset()
{
  int i;
  if (config.sim.verbose && config.nuarts) PRINTF("Resetting %u UART(s).\n", config.nuarts);
  memset(uarts, 0, sizeof(uarts));
 
  for(i = 0; i < config.nuarts; i++) {
    if (config.uarts[i].vapi_id) {
      if ((config.uarts[i].vapi_id & VAPI_DEVICE_ID) != i) {
        fprintf (stderr, "ERROR: Wrong vapi_id (0x%lx) for uart %i, last byte is required to be %02x; ignoring.\n", config.uarts[i].vapi_id, i, i);
        config.uarts[i].vapi_id = 0;
      } else {
        vapi_install_handler (config.uarts[i].vapi_id, uart_vapi_read);
        register_memoryarea(config.uarts[i].baseaddr, UART_ADDR_SPACE, 1, 0, uart_read_byte, uart_write_byte);
      }
    } else if (config.uarts[i].channel[0]) { /* MM: Try to create stream.  */
      if(channels[i])
        channel_close(channels[i]);
      else
        channels[i] = channel_init(config.uarts[i].channel);
      if(channel_open(channels[i]) < 0) {
        debug (0, "WARNING: UART%d has problems with channel \"%s\".\n", i, config.uarts[i].channel);
        continue;
      }
      if (config.sim.verbose)
        PRINTF("UART%d at 0x%.8lx uses ", i, config.uarts[i].baseaddr);
      register_memoryarea(config.uarts[i].baseaddr, UART_ADDR_SPACE, 1, 0, uart_read_byte, uart_write_byte);
    } else {
        debug (0, "WARNING: UART%d has no vapi nor channel specified\n", i);
        continue;
    }
 
    if (config.uarts[i].uart16550)
      uarts[i].fifo_len = 16;
    else
      uarts[i].fifo_len = 1;
 
    uarts[i].istat.rxbuf_head = uarts[i].istat.rxbuf_tail = 0;
    uarts[i].istat.txbuf_head = uarts[i].istat.txbuf_tail = 0;
 
    uarts[i].istat.break_set = 0;
    uarts[i].istat.timeout_count = 0;
 
    // For FIFO-mode only, THRE interrupt is set when both THR and FIFO are empty
    uarts[i].istat.thre_int = (uarts[i].fifo_len == 16);
 
    uarts[i].slowdown = UART_FGETC_SLOWDOWN;
 
    uarts[i].regs.lcr = UART_LCR_RESET;
    uarts[i].vapi.cur_break = uarts[i].vapi.cur_break_cnt = uarts[i].vapi.next_break = 0;
    uarts[i].vapi.next_break_cnt = -1;
    PRINTF ("%i\n", i);
    SCHED_ADD (uart_clock16, i, runtime.sim.cycles + UART_CLOCK_DIVIDER);
  }
}
 
/* Print register values on stdout. */
void uart_status()
{
  int i, j;
 
  for(i = 0; i < config.nuarts; i++) {
    if ( !config.uarts[i].baseaddr )
      continue;
    PRINTF("\nUART%d visible registers at 0x%.8lx:\n", i,
           config.uarts[i].baseaddr);
    PRINTF("RXBUF: ");
    for (j = uarts[i].istat.rxbuf_head; j != uarts[i].istat.rxbuf_tail; j = (j + 1) % uarts[i].fifo_len)
      PRINTF (" %.2x", uarts[i].regs.rxbuf[j]);
    PRINTF("TXBUF: ");
    for (j = uarts[i].istat.txbuf_head; j != uarts[i].istat.txbuf_tail; j = (j + 1) % uarts[i].fifo_len)
      PRINTF (" %.2x", uarts[i].regs.txbuf[j]);
    PRINTF("\n");
    PRINTF("DLL  : %.2x  DLH  : %.2x\n", uarts[i].regs.dll, uarts[i].regs.dlh);
    PRINTF("IER  : %.2x  IIR  : %.2x\n", uarts[i].regs.ier, uarts[i].regs.iir);
    PRINTF("LCR  : %.2x  MCR  : %.2x\n", uarts[i].regs.lcr, uarts[i].regs.mcr);
    PRINTF("LSR  : %.2x  MSR  : %.2x\n", uarts[i].regs.lsr, uarts[i].regs.msr);
    PRINTF("SCR  : %.2x\n", uarts[i].regs.scr);
 
    PRINTF("\nInternal registers (sim debug):\n");
    PRINTF("RXSER: %.2lx  TXSER: %.2lx\n", uarts[i].iregs.rxser,
           uarts[i].iregs.txser);
 
    PRINTF("\nInternal status (sim debug):\n");
    PRINTF("char_clks: %ld\n", uarts[i].char_clks);
    PRINTF("rxser_clks: %ld  txser_clks: %ld\n", uarts[i].istat.rxser_clks,
           uarts[i].istat.txser_clks);
    PRINTF("rxser: %d  txser: %d\n", uarts[i].istat.rxser_full, uarts[i].istat.txser_full);
    PRINTF("rxbuf_full: %d  txbuf_full: %d\n", uarts[i].istat.rxbuf_full, uarts[i].istat.txbuf_full);
    PRINTF("Using IRQ%i\n", config.uarts[i].irq);
    if (config.uarts[i].vapi_id)
      PRINTF ("Connected to vapi ID=%lx\n\n", config.uarts[i].vapi_id);
    /* TODO: replace by a channel_status
    else
      PRINTF("RX fs: %p  TX fs: %p\n\n", uarts[i].rxfs, uarts[i].txfs);
    */
  }
}

Line No.	Rev	Author	Line
1	31	lampret	`/* 16450.c -- Simulation of 8250/16450 serial UART`
2			`Copyright (C) 1999 Damjan Lampret, lampret@opencores.org`
3
4			`This file is part of OpenRISC 1000 Architectural Simulator.`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License as published by`
8			`the Free Software Foundation; either version 2 of the License, or`
9			`(at your option) any later version.`
10
11			`This program is distributed in the hope that it will be useful,`
12			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`GNU General Public License for more details.`
15
16			`You should have received a copy of the GNU General Public License`
17			`along with this program; if not, write to the Free Software`
18			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */`
19
20			`/* This is functional simulation of 8250/16450 UARTs. Since we RX/TX data`
21			`via file streams, we can't simulate modem control lines coming from the`
22			`DCE and similar details of communication with the DCE.`
23
24			`This simulated UART device is intended for basic UART device driver`
25			`verification. From device driver perspective this device looks like a`
26			`regular UART but never reports and modem control lines changes (the`
27			`only DCE responses are incoming characters from the file stream).`
28			`*/`
29
30			`#include <stdlib.h>`
31			`#include <stdio.h>`
32			`#include <string.h>`
33
34	1350	nogj	`#include "config.h"`
35
36			`#ifdef HAVE_INTTYPES_H`
37			`#include <inttypes.h>`
38			`#endif`
39
40			`#include "port.h"`
41			`#include "arch.h"`
42	235	erez	`#include "abstract.h"`
43	31	lampret	`#include "16450.h"`
44			`#include "sim-config.h"`
45	102	lampret	`#include "pic.h"`
46	336	markom	`#include "vapi.h"`
47	805	markom	`#include "sched.h"`
48	1073	rprescott	`#include "channel.h"`
49	1308	phoenix	`#include "debug.h"`
50	31	lampret
51	409	markom	`#define MIN(a,b) ((a) < (b) ? (a) : (b))`
52
53	1073	rprescott	`static struct dev_16450 uarts[MAX_UARTS]; /* simulation info */`
54			`static struct channel * channels[MAX_UARTS] = { NULL, }; /* emulation info */`
55	31	lampret
56			`/* Number of clock cycles (one clock cycle is one call to the uart_clock())`
57			`before a single character is transmitted or received. */`
58	355	markom	`static unsigned long char_clks(int dll, int dlh, int lcr)`
59	31	lampret	`{`
60	409	markom	`float bauds_per_char = 1.;`
61	806	markom	`unsigned long char_clks = ((dlh << 8) + dll);`
62	355	markom
63			`if (lcr & UART_LCR_PARITY)`
64			`bauds_per_char = bauds_per_char + 1.;`
65	31	lampret
66	355	markom	`/* stop bits 1 or two */`
67			`if (lcr & UART_LCR_STOP)`
68			`bauds_per_char = bauds_per_char + 2.;`
69			`else`
70			`if ((lcr & 0x3) != 0)`
71			`bauds_per_char = bauds_per_char + 1.;`
72			`else`
73			`bauds_per_char = bauds_per_char + 1.5;`
74
75			`bauds_per_char = bauds_per_char + (5. + (lcr & 0x3));`
76
77			`return char_clks * bauds_per_char;`
78	31	lampret	`}`
79
80			`/* Set a specific UART register with value. */`
81	1350	nogj	`void uart_write_byte(oraddr_t addr, uint32_t value)`
82	31	lampret	`{`
83	355	markom	`int chipsel;`
84
85	1350	nogj	`debug(4, "uart_write_byte(%"PRIxADDR",%02"PRIx32")\n", addr, value);`
86	341	markom
87	424	markom	`for(chipsel = 0; chipsel < MAX_UARTS; chipsel++)`
88	355	markom	`if ((addr & ~(UART_ADDR_SPACE-1)) == config.uarts[chipsel].baseaddr)`
89			`break;`
90	424	markom	`if (chipsel >= MAX_UARTS) return;`
91	31	lampret
92	355	markom	`if (uarts[chipsel].regs.lcr & UART_LCR_DLAB) {`
93			`switch (addr % UART_ADDR_SPACE) {`
94			`case UART_DLL:`
95			`uarts[chipsel].regs.dll = value;`
96			`uarts[chipsel].char_clks = char_clks(uarts[chipsel].regs.dll, uarts[chipsel].regs.dlh, uarts[chipsel].regs.lcr);`
97			`return;`
98			`case UART_DLH:`
99			`uarts[chipsel].regs.dlh = value;`
100			`return;`
101			`}`
102			`}`
103
104			`switch (addr % UART_ADDR_SPACE) {`
105			`case UART_TXBUF:`
106			`if (uarts[chipsel].istat.txbuf_full < uarts[chipsel].fifo_len) {`
107			`uarts[chipsel].istat.txbuf_full++;`
108			`uarts[chipsel].regs.txbuf[uarts[chipsel].istat.txbuf_head] = value;`
109			`uarts[chipsel].istat.txbuf_head = (uarts[chipsel].istat.txbuf_head + 1) % uarts[chipsel].fifo_len;`
110			`} else`
111			`uarts[chipsel].regs.txbuf[uarts[chipsel].istat.txbuf_head] = value;`
112	341	markom
113	411	markom	`uarts[chipsel].regs.lsr &= ~(UART_LSR_TXSERE \| UART_LSR_TXBUFE);`
114	1153	sfurman	`if (uarts[chipsel].regs.iir & UART_IIR_THRI)`
115			`uarts[chipsel].istat.thre_int = 0;`
116	355	markom	`break;`
117	409	markom	`case UART_FCR:`
118			`uarts[chipsel].regs.fcr = value & UART_VALID_FCR;`
119			`if (uarts[chipsel].fifo_len == 1 && (value & UART_FCR_FIE)`
120			`\|\| uarts[chipsel].fifo_len != 1 && !(value & UART_FCR_FIE))`
121			`value \|= UART_FCR_RRXFI \| UART_FCR_RTXFI;`
122			`uarts[chipsel].fifo_len = (value & UART_FCR_FIE) ? 16 : 1;`
123			`if (value & UART_FCR_RTXFI) {`
124			`uarts[chipsel].istat.txbuf_head = uarts[chipsel].istat.txbuf_tail = 0;`
125			`uarts[chipsel].istat.txbuf_full = 0;`
126	1145	sfurman	`uarts[chipsel].regs.lsr \|= UART_LSR_TXBUFE;`
127
128			`// For FIFO-mode only, THRE interrupt is set when THR and FIFO are empty`
129			`uarts[chipsel].istat.thre_int = (uarts[chipsel].fifo_len == 16);`
130	409	markom	`}`
131			`if (value & UART_FCR_RRXFI) {`
132			`uarts[chipsel].istat.rxbuf_head = uarts[chipsel].istat.rxbuf_tail = 0;`
133			`uarts[chipsel].istat.rxbuf_full = 0;`
134	411	markom	`uarts[chipsel].regs.lsr &= ~UART_LSR_RDRDY;`
135	409	markom	`}`
136			`break;`
137	355	markom	`case UART_IER:`
138			`uarts[chipsel].regs.ier = value & UART_VALID_IER;`
139			`break;`
140			`case UART_LCR:`
141			`uarts[chipsel].regs.lcr = value & UART_VALID_LCR;`
142	409	markom	`uarts[chipsel].char_clks = char_clks(uarts[chipsel].regs.dll, uarts[chipsel].regs.dlh, uarts[chipsel].regs.lcr);`
143	355	markom	`break;`
144			`case UART_MCR:`
145			`uarts[chipsel].regs.mcr = value & UART_VALID_MCR;`
146			`break;`
147			`case UART_SCR:`
148			`uarts[chipsel].regs.scr = value;`
149			`break;`
150			`default:`
151			`debug(1, "write out of range (addr %x)\n", addr);`
152			`}`
153	31	lampret	`}`
154
155			`/* Read a specific UART register. */`
156	1350	nogj	`uint32_t uart_read_byte(oraddr_t addr)`
157	31	lampret	`{`
158	1350	nogj	`uint8_t value = 0;`
159	355	markom	`int chipsel;`
160
161	1350	nogj	`debug(4, "uart_read_byte(%"PRIxADDR")", addr);`
162	355	markom
163	424	markom	`for(chipsel = 0; chipsel < MAX_UARTS; chipsel++)`
164	355	markom	`if ((addr & ~(UART_ADDR_SPACE-1)) == config.uarts[chipsel].baseaddr)`
165			`break;`
166	31	lampret
167	424	markom	`if (chipsel >= MAX_UARTS)`
168	355	markom	`return 0;`
169	344	markom
170	355	markom	`if (uarts[chipsel].regs.lcr & UART_LCR_DLAB) {`
171			`switch (addr % UART_ADDR_SPACE) {`
172			`case UART_DLL:`
173			`value = uarts[chipsel].regs.dll;`
174	1350	nogj	`debug(4, "= %"PRIx8"\n", value);`
175	355	markom	`return value;`
176			`case UART_DLH:`
177			`value = uarts[chipsel].regs.dlh;`
178	1350	nogj	`debug(4, "= %"PRIx8"\n", value);`
179	355	markom	`return value;`
180			`}`
181			`}`
182
183			`switch (addr % UART_ADDR_SPACE) {`
184			`case UART_RXBUF:`
185	409	markom	`{ /* Print out FIFO for debugging */`
186			`int i;`
187			`debug(4, "(%i/%i,%i,%i:", uarts[chipsel].istat.rxbuf_full, uarts[chipsel].fifo_len,`
188			`uarts[chipsel].istat.rxbuf_head, uarts[chipsel].istat.rxbuf_tail);`
189			`for (i = 0; i < uarts[chipsel].istat.rxbuf_full; i++)`
190			`debug(4, "%02x ", uarts[chipsel].regs.rxbuf[(uarts[chipsel].istat.rxbuf_tail + i) % uarts[chipsel].fifo_len]);`
191			`debug(4, ")");`
192			`}`
193	355	markom	`if (uarts[chipsel].istat.rxbuf_full) {`
194			`value = uarts[chipsel].regs.rxbuf[uarts[chipsel].istat.rxbuf_tail];`
195			`uarts[chipsel].istat.rxbuf_tail = (uarts[chipsel].istat.rxbuf_tail + 1) % uarts[chipsel].fifo_len;`
196			`uarts[chipsel].istat.rxbuf_full--;`
197			`}`
198
199			`if (uarts[chipsel].istat.rxbuf_full)`
200			`uarts[chipsel].regs.lsr \|= UART_LSR_RDRDY;`
201			`else`
202			`uarts[chipsel].regs.lsr &= ~UART_LSR_RDRDY;`
203	409	markom
204			`uarts[chipsel].istat.timeout_count = 0;`
205	355	markom	`break;`
206			`case UART_IER:`
207			`value = uarts[chipsel].regs.ier & UART_VALID_IER;`
208			`break;`
209			`case UART_IIR:`
210			`value = (uarts[chipsel].regs.iir & UART_VALID_IIR) \| 0xc0;`
211	1153	sfurman	`if (uarts[chipsel].regs.iir & UART_IIR_THRI)`
212	490	markom	`uarts[chipsel].istat.thre_int = 0;`
213	355	markom	`break;`
214			`case UART_LCR:`
215			`value = uarts[chipsel].regs.lcr & UART_VALID_LCR;`
216			`break;`
217			`case UART_MCR:`
218			`value = 0;`
219			`break;`
220			`case UART_LSR:`
221			`value = uarts[chipsel].regs.lsr & UART_VALID_LSR;`
222			`uarts[chipsel].regs.lsr &=`
223	409	markom	`~(UART_LSR_OVRRUN \| UART_LSR_BREAK \| UART_LSR_PARITY`
224			`\| UART_LSR_FRAME \| UART_LSR_RXERR);`
225	355	markom	`break;`
226			`case UART_MSR:`
227			`value = uarts[chipsel].regs.msr & UART_VALID_MSR;`
228			`uarts[chipsel].regs.msr = 0;`
229			`break;`
230			`case UART_SCR:`
231			`value = uarts[chipsel].regs.scr;`
232			`break;`
233			`default:`
234	1350	nogj	`debug(1, "read out of range (addr %"PRIxADDR")\n", addr);`
235	355	markom	`}`
236	1350	nogj	`debug(4, " = %"PRIx8"\n", value);`
237	355	markom	`return value;`
238	31	lampret	`}`
239
240	336	markom	`/* Function that handles incoming VAPI data. */`
241			`void uart_vapi_read (unsigned long id, unsigned long data)`
242			`{`
243	341	markom	`int uart;`
244	1350	nogj	`debug(4, "UART: id %08lx, data %08lx\n", id, data);`
245	341	markom	`uart = id & VAPI_DEVICE_ID;`
246			`uarts[uart].vapi_buf[uarts[uart].vapi_buf_head_ptr] = data;`
247	409	markom	`uarts[uart].vapi_buf_head_ptr = (uarts[uart].vapi_buf_head_ptr + 1) % UART_VAPI_BUF_LEN;`
248	341	markom	`if (uarts[uart].vapi_buf_tail_ptr == uarts[uart].vapi_buf_head_ptr) {`
249			`fprintf (stderr, "FATAL: uart VAPI buffer to small.\n");`
250			`exit (1);`
251			`}`
252			`}`
253	336	markom
254	409	markom	`static void send_char (int uart, int bits_send)`
255			`{`
256	1350	nogj	`PRINTF ("%c", (char)uarts[uart].iregs.txser);`
257			`debug(4, "TX \'%c\' via UART%d...\n", (char)uarts[uart].iregs.txser, uart);`
258	409	markom	`if (uarts[uart].regs.mcr & UART_MCR_LOOP)`
259			`uarts[uart].iregs.loopback = uarts[uart].iregs.txser;`
260			`else {`
261			`/* Send to either VAPI or to file */`
262			`if (config.uarts[uart].vapi_id) {`
263			`int par, pe, fe, nbits;`
264			`int j, data;`
265			`unsigned long packet = 0;`
266
267			`nbits = MIN (bits_send, (uarts[uart].regs.lcr & UART_LCR_WLEN8) + 5);`
268			`/* Encode a packet */`
269			`packet = uarts[uart].iregs.txser & ((1 << nbits) - 1);`
270
271			`/* Calculate parity */`
272			`for (j = 0, par = 0; j < nbits; j++)`
273			`par ^= (packet >> j) & 1;`
274
275			`if (uarts[uart].regs.lcr & UART_LCR_PARITY) {`
276			`if (uarts[uart].regs.lcr & UART_LCR_SPAR) {`
277			`packet \|= 1 << nbits;`
278			`} else {`
279			`if (uarts[uart].regs.lcr & UART_LCR_EPAR)`
280			`packet \|= par << nbits;`
281			`else`
282			`packet \|= (par ^ 1) << nbits;`
283			`}`
284			`nbits++;`
285			`}`
286			`packet \|= 1 << (nbits++);`
287			`if (uarts[uart].regs.lcr & UART_LCR_STOP)`
288			`packet \|= 1 << (nbits++);`
289
290			`/* Decode a packet */`
291			`nbits = (uarts[uart].vapi.lcr & UART_LCR_WLEN8) + 5;`
292			`data = packet & ((1 << nbits) - 1);`
293
294			`/* Calculate parity, including parity bit */`
295			`for (j = 0, par = 0; j < nbits + 1; j++)`
296			`par ^= (packet >> j) & 1;`
297
298			`if (uarts[uart].vapi.lcr & UART_LCR_PARITY) {`
299			`if (uarts[uart].vapi.lcr & UART_LCR_SPAR) {`
300			`pe = !((packet >> nbits) & 1);`
301			`} else {`
302			`if (uarts[uart].vapi.lcr & UART_LCR_EPAR)`
303			`pe = par != 0;`
304			`else`
305			`pe = par != 1;`
306			`}`
307			`nbits++;`
308			`} else`
309			`pe = 0;`
310
311			`fe = ((packet >> (nbits++)) & 1) ^ 1;`
312			`if (uarts[uart].vapi.lcr & UART_LCR_STOP)`
313			`fe \|= ((packet >> (nbits++)) & 1) ^ 1;`
314
315			`debug (4, "lcr vapi %02x, uart %02x\n", uarts[uart].vapi.lcr, uarts[uart].regs.lcr);`
316			`data \|= (uarts[uart].vapi.lcr << 8) \| (pe << 16) \| (fe << 17) \| (uarts[uart].vapi.lcr << 8);`
317	1308	phoenix	`PRINTF ("vapi_send (%08lx, %08x)\n", config.uarts[uart].vapi_id, data);`
318	1350	nogj	`debug (4, "vapi_send (%08lx, %08x)\n", config.uarts[uart].vapi_id, data);`
319	409	markom	`vapi_send (config.uarts[uart].vapi_id, data);`
320			`} else {`
321	1073	rprescott	`char buffer[1] = { uarts[uart].iregs.txser & 0xFF };`
322			`channel_write(channels[uart], buffer, 1);`
323	409	markom	`}`
324			`}`
325			`uarts[uart].istat.txser_full = 0;`
326			`uarts[uart].istat.txser_clks = 0;`
327			`}`
328
329	411	markom	`/* Adds a character to the FIFO */`
330
331			`void uart_add_char (int uart, int ch)`
332			`{`
333			`if (uarts[uart].istat.rxbuf_full + 1 > uarts[uart].fifo_len)`
334			`uarts[uart].regs.lsr \|= UART_LSR_OVRRUN \| UART_LSR_RXERR;`
335			`else {`
336			`debug(4, "add %02x\n", ch);`
337			`uarts[uart].regs.rxbuf[uarts[uart].istat.rxbuf_head] = ch;`
338			`uarts[uart].istat.rxbuf_head = (uarts[uart].istat.rxbuf_head + 1) % uarts[uart].fifo_len;`
339			`uarts[uart].istat.rxbuf_full++;`
340			`}`
341			`uarts[uart].regs.lsr \|= UART_LSR_RDRDY;`
342			`uarts[uart].istat.timeout_count = 0;`
343			`}`
344
345	806	markom	`/* Simulation hook. Must be called every clock cycle to simulate all UART`
346			`devices. It does internal functional UART simulation. */`
347	821	markom	`void uart_clock16 (int i)`
348	806	markom	`{`
349			`int retval;`
350	1073	rprescott
351	821	markom	`/* Schedule for later */`
352	884	markom	`SCHED_ADD (uart_clock16, i, runtime.sim.cycles + UART_CLOCK_DIVIDER);`
353	821	markom
354	806	markom	`/* If VAPI is not selected, UART communicates with two file streams;`
355			`if VAPI is selected, we use VAPI streams. */`
356			`/* if txfs is corrupted, skip this uart. */`
357	1073	rprescott	`if (!config.uarts[i].vapi_id && !channel_ok(channels[i])) return;`
358	806	markom
359			`if (uarts[i].vapi.next_break_cnt >= 0)`
360			`if (--uarts[i].vapi.next_break_cnt < 0) {`
361			`if (!(uarts[i].vapi.cur_break = uarts[i].vapi.next_break))`
362			`uarts[i].istat.break_set = 0;`
363			`}`
364	821	markom
365	806	markom	`/*************** Transmit ***************/`
366			`if (!uarts[i].istat.txser_full) {`
367			`// uarts[i].regs.lsr \|= UART_LSR_TXBUFE;`
368			`if (uarts[i].istat.txbuf_full) {`
369			`uarts[i].iregs.txser = uarts[i].regs.txbuf[uarts[i].istat.txbuf_tail];`
370			`uarts[i].istat.txbuf_tail = (uarts[i].istat.txbuf_tail + 1) % uarts[i].fifo_len;`
371			`uarts[i].istat.txser_full = 1;`
372			`uarts[i].istat.txbuf_full--;`
373			`uarts[i].regs.lsr &= ~UART_LSR_TXSERE;`
374	1143	sfurman
375			`// When UART is in either character mode, i.e. 16450 emulation mode, or FIFO mode,`
376			`// the THRE interrupt is raised when THR transitions from full to empty.`
377			`if (!uarts[i].istat.txbuf_full) {`
378			`uarts[i].istat.thre_int = 1;`
379			`uarts[i].regs.lsr \|= UART_LSR_TXBUFE;`
380			`}`
381	806	markom	`} else {`
382			`uarts[i].regs.lsr \|= UART_LSR_TXSERE;`
383			`}`
384			`} else if (uarts[i].char_clks <= uarts[i].istat.txser_clks++) {`
385			`send_char(i, (uarts[i].regs.lcr & UART_LCR_WLEN8) + 5); /* We've sent all bits */`
386			`} else {`
387			`/* We are still sending char here*/`
388
389			`/* Check if we set the break bit */`
390			`if (uarts[i].regs.lcr & UART_LCR_SBC) {`
391			`if (!uarts[i].vapi.break_sent) {`
392			`#if 0`
393			`/* Send broken frame */`
394			`int nbits_sent = ((uarts[i].regs.lcr & UART_LCR_WLEN8) + 5) * (uarts[i].istat.txser_clks - 1) / uarts[i].char_clks;`
395			`send_char(i, nbits_sent);`
396			`#endif`
397			`/* Send one break signal */`
398			`vapi_send (config.uarts[i].vapi_id, UART_LCR_SBC << 8);`
399			`uarts[i].vapi.break_sent = 1;`
400			`}`
401			`/* mark as character was sent */`
402			`uarts[i].istat.txser_full = 0;`
403			`uarts[i].istat.txser_clks = 0;`
404			`} else`
405			`uarts[i].vapi.break_sent = 0;`
406	1143	sfurman
407	806	markom	`}`
408	1143	sfurman
409	806	markom	`/*************** Receive ***************/`
410
411			`/* Is there a break? */`
412			`if (uarts[i].vapi.cur_break) {`
413			`uarts[i].vapi.cur_break_cnt++;`
414			`if (uarts[i].vapi.cur_break_cnt > UART_BREAK_COUNT * uarts[i].vapi.char_clks) {`
415			`if (!uarts[i].istat.break_set) {`
416			`unsigned lsr;`
417			`uarts[i].istat.break_set = 1;`
418			`lsr = UART_LSR_BREAK \| UART_LSR_RXERR \| UART_LSR_RDRDY;`
419	997	markom	`PRINTF ("[%x]\n", uarts[i].regs.lsr);`
420	806	markom	`uarts[i].istat.rxser_full = 0;`
421			`uarts[i].istat.rxser_clks = 0;`
422			`uart_add_char (i, lsr << 8);`
423			`} else`
424			`uarts[i].vapi.cur_break_cnt = 0;`
425			`}`
426			`if (uarts[i].istat.rxser_full) {`
427			`uarts[i].istat.rxser_full = 0;`
428			`uarts[i].istat.rxser_clks = 0;`
429			`}`
430			`} else {`
431			`if (uarts[i].istat.rxser_full) {`
432			`if (uarts[i].char_clks <= uarts[i].istat.rxser_clks++) {`
433			`/* Set unused character bits to zero and allow lsr register in fifo */`
434			`uarts[i].iregs.rxser &= ((1 << ((uarts[i].regs.lcr & 3) + 5)) - 1) \| 0xff00;`
435	1350	nogj	`debug(4, "Receiving 0x%02lx'%c' via UART%d...\n", uarts[i].iregs.rxser,`
436			`(char)uarts[i].iregs.rxser, i);`
437			`PRINTF ("%c", (char)uarts[i].iregs.rxser);`
438	806	markom	`uarts[i].istat.rxser_full = 0;`
439			`uarts[i].istat.rxser_clks = 0;`
440			`uart_add_char (i, uarts[i].iregs.rxser);`
441			`}`
442			`}`
443			`}`
444
445			`/* Check if there is something waiting, and put it into rxser */`
446			`if (uarts[i].regs.mcr & UART_MCR_LOOP) {`
447			`uarts[i].iregs.rxser = uarts[i].iregs.loopback;`
448			`uarts[i].istat.rxser_full = 1;`
449			`} else {`
450			`if (!config.uarts[i].vapi_id) {`
451			`if(uarts[i].istat.rxser_full == 0) {`
452			`if (uarts[i].slowdown)`
453			`uarts[i].slowdown--;`
454	1073	rprescott	`else {`
455			`char buffer[1];`
456			`retval = channel_read(channels[i], buffer, 1);`
457			`if(retval < 0)`
458			`perror(config.uarts[i].channel);`
459			`else if(retval > 0) {`
460	1116	sfurman	`uarts[i].iregs.rxser = (unsigned char)buffer[0];`
461	1073	rprescott	`uarts[i].istat.rxser_full = 1;`
462			`} else`
463			`uarts[i].slowdown = UART_FGETC_SLOWDOWN;`
464			`}`
465	806	markom	`}`
466			`} else { /* VAPI */`
467			`int received = 0;`
468			`/* do not handle commands while receiving */`
469			`if (uarts[i].istat.rxser_full) return;`
470			`while (!received) {`
471			`if (uarts[i].vapi_buf_head_ptr != uarts[i].vapi_buf_tail_ptr) {`
472			`unsigned long data = uarts[i].vapi_buf[uarts[i].vapi_buf_tail_ptr];`
473	1350	nogj	`debug(4, "Handling: %08lx (%i,%i)\n", data, uarts[i].vapi_buf_head_ptr, uarts[i].vapi_buf_tail_ptr);`
474	806	markom	`uarts[i].vapi_buf_tail_ptr = (uarts[i].vapi_buf_tail_ptr + 1) % UART_VAPI_BUF_LEN;`
475			`switch (data >> 24) {`
476			`case 0x00:`
477			`uarts[i].vapi.lcr = (data >> 8) & 0xff;`
478			`/* Put data into rx fifo */`
479			`uarts[i].iregs.rxser = data & 0xff;`
480			`uarts[i].vapi.char_clks = char_clks (uarts[i].vapi.dll, uarts[i].vapi.dlh, uarts[i].vapi.lcr);`
481			`if ((uarts[i].vapi.lcr & ~UART_LCR_SBC) != (uarts[i].regs.lcr & ~UART_LCR_SBC)`
482			`\|\| uarts[i].vapi.char_clks != uarts[i].char_clks`
483			`\|\| uarts[i].vapi.skew < -MAX_SKEW \|\| uarts[i].vapi.skew > MAX_SKEW) {`
484			`debug (3, "WARNING: unmatched VAPI (%02x) and uart (%02x) modes.\n",`
485			`uarts[i].vapi.lcr & ~UART_LCR_SBC, uarts[i].regs.lcr & ~UART_LCR_SBC);`
486			`/* Set error bits */`
487			`uarts[i].iregs.rxser \|= (UART_LSR_FRAME \| UART_LSR_RXERR) << 8;`
488			`if (uarts[i].regs.lcr & UART_LCR_PARITY) uarts[i].iregs.rxser \|= UART_LSR_PARITY << 8;`
489			`}`
490			`uarts[i].istat.rxser_full = 1;`
491			`received = 1;`
492			`break;`
493			`case 0x01:`
494			`uarts[i].vapi.dll = (data >> 0) & 0xff;`
495			`uarts[i].vapi.dlh = (data >> 8) & 0xff;`
496			`break;`
497			`case 0x02:`
498			`uarts[i].vapi.lcr = (data >> 8) & 0xff;`
499			`break;`
500			`case 0x03:`

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