OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_1_0/] [or1ksim/] [peripheral/] [eth.c] - Blame information for rev 836

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 696 ivang 
/* ethernet.c -- Simulation of Ethernet MAC
2 
   Copyright (C) 2001 by Erez Volk, erez@opencores.org
3 
                         Ivan Guzvinec, ivang@opencores.org
4 
 
5 
   This file is part of OpenRISC 1000 Architectural Simulator.
6 
 
7 
   This program is free software; you can redistribute it and/or modify
8 
   it under the terms of the GNU General Public License as published by
9 
   the Free Software Foundation; either version 2 of the License, or
10 
   (at your option) any later version.
11 
 
12 
   This program is distributed in the hope that it will be useful,
13 
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14 
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 
   GNU General Public License for more details.
16 
 
17 
   You should have received a copy of the GNU General Public License
18 
   along with this program; if not, write to the Free Software
19 
   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 
*/
21 
 
22 
#include <stdlib.h>
23 
#include <stdio.h>
24 
#include <string.h>
25 
#include <sys/types.h>
26 
#include <sys/stat.h>
27 
#include <fcntl.h>
28 
#include <sys/poll.h>
29 
#include <sys/time.h>
30 
#include <unistd.h>
31 
#include <errno.h>
32 
 
33 
#include "abstract.h"
34 
#include "ethernet_i.h"
35 
#include "dma.h"
36 
#include "sim-config.h"
37 
#include "fields.h"
38 
#include "crc32.h"
39 
 
40 
static struct eth_device eths[MAX_ETHERNETS];
41 
 
42 702 ivang 
/* simulator interface */
43 
static void eth_reset_controller( struct eth_device *eth);
44 696 ivang 
/* register interface */
45 
static void eth_write32( unsigned long addr, unsigned long value );
46 
static unsigned long eth_read32( unsigned long addr );
47 
/* clock */
48 
static void eth_controller_tx_clock( struct eth_device * );
49 
static void eth_controller_rx_clock( struct eth_device * );
50 
/* utility functions */
51 
static int eth_find_controller( unsigned long addr, struct eth_device **eth, unsigned long *reladdr );
52 702 ivang 
static ssize_t eth_read_rx_file( struct eth_device *, void *, size_t );
53 
static void eth_skip_rx_file( struct eth_device *, off_t );
54 
static void eth_rewind_rx_file( struct eth_device *, off_t );
55 
static void eth_rx_next_packet( struct eth_device * );
56 
static void eth_write_tx_bd_num( struct eth_device *, unsigned long value );
57 696 ivang 
/* ========================================================================= */
58 702 ivang 
/*  TX LOGIC                                                                 */
59 696 ivang 
/*---------------------------------------------------------------------------*/
60 
 
61 
/*
62 
 * TX clock
63 
 * Responsible for starting and finishing TX
64 
 */
65 
void eth_controller_tx_clock( struct eth_device *eth )
66 
{
67 702 ivang 
    int breakpoint = 0;
68 
    int bAdvance   = 1;
69 
    struct sockaddr_ll sll;
70 
 
71 
    long nwritten;
72 
    unsigned long read_word;
73 696 ivang 
 
74 
    switch (eth->tx.state) {
75 702 ivang 
        case ETH_TXSTATE_IDLE:
76 
        if ( TEST_FLAG( eth->regs.moder, ETH_MODER, TXEN ) ) {
77 
 
78 
            /* wait for TxBuffer to be ready */
79 705 ivang 
                debug (3, "TX - entering state WAIT4BD (%d)\n", eth->tx.bd_index);
80 702 ivang 
            eth->tx.state = ETH_TXSTATE_WAIT4BD;
81 
        }
82 
        break;
83 696 ivang 
    case ETH_TXSTATE_WAIT4BD:
84 702 ivang 
        /* Read buffer descriptor */
85 
        eth->tx.bd = eth->regs.bd_ram[eth->tx.bd_index];
86 
        eth->tx.bd_addr = eth->regs.bd_ram[eth->tx.bd_index + 1];
87 
 
88 
        if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, READY ) ) {
89 
            /*****************/
90 
            /* initialize TX */
91 
            eth->tx.bytes_left = eth->tx.packet_length = GET_FIELD( eth->tx.bd, ETH_TX_BD, LENGTH );
92 
            eth->tx.bytes_sent = 0;
93 
 
94 
            /*   Initialize error status bits */
95 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, DEFER );
96 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, COLLISION );
97 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, RETRANSMIT );
98 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, UNDERRUN );
99 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, NO_CARRIER );
100 
            SET_FIELD ( eth->tx.bd, ETH_TX_BD, RETRY, 0 );
101 
 
102 
            /* Find out minimum length */
103 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, PAD ) ||
104 
                 TEST_FLAG( eth->regs.moder, ETH_MODER, PAD ) )
105 
                eth->tx.minimum_length = GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL );
106 
            else
107 
                eth->tx.minimum_length = eth->tx.packet_length;
108 
 
109 
            /* Find out maximum length */
110 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, HUGEN ) )
111 
                eth->tx.maximum_length = eth->tx.packet_length;
112 
            else
113 
                eth->tx.maximum_length = GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL );
114 
 
115 
            /* Do we need CRC on this packet? */
116 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, CRCEN ) ||
117 
                 (TEST_FLAG( eth->tx.bd, ETH_TX_BD, CRC) &&
118 
                  TEST_FLAG( eth->tx.bd, ETH_TX_BD, LAST)) )
119 
                eth->tx.add_crc = 1;
120 
            else
121 
                eth->tx.add_crc = 0;
122 
 
123 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, DLYCRCEN ) )
124 
                eth->tx.crc_dly = 1;
125 
            else
126 
                eth->tx.crc_dly = 0;
127 
            /* XXX - For now we skip CRC calculation */
128 
 
129 
            debug( 3, "Ethernet: Starting TX of %u bytes (min. %u, max. %u)\n", eth->tx.packet_length,
130 
                   eth->tx.minimum_length, eth->tx.maximum_length );
131 
 
132 
            if (eth->rtx_type == ETH_RTX_FILE) {
133 
                /* write packet length to file */
134 
                nwritten = write( eth->txfd, &(eth->tx.packet_length), sizeof(eth->tx.packet_length) );
135 
            }
136 
 
137 
            /************************************************/
138 
            /* start transmit with reading packet into FIFO */
139 
                debug (3, "TX - entering state READFIFO\n");
140 
            eth->tx.state = ETH_TXSTATE_READFIFO;
141 
        }
142 
        else if ( !TEST_FLAG( eth->regs.moder, ETH_MODER, TXEN ) ) {
143 
            /* stop TX logic */
144 
                debug (3, "TX - entering state IDLE\n");
145 
            eth->tx.state = ETH_TXSTATE_IDLE;
146 
        }
147 
 
148 
        /* stay in this state if (TXEN && !READY) */
149 
        break;
150 696 ivang 
    case ETH_TXSTATE_READFIFO:
151 744 simons 
#if 1
152 702 ivang 
        if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
153 
            read_word = eval_mem32(eth->tx.bytes_sent + eth->tx.bd_addr, &breakpoint);
154 
            eth->tx_buff[eth->tx.bytes_sent]   = (unsigned char)(read_word >> 24);
155 
            eth->tx_buff[eth->tx.bytes_sent+1] = (unsigned char)(read_word >> 16);
156 
            eth->tx_buff[eth->tx.bytes_sent+2] = (unsigned char)(read_word >> 8);
157 
            eth->tx_buff[eth->tx.bytes_sent+3] = (unsigned char)(read_word);
158 
            eth->tx.bytes_sent += 4;
159 
        }
160 744 simons 
#else
161 
        if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
162 
            eth->tx_buff[eth->tx.bytes_sent] = eval_mem8(eth->tx.bytes_sent + eth->tx.bd_addr, &breakpoint);
163 
            eth->tx.bytes_sent += 1;
164 
        }
165 
#endif
166 702 ivang 
        else {
167 
            debug (3, "TX - entering state TRANSMIT\n");
168 
            eth->tx.state = ETH_TXSTATE_TRANSMIT;
169 
        }
170 
        break;
171 696 ivang 
    case ETH_TXSTATE_TRANSMIT:
172 702 ivang 
        /* send packet */
173 
        switch (eth->rtx_type) {
174 
        case ETH_RTX_FILE:
175 
            nwritten = write( eth->txfd, eth->tx_buff, eth->tx.packet_length );
176 
            break;
177 
        case ETH_RTX_SOCK:
178 
            memset(&sll, 0, sizeof(sll));
179 705 ivang 
            sll.sll_ifindex = eth->ifr.ifr_ifindex;
180 
            nwritten = sendto(eth->rtx_sock, eth->tx_buff, eth->tx.packet_length, 0, (struct sockaddr *)&sll, sizeof(sll));
181 
            break;
182 702 ivang 
        }
183 
 
184 
        /* set BD status */
185 
        if (nwritten == eth->tx.packet_length) {
186 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
187 
            SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXB);
188 836 ivang 
            debug (4, "ETH_INT_SOURCE = %0x\n", eth->regs.int_source);
189 702 ivang 
 
190 705 ivang 
            debug (3, "TX - entering state IDLE\n");
191 702 ivang 
            eth->tx.state = ETH_TXSTATE_IDLE;
192 
            debug (3, "send (%d)bytes OK\n", nwritten);
193 
        }
194 
        else {
195 
            /* XXX - implement retry mechanism here! */
196 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
197 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, COLLISION);
198 
            SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXE);
199 
 
200 
                debug (3, "TX - entering state IDLE\n");
201 
            eth->tx.state = ETH_TXSTATE_IDLE;
202 
            debug (3, "send FAILED!\n");
203 
        }
204 
 
205 
        eth->regs.bd_ram[eth->tx.bd_index] = eth->tx.bd;
206 
 
207 
        /* advance to next BD */
208 
        if (bAdvance) {
209 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, WRAP ) ||
210 
                            eth->tx.bd_index >= ETH_BD_COUNT )
211 
                eth->tx.bd_index = 0;
212 
            else
213 
                eth->tx.bd_index += 2;
214 
        }
215 
 
216 
        /* generate OK interrupt */
217 
        if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, TXE_M) ||
218 
             TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, TXB_M) )
219 
        {
220 
            report_interrupt( eth->mac_int );
221 
        }
222 
 
223 
        break;
224 696 ivang 
    }
225 
}
226 
/* ========================================================================= */
227 
 
228 
 
229 
/* ========================================================================= */
230 702 ivang 
/*  RX LOGIC                                                                 */
231 696 ivang 
/*---------------------------------------------------------------------------*/
232 
 
233 
/*
234 
 * RX clock
235 
 * Responsible for starting and finishing RX
236 
 */
237 
void eth_controller_rx_clock( struct eth_device *eth )
238 
{
239 702 ivang 
    int i;
240 
    int breakpoint = 0;
241 
    long nread;
242 
    unsigned long send_word;
243 
 
244 
    fd_set rfds;
245 
 
246 696 ivang 
    switch (eth->rx.state) {
247 
    case ETH_RXSTATE_IDLE:
248 702 ivang 
        if ( TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN) ) {
249 705 ivang 
                debug (3, "RX - entering state WAIT4BD (%d)\n", eth->rx.bd_index);
250 702 ivang 
            eth->rx.state = ETH_RXSTATE_WAIT4BD;
251 
        }
252 
        break;
253 
 
254 696 ivang 
    case ETH_RXSTATE_WAIT4BD:
255 702 ivang 
        eth->rx.bd = eth->regs.bd_ram[eth->rx.bd_index];
256 
        eth->rx.bd_addr = eth->regs.bd_ram[eth->rx.bd_index + 1];
257 
 
258 
        if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, READY ) ) {
259 
            /*****************/
260 
            /* Initialize RX */
261 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, MISS );
262 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, INVALID );
263 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, DRIBBLE );
264 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, UVERRUN );
265 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, COLLISION );
266 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG );
267 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT );
268 
 
269 
            debug( 3,  "Ethernet: Starting RX\n" );
270 
 
271 
            /* Setup file to read from */
272 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, LOOPBCK ) ) {
273 
                eth->rx.fd = eth->txfd;
274 
                eth->rx.offset = &(eth->loopback_offset);
275 
            } else {
276 
                eth->rx.fd = eth->rxfd;
277 
                eth->rx.offset = 0;
278 
            }
279 
                debug (3, "RX - entering state RECV\n");
280 
            eth->rx.state = ETH_RXSTATE_RECV;
281 
        }
282 705 ivang 
        else if (!TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN)) {
283 
          debug (3, "RX - entering state IDLE\n");
284 
          eth->rx.state = ETH_RXSTATE_IDLE;
285 
        }
286 
        else {
287 744 simons 
            nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, /*MSG_PEEK | */MSG_DONTWAIT);
288 705 ivang 
            if (nread > 0) {
289 702 ivang 
                SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, BUSY);
290 723 ivang 
                if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, BUSY_M) )
291 
                  report_interrupt(eth->mac_int);
292 702 ivang 
            }
293 
        }
294 
        break;
295 
 
296 696 ivang 
    case ETH_RXSTATE_RECV:
297 702 ivang 
        switch (eth->rtx_type) {
298 
        case ETH_RTX_FILE:
299 
            /* Read packet length */
300 
            if ( eth_read_rx_file( eth, &(eth->rx.packet_length), sizeof(eth->rx.packet_length) )
301 
                     < sizeof(eth->rx.packet_length) ) {
302 
                /* TODO: just do what real ethernet would do (some kind of error state) */
303 836 ivang 
                debug (4, "eth_start_rx(): File does not have a packet ready for RX (len = %d)\n", eth->rx.packet_length );
304 702 ivang 
                cont_run = 0;
305 
                break;
306 
            }
307 
 
308 
            /* Packet must be big enough to hold a header */
309 
            if ( eth->rx.packet_length < ETH_HLEN ){
310 
                debug( 3,  "eth_start_rx(): Packet too small\n" );
311 
                eth_rx_next_packet( eth );
312 
 
313 836 ivang 
                debug (3, "RX - entering state IDLE\n");
314 702 ivang 
                eth->rx.state = ETH_RXSTATE_IDLE;
315 
                break;
316 
            }
317 
 
318 
            eth->rx.bytes_read = 0;
319 
            eth->rx.bytes_left = eth->rx.packet_length;
320 
 
321 
            /* for now Read entire packet into memory */
322 
            nread = eth_read_rx_file( eth, eth->rx_buff, eth->rx.bytes_left );
323 
            if ( nread < eth->rx.bytes_left )
324 
                debug (3, "Read %d from %d. Error!\n", nread, eth->rx.bytes_left);
325 
                eth->rx.error = 1;
326 
            break;
327 
 
328 
        case ETH_RTX_SOCK:
329 
            nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, MSG_DONTWAIT);
330 744 simons 
 
331 
            if (nread == 0)
332 
                break;
333 
            else if (nread < 0) {
334 
                if ( errno != EAGAIN ) {
335 702 ivang 
                            debug (3, "recv() FAILED!\n");
336 
                            break;
337 
                        }
338 
                        else {
339 
                        break;
340 
                    }
341 744 simons 
            }
342 
            /* If not promiscouos mode, check the destination address */
343 
            if (!TEST_FLAG(eth->regs.moder, ETH_MODER, PRO)) {
344 
                if (TEST_FLAG(eth->regs.moder, ETH_MODER, IAM) && (eth->rx_buff[0] & 1)) {
345 
                /* Nothing for now */
346 
                }
347 
 
348 
                if (eth->mac_address[5] != eth->rx_buff[0] ||
349 
                    eth->mac_address[4] != eth->rx_buff[1] ||
350 
                    eth->mac_address[3] != eth->rx_buff[2] ||
351 
                    eth->mac_address[2] != eth->rx_buff[3] ||
352 
                    eth->mac_address[1] != eth->rx_buff[4] ||
353 
                    eth->mac_address[0] != eth->rx_buff[5])
354 
                        break;
355 
            }
356 
 
357 702 ivang 
            break;
358 
        }
359 836 ivang 
 
360 
        eth->rx.packet_length = nread;
361 
        eth->rx.bytes_left = nread;
362 
        eth->rx.bytes_read = 0;
363 
 
364 
        debug (3, "RX - entering state WRITEFIFO\n");
365 
        eth->rx.state = ETH_RXSTATE_WRITEFIFO;
366 702 ivang 
 
367 836 ivang 
        break;
368 
 
369 696 ivang 
    case ETH_RXSTATE_WRITEFIFO:
370 744 simons 
#if 1
371 702 ivang 
        send_word = ((unsigned long)eth->rx_buff[eth->rx.bytes_read]   << 24) |
372 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+1] << 16) |
373 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+2] << 8)  |
374 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+3] );
375 
        set_mem32( eth->rx.bd_addr + eth->rx.bytes_read, send_word, &breakpoint);
376 
        /* update counters */
377 
        debug (3, "Write %d, left %d - %08lXd\n", eth->rx.bytes_read, eth->rx.bytes_left, send_word);
378 
        eth->rx.bytes_left -= 4;
379 
        eth->rx.bytes_read += 4;
380 744 simons 
#else
381 
        set_mem8( eth->rx.bd_addr + eth->rx.bytes_read, eth->rx_buff[eth->rx.bytes_read], &breakpoint);
382 
        eth->rx.bytes_left -= 1;
383 
        eth->rx.bytes_read += 1;
384 
#endif
385 
 
386 702 ivang 
        if ( eth->rx.bytes_left <= 0 ) {
387 
            /* Write result to bd */
388 
            SET_FIELD( eth->rx.bd, ETH_RX_BD, LENGTH, eth->rx.packet_length );
389 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, READY);
390 705 ivang 
            SET_FLAG( eth->regs.int_source, ETH_INT_SOURCE, RXB);
391 836 ivang 
            debug (4, "ETH_INT_SOURCE = %0x\n", eth->regs.int_source);
392 702 ivang 
 
393 
            if ( eth->rx.packet_length < GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL ) )
394 744 simons 
                SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT);
395 
            if ( eth->rx.packet_length > GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL ) )
396 702 ivang 
                SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG);
397 
 
398 
            eth->regs.bd_ram[eth->rx.bd_index] = eth->rx.bd;
399 
 
400 
            /* advance to next BD */
401 
            if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, WRAP ) || eth->rx.bd_index >= ETH_BD_COUNT )
402 705 ivang 
                eth->rx.bd_index = eth->regs.tx_bd_num;
403 702 ivang 
            else
404 705 ivang 
                eth->rx.bd_index += 2;
405 702 ivang 
 
406 705 ivang 
            if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, RXB_M) ) {
407 702 ivang 
                report_interrupt( eth->mac_int );
408 
            }
409 
 
410 
            /* ready to receive next packet */
411 
                debug (3, "RX - entering state IDLE\n");
412 
            eth->rx.state = ETH_RXSTATE_IDLE;
413 
        }
414 
        break;
415 696 ivang 
    }
416 
}
417 702 ivang 
 
418 696 ivang 
/* ========================================================================= */
419 702 ivang 
/* Move to next RX BD */
420 
void eth_rx_next_packet( struct eth_device *eth )
421 
{
422 
    /* Skip any possible leftovers */
423 
    if ( eth->rx.bytes_left )
424 
        eth_skip_rx_file( eth, eth->rx.bytes_left );
425 
}
426 
/* "Skip" bytes in RX file */
427 
void eth_skip_rx_file( struct eth_device *eth, off_t count )
428 
{
429 
    eth->rx.offset += count;
430 
}
431 696 ivang 
 
432 702 ivang 
/* Move RX file position back */
433 
void eth_rewind_rx_file( struct eth_device *eth, off_t count )
434 
{
435 
    eth->rx.offset -= count;
436 
}
437 
/*
438 
 * Utility function to read from the ethernet RX file
439 
 * This function moves the file pointer to the current place in the packet before reading
440 
 */
441 
ssize_t eth_read_rx_file( struct eth_device *eth, void *buf, size_t count )
442 
{
443 
    ssize_t result;
444 
 
445 
    if ( eth->rx.fd <= 0 ) {
446 
        debug( 3,  "Ethernet: No RX file\n" );
447 
        return 0;
448 
    }
449 
 
450 
    if ( eth->rx.offset )
451 
        if ( lseek( eth->rx.fd, *(eth->rx.offset), SEEK_SET ) == (off_t)-1 ) {
452 
            debug( 3,  "Ethernet: Error seeking RX file\n" );
453 
            return 0;
454 
        }
455 696 ivang 
 
456 702 ivang 
    result = read( eth->rx.fd, buf, count );
457 836 ivang 
    debug (4, "Ethernet: read result = %d \n", result);
458 702 ivang 
    if ( eth->rx.offset && result >= 0 )
459 
        *(eth->rx.offset) += result;
460 
 
461 
    return result;
462 
}
463 
 
464 
/* ========================================================================= */
465 
 
466 696 ivang 
/*
467 702 ivang 
  Reset. Initializes all registers to default and places devices in
468 
         memory address space.
469 696 ivang 
*/
470 
void eth_reset()
471 
{
472 
    static int first_time = 1;
473 
    unsigned i;
474 
 
475 
    if (!config.nethernets)
476 702 ivang 
        return;
477 696 ivang 
 
478 
    if ( first_time ) {
479 702 ivang 
        memset( eths, 0, sizeof(eths) );
480 
        first_time = 0;
481 696 ivang 
    }
482 
 
483 
    for ( i = 0; i < MAX_ETHERNETS; ++ i ) {
484 702 ivang 
        struct eth_device *eth = &(eths[i]);
485 
 
486 
        eth->eth_number = i;
487 
        eth_reset_controller( eth );
488 696 ivang 
    }
489 
}
490 
/* ========================================================================= */
491 
 
492 
 
493 702 ivang 
static void eth_reset_controller(struct eth_device *eth)
494 
{
495 
    int i = eth->eth_number;
496 
    int j;
497 
    struct sockaddr_ll sll;
498 
 
499 
    eth->baseaddr = config.ethernets[i].baseaddr;
500 
 
501 
    if ( eth->baseaddr != 0 ) {
502 
        /* Mark which DMA controller and channels */
503 
        eth->dma        = config.ethernets[i].dma;
504 725 ivang 
        eth->mac_int    = config.ethernets[i].irq;
505 702 ivang 
        eth->tx_channel = config.ethernets[i].tx_channel;
506 
        eth->rx_channel = config.ethernets[i].rx_channel;
507 725 ivang 
        eth->rtx_type   = config.ethernets[i].rtx_type;
508 702 ivang 
 
509 
        switch (eth->rtx_type) {
510 
        case ETH_RTX_FILE:
511 
            /* (Re-)open TX/RX files */
512 
            eth->rxfile = config.ethernets[i].rxfile;
513 
            eth->txfile = config.ethernets[i].txfile;
514 
 
515 
            if ( eth->rxfd > 0 )
516 
                close( eth->rxfd );
517 
            if ( eth->txfd > 0 )
518 
                close( eth->txfd );
519 
            eth->rxfd = eth->txfd = -1;
520 
 
521 
            if ( (eth->rxfd = open( eth->rxfile, O_RDONLY )) < 0 )
522 
                fprintf( stderr, "Cannot open Ethernet RX file \"%s\"\n", eth->rxfile );
523 
            if ( (eth->txfd = open( eth->txfile,
524 
                                    O_RDWR | O_CREAT | O_APPEND | O_SYNC,
525 
                                    S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH )) < 0 )
526 
                fprintf( stderr, "Cannot open Ethernet TX file \"%s\"\n", eth->txfile );
527 
            eth->loopback_offset = lseek( eth->txfd, 0, SEEK_END );
528 
 
529 
            break;
530 
        case ETH_RTX_SOCK:
531 
            /* (Re-)open TX/RX sockets */
532 
            if (eth->rtx_sock != 0)
533 
                break;
534 
 
535 
            debug (3, "RTX oppening socket...\n");
536 
            eth->rtx_sock = socket(PF_PACKET, SOCK_RAW, htons(ETH_P_ALL));
537 
            if (eth->rtx_sock == -1) {
538 
                fprintf( stderr, "Cannot open rtx_sock.\n");
539 
                return;
540 
            }
541 
 
542 
            /* get interface index number */
543 
            debug (3, "RTX getting interface...\n");
544 
            memset(&(eth->ifr), 0, sizeof(eth->ifr));
545 725 ivang 
            strncpy(eth->ifr.ifr_name, config.ethernets[i].sockif, IFNAMSIZ);
546 702 ivang 
            if (ioctl(eth->rtx_sock, SIOCGIFINDEX, &(eth->ifr)) == -1) {
547 
                fprintf( stderr, "SIOCGIFINDEX failed!\n");
548 
                return;
549 
            }
550 
            debug (3, "RTX Socket Interface : %d\n", eth->ifr.ifr_ifindex);
551 
 
552 
            /* Bind to interface... */
553 
            debug (3, "Binding to the interface ifindex=%d\n", eth->ifr.ifr_ifindex);
554 
            memset(&sll, 0xff, sizeof(sll));
555 
            sll.sll_family = AF_PACKET;    /* allways AF_PACKET */
556 
            sll.sll_protocol = htons(ETH_P_ALL);
557 
            sll.sll_ifindex = eth->ifr.ifr_ifindex;
558 
            if (bind(eth->rtx_sock, (struct sockaddr *)&sll, sizeof(sll)) == -1) {
559 
                fprintf( stderr, "Error bind().\n");
560 
                return;
561 
            }
562 
 
563 
            /* first, flush all received packets. */
564 
            debug (3, "Flush");
565 
            do {
566 
                fd_set fds;
567 
                struct timeval t;
568 
 
569 
                debug( 3, ".");
570 
                FD_ZERO(&fds);
571 
                FD_SET(eth->rtx_sock, &fds);
572 
                memset(&t, 0, sizeof(t));
573 
                j = select(FD_SETSIZE, &fds, NULL, NULL, &t);
574 
                if (j > 0)
575 
                    recv(eth->rtx_sock, eth->rx_buff, j, 0);
576 
            } while (j);
577 
            debug (3, "\n");
578 
 
579 
            break;
580 
        }
581 
 
582 
        /* Set registers to default values */
583 
        memset( &(eth->regs), 0, sizeof(eth->regs) );
584 
        eth->regs.moder = 0x0000A000;
585 
        eth->regs.ipgt = 0x00000012;
586 
        eth->regs.ipgr1 = 0x0000000C;
587 
        eth->regs.ipgr2 = 0x00000012;
588 
        eth->regs.packetlen = 0x003C0600;
589 
        eth->regs.collconf = 0x000F003F;
590 
        eth->regs.miimoder = 0x00000064;
591 
        eth->regs.tx_bd_num = 0x00000080;
592 
 
593 
        /* Initialize TX/RX status */
594 
        memset( &(eth->tx), 0, sizeof(eth->tx) );
595 
        memset( &(eth->rx), 0, sizeof(eth->rx) );
596 
        eth->rx.bd_index = eth->regs.tx_bd_num;
597 
 
598 
        /* Register memory range */
599 
        register_memoryarea( eth->baseaddr, ETH_ADDR_SPACE, 4, eth_read32, eth_write32 );
600 
    }
601 
}
602 
/* ========================================================================= */
603 
 
604 
 
605 696 ivang 
/*
606 
  Print register values on stdout
607 
*/
608 
void eth_status( void )
609 
{
610 
    unsigned i;
611 
 
612 
    for ( i = 0; i < MAX_ETHERNETS; ++ i ) {
613 702 ivang 
        struct eth_device *eth = &(eths[i]);
614 
 
615 
        if ( eth->baseaddr == 0 )
616 
            continue;
617 
 
618 
        printf( "\nEthernet MAC %u at 0x%08X:\n", i, eth->baseaddr );
619 
        printf( "MODER        : 0x%08lX\n", eth->regs.moder );
620 
        printf( "INT_SOURCE   : 0x%08lX\n", eth->regs.int_source );
621 
        printf( "INT_MASK     : 0x%08lX\n", eth->regs.int_mask );
622 
        printf( "IPGT         : 0x%08lX\n", eth->regs.ipgt );
623 
        printf( "IPGR1        : 0x%08lX\n", eth->regs.ipgr1 );
624 
        printf( "IPGR2        : 0x%08lX\n", eth->regs.ipgr2 );
625 
        printf( "PACKETLEN    : 0x%08lX\n", eth->regs.packetlen );
626 
        printf( "COLLCONF     : 0x%08lX\n", eth->regs.collconf );
627 
        printf( "TX_BD_NUM    : 0x%08lX\n", eth->regs.tx_bd_num );
628 
        printf( "CTRLMODER    : 0x%08lX\n", eth->regs.controlmoder );
629 
        printf( "MIIMODER     : 0x%08lX\n", eth->regs.miimoder );
630 
        printf( "MIICOMMAND   : 0x%08lX\n", eth->regs.miicommand );
631 
        printf( "MIIADDRESS   : 0x%08lX\n", eth->regs.miiaddress );
632 
        printf( "MIITX_DATA   : 0x%08lX\n", eth->regs.miitx_data );
633 
        printf( "MIIRX_DATA   : 0x%08lX\n", eth->regs.miirx_data );
634 
        printf( "MIISTATUS    : 0x%08lX\n", eth->regs.miistatus );
635 
        printf( "MAC Address  : %02X:%02X:%02X:%02X:%02X:%02X\n",
636 
                eth->mac_address[0], eth->mac_address[1], eth->mac_address[2],
637 
                eth->mac_address[3], eth->mac_address[4], eth->mac_address[5] );
638 744 simons 
        printf( "HASH0        : 0x%08lX\n", eth->regs.hash0 );
639 
        printf( "HASH1        : 0x%08lX\n", eth->regs.hash1 );
640 696 ivang 
    }
641 
}
642 
/* ========================================================================= */
643 
 
644 
 
645 
/*
646 
  Simulation hook. Must be called every clock cycle to simulate Ethernet MAC.
647 
*/
648 
void eth_clock()
649 
{
650 
    unsigned i;
651 
 
652 
    for ( i = 0; i < config.nethernets; ++ i ) {
653 702 ivang 
        eth_controller_tx_clock( &(eths[i]) );
654 
        eth_controller_rx_clock( &(eths[i]) );
655 696 ivang 
    }
656 
}
657 
/* ========================================================================= */
658 
 
659 
 
660 
/*
661 
  Read a register
662 
*/
663 
unsigned long eth_read32( unsigned long addr )
664 
{
665 
    struct eth_device *eth;
666 702 ivang 
    if ( !eth_find_controller( addr, &eth, &addr ) )    {
667 
        printf( "eth_read32( 0x%08lX ): Not in registered range(s)\n", addr );
668 
        return 0;
669 696 ivang 
    }
670 
 
671 
    switch( addr ) {
672 
    case ETH_MODER: return eth->regs.moder;
673 
    case ETH_INT_SOURCE: return eth->regs.int_source;
674 
    case ETH_INT_MASK: return eth->regs.int_mask;
675 
    case ETH_IPGT: return eth->regs.ipgt;
676 
    case ETH_IPGR1: return eth->regs.ipgr1;
677 
    case ETH_IPGR2: return eth->regs.ipgr2;
678 
    case ETH_PACKETLEN: return eth->regs.packetlen;
679 
    case ETH_COLLCONF: return eth->regs.collconf;
680 
    case ETH_TX_BD_NUM: return eth->regs.tx_bd_num;
681 
    case ETH_CTRLMODER: return eth->regs.controlmoder;
682 
    case ETH_MIIMODER: return eth->regs.miimoder;
683 
    case ETH_MIICOMMAND: return eth->regs.miicommand;
684 
    case ETH_MIIADDRESS: return eth->regs.miiaddress;
685 
    case ETH_MIITX_DATA: return eth->regs.miitx_data;
686 
    case ETH_MIIRX_DATA: return eth->regs.miirx_data;
687 
    case ETH_MIISTATUS: return eth->regs.miistatus;
688 
    case ETH_MAC_ADDR0: return (((unsigned long)eth->mac_address[3]) << 24) |
689 702 ivang 
                               (((unsigned long)eth->mac_address[2]) << 16) |
690 
                               (((unsigned long)eth->mac_address[1]) << 8) |
691 
                                 (unsigned long)eth->mac_address[0];
692 696 ivang 
    case ETH_MAC_ADDR1: return (((unsigned long)eth->mac_address[5]) << 8) |
693 702 ivang 
                                 (unsigned long)eth->mac_address[4];
694 744 simons 
    case ETH_HASH0: return eth->regs.hash0;
695 
    case ETH_HASH1: return eth->regs.hash1;
696 702 ivang 
    /*case ETH_DMA_RX_TX: return eth_rx( eth );*/
697 696 ivang 
    }
698 
 
699 
    if ( (addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE) )
700 702 ivang 
        return eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4];
701 696 ivang 
 
702 
    printf( "eth_read32( 0x%08lX ): Illegal address\n", addr + eth->baseaddr );
703 
    cont_run = 0;
704 
    return 0;
705 
}
706 
/* ========================================================================= */
707 
 
708 
 
709 
/*
710 
  Write a register
711 
*/
712 
void eth_write32( unsigned long addr, unsigned long value )
713 
{
714 
    struct eth_device *eth;
715 702 ivang 
    if ( !eth_find_controller( addr, &eth, &addr ) )    {
716 
        printf( "eth_write32( 0x%08lX ): Not in registered range(s)\n", addr );
717 
    return;
718 696 ivang 
    }
719 
 
720 
    switch( addr ) {
721 
    case ETH_MODER: eth->regs.moder = value; return;
722 744 simons 
    case ETH_INT_SOURCE: eth->regs.int_source &= ~value; return;
723 696 ivang 
    case ETH_INT_MASK: eth->regs.int_mask = value; return;
724 
    case ETH_IPGT: eth->regs.ipgt = value; return;
725 
    case ETH_IPGR1: eth->regs.ipgr1 = value; return;
726 
    case ETH_IPGR2: eth->regs.ipgr2 = value; return;
727 
    case ETH_PACKETLEN: eth->regs.packetlen = value; return;
728 
    case ETH_COLLCONF: eth->regs.collconf = value; return;
729 
    case ETH_TX_BD_NUM: eth_write_tx_bd_num( eth, value ); return;
730 
    case ETH_CTRLMODER: eth->regs.controlmoder = value; return;
731 
    case ETH_MIIMODER: eth->regs.miimoder = value; return;
732 
    case ETH_MIICOMMAND: eth->regs.miicommand = value; return;
733 
    case ETH_MIIADDRESS: eth->regs.miiaddress = value; return;
734 
    case ETH_MIITX_DATA: eth->regs.miitx_data = value; return;
735 
    case ETH_MIIRX_DATA: eth->regs.miirx_data = value; return;
736 
    case ETH_MIISTATUS: eth->regs.miistatus = value; return;
737 
    case ETH_MAC_ADDR0:
738 702 ivang 
        eth->mac_address[0] = value & 0xFF;
739 
        eth->mac_address[1] = (value >> 8) & 0xFF;
740 
        eth->mac_address[2] = (value >> 16) & 0xFF;
741 
        eth->mac_address[3] = (value >> 24) & 0xFF;
742 
        return;
743 696 ivang 
    case ETH_MAC_ADDR1:
744 702 ivang 
        eth->mac_address[4] = value & 0xFF;
745 
        eth->mac_address[5] = (value >> 8) & 0xFF;
746 
        return;
747 744 simons 
    case ETH_HASH0: eth->regs.hash0 = value; return;
748 
    case ETH_HASH1: eth->regs.hash1 = value; return;
749 702 ivang 
 
750 
    /*case ETH_DMA_RX_TX: eth_tx( eth, value ); return;*/
751 696 ivang 
    }
752 
 
753 
    if ( (addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE) ) {
754 702 ivang 
        eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4] = value;
755 
        return;
756 696 ivang 
    }
757 
 
758 
    printf( "eth_write32( 0x%08lX ): Illegal address\n", addr + eth->baseaddr );
759 
    cont_run = 0;
760 
    return;
761 
}
762 
/* ========================================================================= */
763 
 
764 
 
765 702 ivang 
/* When TX_BD_NUM is written, also reset current RX BD index */
766 
void eth_write_tx_bd_num( struct eth_device *eth, unsigned long value )
767 
{
768 
    eth->rx.bd_index = eth->regs.tx_bd_num = value & 0xFF;
769 
}
770 
/* ========================================================================= */
771 
 
772 
 
773 696 ivang 
/*
774 
  Convert a memory address to a oontroller struct and relative address.
775 
  Return nonzero on success
776 
*/
777 
int eth_find_controller( unsigned long addr, struct eth_device **eth, unsigned long *reladdr )
778 
{
779 
    unsigned i;
780 
    *eth = NULL;
781 
 
782 
    for ( i = 0; i < MAX_ETHERNETS && *eth == NULL; ++ i ) {
783 702 ivang 
        if ( (addr >= eths[i].baseaddr) && (addr < eths[i].baseaddr + ETH_ADDR_SPACE) )
784 
            *eth = &(eths[i]);
785 
        }
786 696 ivang 
 
787 
    /* verify we found a controller */
788 
    if ( *eth == NULL )
789 702 ivang 
        return 0;
790 696 ivang 
 
791 
    /* Verify legal address */
792 
    if ( (addr - (*eth)->baseaddr) % 4 != 0 )
793 702 ivang 
        return 0;
794 696 ivang 
 
795 
    *reladdr = addr - (*eth)->baseaddr;
796 
    return 1;
797 
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.