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[/] [or1k/] [tags/] [stable_0_1_0/] [or1ksim/] [peripheral/] [mc.c] - Blame information for rev 1780

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1 239 markom 
/* mc.c -- Simulation of Memory Controller
2 
         Copyright (C) 2001 by Marko Mlinar, markom@opencores.org
3 
 
4 
         This file is part of OpenRISC 1000 Architectural Simulator.
5 
 
6 
         This program is free software; you can redistribute it and/or modify
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         it under the terms of the GNU General Public License as published by
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         the Free Software Foundation; either version 2 of the License, or
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         (at your option) any later version.
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11 
         This program is distributed in the hope that it will be useful,
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         but WITHOUT ANY WARRANTY; without even the implied warranty of
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         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.    See the
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         GNU General Public License for more details.
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16 
         You should have received a copy of the GNU General Public License
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         along with this program; if not, write to the Free Software
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         Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 
*/
20 
 
21 
/* Enable memory controller, via:
22 
  section mc
23 
    enable = 1
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    POC = 0x13243545
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  end
26 
 
27 261 markom 
   Limitations:
28 
    - memory refresh is not simulated
29 742 ivang 
*/
30 239 markom 
 
31 1308 phoenix 
#include <string.h>
32 
 
33 1350 nogj 
#include "config.h"
34 
 
35 
#ifdef HAVE_INTTYPES_H
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#include <inttypes.h>
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#endif
38 
 
39 
#include "port.h"
40 
#include "arch.h"
41 239 markom 
#include "mc.h"
42 
#include "abstract.h"
43 261 markom 
#include "sim-config.h"
44 1308 phoenix 
#include "debug.h"
45 261 markom 
 
46 539 simons 
extern struct dev_memarea *dev_list;
47 
 
48 261 markom 
static struct mc mc;
49 
 
50 539 simons 
void set_csc_tms (int cs, unsigned long csc, unsigned long tms) {
51 
  struct dev_memarea *mem_dev = dev_list;
52 
 
53 
  while (mem_dev) {
54 
    if (mem_dev->chip_select == cs) {
55 970 simons 
      mem_dev->addr_mask = mc.ba_mask << 22;
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      mem_dev->addr_compare = ((csc >> MC_CSC_SEL_OFFSET) /* & 0xff*/) << 22;
57 543 simons 
      mem_dev->valid = (csc >> MC_CSC_EN_OFFSET) & 0x01;
58 539 simons 
 
59 
      if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {
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        mem_dev->delayr = (tms & 0xff) + ((tms >> 8) & 0x0f);
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        mem_dev->delayw = ((tms >> 12)  & 0x0f) + ((tms >> 16) & 0x0f) + ((tms >> 20) & 0x3f);
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      } else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {
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        mem_dev->delayr = 3 + ((tms >> 4) & 0x03);
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        mem_dev->delayw = 3 + ((tms >> 4) & 0x03);
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      } else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SSRAM) {
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        mem_dev->delayr = 2;
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        mem_dev->delayw = 2;
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      } else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
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        mem_dev->delayr = 2;
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        mem_dev->delayw = 2;
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      }
72 543 simons 
      return;
73 539 simons 
    }
74 
    mem_dev = mem_dev->next;
75 
  }
76 261 markom 
}
77 
 
78 
/* Set a specific MC register with value. */
79 1350 nogj 
void mc_write_word(oraddr_t addr, uint32_t value)
80 261 markom 
{
81 
        int chipsel;
82 
 
83 1350 nogj 
        debug(5, "mc_write_word(%"PRIxADDR",%08"PRIx32")\n", addr, value);
84 261 markom 
 
85 
  addr -= config.mc.baseaddr;
86 
 
87 
        switch (addr) {
88 
          case MC_CSR:
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            mc.csr = value;
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            break;
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          case MC_POC:
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            fprintf (stderr, "warning: write to MC's POC register!");
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            break;
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          case MC_BA_MASK:
95 539 simons 
            mc.ba_mask = value & MC_BA_MASK_VALID;
96 543 simons 
      for (chipsel = 0; chipsel < N_CE; chipsel++)
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        set_csc_tms (chipsel, mc.csc[chipsel], mc.tms[chipsel]);
98 261 markom 
            break;
99 
                default:
100 
                  if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {
101 
                    addr -= MC_CSC(0);
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                    if ((addr >> 2) & 1)
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                      mc.tms[addr >> 3] = value;
104 
                    else
105 
                      mc.csc[addr >> 3] = value;
106 
 
107 
                    set_csc_tms (addr >> 3, mc.csc[addr >> 3], mc.tms[addr >> 3]);
108 
                    break;
109 
                  } else
110 1350 nogj 
                        debug(1, "write out of range (addr %"PRIxADDR")\n", addr + config.mc.baseaddr);
111 261 markom 
        }
112 
}
113 
 
114 
/* Read a specific MC register. */
115 1350 nogj 
uint32_t mc_read_word(oraddr_t addr)
116 261 markom 
{
117 1350 nogj 
        uint32_t value = 0;
118 261 markom 
 
119 1350 nogj 
        debug(5, "mc_read_word(%"PRIxADDR")", addr);
120 261 markom 
 
121 
  addr -= config.mc.baseaddr;
122 
 
123 
        switch (addr) {
124 
          case MC_CSR:
125 
            value = mc.csr;
126 
            break;
127 
          case MC_POC:
128 
            value = mc.poc;
129 
            break;
130 
          case MC_BA_MASK:
131 
            value = mc.ba_mask;
132 
            break;
133 
                default:
134 
                  if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {
135 
                    addr -= MC_CSC(0);
136 
                    if ((addr >> 2) & 1)
137 
                      value = mc.tms[addr >> 3];
138 
                    else
139 
                      value = mc.csc[addr >> 3];
140 
                  } else
141 1350 nogj 
                        debug(1, " read out of range (addr %"PRIxADDR")\n", addr + config.mc.baseaddr);
142 261 markom 
            break;
143 
        }
144 1350 nogj 
        debug(5, " value(%"PRIx32")\n", value);
145 261 markom 
        return value;
146 
}
147 
 
148 
/* Read POC register and init memory controler regs. */
149 
void mc_reset()
150 
{
151 543 simons 
  struct dev_memarea *mem_dev = dev_list;
152 
 
153 261 markom 
  if (config.mc.enabled) {
154 997 markom 
        PRINTF("Resetting memory controller.\n");
155 261 markom 
        memset(&mc, 0, sizeof(struct mc));
156 
 
157 
    mc.poc = config.mc.POC;
158 539 simons 
 
159 
    /* Set CS0 */
160 
    mc.csc[0] = (((config.mc.POC & 0x0c) >> 2) << MC_CSC_MEMTYPE_OFFSET) | ((config.mc.POC & 0x03) << MC_CSC_BW_OFFSET) | 1;
161 
 
162 
    if ((mc.csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {
163 
      mc.tms[0] = MC_TMS_ASYNC_VALID;
164 
    } else if ((mc.csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {
165 
      mc.tms[0] = MC_TMS_SDRAM_VALID;
166 
    } else if ((mc.csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SSRAM) {
167 
      mc.tms[0] = MC_TMS_SSRAM_VALID;
168 
    } else if ((mc.csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
169 
      mc.tms[0] = MC_TMS_SYNC_VALID;
170 
    }
171 
 
172 543 simons 
    while (mem_dev) {
173 
      mem_dev->valid = 0;
174 
      mem_dev = mem_dev->next;
175 
    }
176 
 
177 539 simons 
    set_csc_tms (0, mc.csc[0], mc.tms[0]);
178 
 
179 970 simons 
        register_memoryarea(config.mc.baseaddr, MC_ADDR_SPACE, 4, 1, mc_read_word, mc_write_word);
180 261 markom 
  }
181 
}
182 
 
183 
inline void mc_clock()
184 
{
185 
}
186 742 ivang 
 
187 
void mc_status()
188 
{
189 
    int i;
190 
 
191 1350 nogj 
    PRINTF( "\nMemory Controller at 0x%lX:\n", config.mc.baseaddr );
192 1308 phoenix 
    PRINTF( "POC: 0x%08lX\n", mc.poc );
193 
    PRINTF( "BAS: 0x%08lX\n", mc.ba_mask );
194 
    PRINTF( "CSR: 0x%08lX\n", mc.csr );
195 742 ivang 
 
196 
    for (i=0; i<N_CE; i++) {
197 1308 phoenix 
        PRINTF( "CE %02d -  CSC: 0x%08lX  TMS: 0x%08lX\n", i, mc.csc[i],
198 
               mc.tms[i]);
199 742 ivang 
    }
200 
}

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