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[/] [or1k/] [tags/] [stable_0_2_0_rc1/] [or1ksim/] [cpu/] [or1k/] [spr_dump.c] - Blame information for rev 1765

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1 1532 nogj 
/* spr_dump.c -- Dump given spr in human readable form
2 
   Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org
3 
 
4 
This file is part of OpenRISC 1000 Architectural Simulator.
5 
 
6 
This program is free software; you can redistribute it and/or modify
7 
it under the terms of the GNU General Public License as published by
8 
the Free Software Foundation; either version 2 of the License, or
9 
(at your option) any later version.
10 
 
11 
This program is distributed in the hope that it will be useful,
12 
but WITHOUT ANY WARRANTY; without even the implied warranty of
13 
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 
GNU General Public License for more details.
15 
 
16 
You should have received a copy of the GNU General Public License
17 
along with this program; if not, write to the Free Software
18 
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
19 
 
20 
#include <string.h>
21 
 
22 
#include "config.h"
23 
 
24 
#ifdef HAVE_INTTYPES_H
25 
#include <inttypes.h>
26 
#endif
27 
 
28 
#include "port.h"
29 
#include "arch.h"
30 
#include "abstract.h"
31 
#include "opcode/or32.h"
32 
#include "spr_defs.h"
33 
#include "execute.h"
34 
#include "debug.h"
35 1555 nogj 
#include "misc.h"
36 1532 nogj 
 
37 
DEFAULT_DEBUG_CHANNEL(spr);
38 
 
39 
struct spr_bit_def {
40 
  const char *name;
41 
  uorreg_t mask;
42 
};
43 
 
44 
struct spr_def {
45 
  uint16_t from_spr;
46 
  uint16_t to_spr;
47 
  const char *name;
48 
  const struct spr_bit_def *bits;
49 
};
50 
 
51 
/* One value spr */
52 
static const struct spr_bit_def spr_one_val[] = {
53 
 { "", 0xffffffff },
54 
 { NULL, 0 } };
55 
 
56 
/*---------------------------------------------------------[ System group ]---*/
57 
/* Supervisor register */
58 
static const struct spr_bit_def spr_sr[] = {
59 
 { "SR_CID", SPR_SR_CID },
60 
 { "SR_SUMRA", SPR_SR_SUMRA },
61 
 { "SR_FO", SPR_SR_FO },
62 
 { "SR_EPH", SPR_SR_EPH },
63 
 { "SR_DSX", SPR_SR_DSX },
64 
 { "SR_OVE", SPR_SR_OVE },
65 
 { "SR_OV", SPR_SR_OV },
66 
 { "SR_CY", SPR_SR_CY },
67 
 { "SR_F", SPR_SR_F },
68 
 { "SR_CE", SPR_SR_CE },
69 
 { "SR_IME", SPR_SR_IME },
70 
 { "SR_DME", SPR_SR_DME },
71 
 { "SR_ICE", SPR_SR_ICE },
72 
 { "SR_DCE", SPR_SR_DCE },
73 
 { "SR_IEE", SPR_SR_IEE },
74 
 { "SR_TEE", SPR_SR_TEE },
75 
 { "SR_SM", SPR_SR_SM },
76 
 { NULL, 0 } };
77 
 
78 
/* Version register */
79 
static const struct spr_bit_def spr_vr[] = {
80 
 { "VR_VER", SPR_VR_VER },
81 
 { "VR_REV", SPR_VR_REV },
82 
 { NULL, 0 } };
83 
 
84 
/* upr register */
85 
static const struct spr_bit_def spr_upr[] = {
86 
 { "UPR_UP", SPR_UPR_UP },
87 
 { "UPR_DCP", SPR_UPR_DCP },
88 
 { "UPR_ICP", SPR_UPR_ICP },
89 
 { "UPR_DMP", SPR_UPR_DMP },
90 
 { "UPR_IMP", SPR_UPR_IMP },
91 
 { "UPR_OB32P", SPR_UPR_OB32P },
92 
 { "UPR_OB64P", SPR_UPR_OB64P },
93 
 { "UPR_OF32P", SPR_UPR_OF32P },
94 
 { "UPR_OF64P", SPR_UPR_OF64P },
95 
 { "UPR_OV32P", SPR_UPR_OV32P },
96 
 { "UPR_OV64P", SPR_UPR_OV64P },
97 
 { "UPR_DUP", SPR_UPR_DUP },
98 
 { "UPR_PCUP", SPR_UPR_PCUP },
99 
 { "UPR_PMP", SPR_UPR_PMP },
100 
 { "UPR_PICP", SPR_UPR_PICP },
101 
 { "UPR_TTP", SPR_UPR_TTP },
102 
 { "UPR_SRP", SPR_UPR_SRP },
103 
 { "UPR_RES", SPR_UPR_RES },
104 
 { "UPR_CUST", SPR_UPR_CUST },
105 
 { NULL, 0 } };
106 
 
107 
/* dmmucfgr register */
108 
static const struct spr_bit_def spr_dmmucfgr[] = {
109 
 { "DMMUCFGR_NTW", SPR_DMMUCFGR_NTW },
110 
 { "DMMUCFGR_NTS", SPR_DMMUCFGR_NTS },
111 
 { "DMMUCFGR_NAE", SPR_DMMUCFGR_NAE },
112 
 { "DMMUCFGR_CRI", SPR_DMMUCFGR_CRI },
113 
 { "DMMUCFGR_PRI", SPR_DMMUCFGR_PRI },
114 
 { "DMMUCFGR_TEIRI", SPR_DMMUCFGR_TEIRI },
115 
 { "DMMUCFGR_HTR", SPR_DMMUCFGR_HTR },
116 
 { NULL, 0 } };
117 
 
118 
/* immucfgr register */
119 
static const struct spr_bit_def spr_immucfgr[] = {
120 
 { "IMMUCFGR_NTW", SPR_IMMUCFGR_NTW },
121 
 { "IMMUCFGR_NTS", SPR_IMMUCFGR_NTS },
122 
 { "IMMUCFGR_NAE", SPR_IMMUCFGR_NAE },
123 
 { "IMMUCFGR_CRI", SPR_IMMUCFGR_CRI },
124 
 { "IMMUCFGR_PRI", SPR_IMMUCFGR_PRI },
125 
 { "IMMUCFGR_TEIRI", SPR_IMMUCFGR_TEIRI },
126 
 { "IMMUCFGR_HTR", SPR_IMMUCFGR_HTR },
127 
 { NULL, 0 } };
128 
 
129 
/* dccfgr register */
130 
static const struct spr_bit_def spr_dccfgr[] = {
131 
 { "DCCFGR_NCW", SPR_DCCFGR_NCW },
132 
 { "DCCFGR_NCS", SPR_DCCFGR_NCS },
133 
 { "DCCFGR_CBS", SPR_DCCFGR_CBS },
134 
 { "DCCFGR_CWS", SPR_DCCFGR_CWS },
135 
 { "DCCFGR_CCRI", SPR_DCCFGR_CCRI },
136 
 { "DCCFGR_CBIRI", SPR_DCCFGR_CBIRI },
137 
 { "DCCFGR_CBPRI", SPR_DCCFGR_CBPRI },
138 
 { "DCCFGR_CBLRI", SPR_DCCFGR_CBLRI },
139 
 { "DCCFGR_CBFRI", SPR_DCCFGR_CBFRI },
140 
 { "DCCFGR_CBWBRI", SPR_DCCFGR_CBWBRI },
141 
 { NULL, 0 } };
142 
 
143 
/* iccfgr register */
144 
static const struct spr_bit_def spr_iccfgr[] = {
145 
 { "ICCFGR_NCW", SPR_ICCFGR_NCW },
146 
 { "ICCFGR_NCS", SPR_ICCFGR_NCS },
147 
 { "ICCFGR_CBS", SPR_ICCFGR_CBS },
148 
 { "ICCFGR_CCRI", SPR_ICCFGR_CCRI },
149 
 { "ICCFGR_CBIRI", SPR_ICCFGR_CBIRI },
150 
 { "ICCFGR_CBPRI", SPR_ICCFGR_CBPRI },
151 
 { "ICCFGR_CBLRI", SPR_ICCFGR_CBLRI },
152 
 { NULL, 0 } };
153 
 
154 
/* System group */
155 
static const struct spr_def spr_sys_group[] = {
156 
 /* 000-000 */ { 0x000, 0x000, "SPR_VR", spr_vr },
157 
 /* 001-001 */ { 0x001, 0x001, "SPR_UPR", spr_upr },
158 
 /* 003-003 */ { 0x003, 0x003, "SPR_DMMUCFGR", spr_dmmucfgr },
159 
 /* 004-004 */ { 0x004, 0x004, "SPR_IMMUCFGR", spr_immucfgr },
160 
 /* 005-005 */ { 0x005, 0x005, "SPR_DCCFGR", spr_dccfgr },
161 
 /* 006-006 */ { 0x006, 0x006, "SPR_ICCFGR", spr_iccfgr },
162 
 /* 010-010 */ { 0x010, 0x010, "SPR_NPC", spr_one_val },
163 
 /* 011-011 */ { 0x011, 0x011, "SPR_SR", spr_sr },
164 
 /* 012-012 */ { 0x012, 0x012, "SPR_PPC", spr_one_val },
165 
 /* 020-02f */ { 0x020, 0x02f, "SPR_EPCR(%i)", spr_one_val },
166 
 /* 030-03f */ { 0x030, 0x03f, "SPR_EEAR(%i)", spr_one_val },
167 
 /* 040-04f */ { 0x040, 0x04f, "SPR_ESR(%i)", spr_sr },
168 
 /* 400-41f */ { 0x400, 0x41f, "GPR(%i)", spr_one_val },
169 
 /* ----- */ { -1, -1, NULL, NULL } };
170 
 
171 
/*-----------------------------------------------------------[ DMMU group ]---*/
172 
/* Data MMU conrtol reg */
173 
static const struct spr_bit_def spr_dmmucr[] = {
174 
 { "DMMUCR_P2S", SPR_DMMUCR_P2S },
175 
 { "DMMUCR_P1S", SPR_DMMUCR_P1S },
176 
 { "DMMUCR_VADDR_WIDTH", SPR_DMMUCR_VADDR_WIDTH },
177 
 { "DMMUCR_PADDR_WIDTH", SPR_DMMUCR_PADDR_WIDTH },
178 
 { NULL, 0 } };
179 
 
180 
/* dtlbmr register */
181 
static const struct spr_bit_def spr_dtlbmr[] = {
182 
 { "DTLBMR_V", SPR_DTLBMR_V },
183 
 { "DTLBMR_PL1", SPR_DTLBMR_PL1 },
184 
 { "DTLBMR_CID", SPR_DTLBMR_CID },
185 
 { "DTLBMR_LRU", SPR_DTLBMR_LRU },
186 
 { "DTLBMR_VPN", SPR_DTLBMR_VPN },
187 
 { NULL, 0 } };
188 
 
189 
/* dtlbtr register */
190 
static const struct spr_bit_def spr_dtlbtr[] = {
191 
 { "DTLBTR_CC", SPR_DTLBTR_CC },
192 
 { "DTLBTR_CI", SPR_DTLBTR_CI },
193 
 { "DTLBTR_WBC", SPR_DTLBTR_WBC },
194 
 { "DTLBTR_WOM", SPR_DTLBTR_WOM },
195 
 { "DTLBTR_A", SPR_DTLBTR_A },
196 
 { "DTLBTR_D", SPR_DTLBTR_D },
197 
 { "DTLBTR_URE", SPR_DTLBTR_URE },
198 
 { "DTLBTR_UWE", SPR_DTLBTR_UWE },
199 
 { "DTLBTR_SRE", SPR_DTLBTR_SRE },
200 
 { "DTLBTR_SWE", SPR_DTLBTR_SWE },
201 
 { "DTLBTR_PPN", SPR_DTLBTR_PPN },
202 
 { NULL, 0 } };
203 
 
204 
/* DMMU group */
205 
static const struct spr_def spr_dmmu_group[] = {
206 
 /* 000-000 */ { 0, 0, "SPR_DMMUCR", spr_dmmucr },
207 
 /* 200-27f */ { 0x200, 0x27f, "SPR_DTLBMR way 0 set %i", spr_dtlbmr },
208 
 /* 280-2ff */ { 0x280, 0x2ff, "SPR_DTLBTR way 0 set %i", spr_dtlbtr },
209 
 /* 300-37f */ { 0x300, 0x37f, "SPR_DTLBMR way 1 set %i", spr_dtlbmr },
210 
 /* 380-3ff */ { 0x380, 0x3ff, "SPR_DTLBTR way 1 set %i", spr_dtlbtr },
211 
 /* 400-47f */ { 0x400, 0x47f, "SPR_DTLBMR way 2 set %i", spr_dtlbmr },
212 
 /* 480-4ff */ { 0x480, 0x4ff, "SPR_DTLBTR way 2 set %i", spr_dtlbtr },
213 
 /* 500-57f */ { 0x500, 0x57f, "SPR_DTLBMR way 3 set %i", spr_dtlbmr },
214 
 /* 580-5ff */ { 0x580, 0x5ff, "SPR_DTLBTR way 3 set %i", spr_dtlbtr },
215 
 /* ------- */ { -1, -1, NULL, NULL } };
216 
 
217 
/*-----------------------------------------------------------[ IMMU group ]---*/
218 
/* Instruction MMU conrtol reg */
219 
static const struct spr_bit_def spr_immucr[] = {
220 
 { "IMMUCR_P2S", SPR_IMMUCR_P2S },
221 
 { "IMMUCR_P1S", SPR_IMMUCR_P1S },
222 
 { "IMMUCR_VADDR_WIDTH", SPR_IMMUCR_VADDR_WIDTH },
223 
 { "IMMUCR_PADDR_WIDTH", SPR_IMMUCR_PADDR_WIDTH },
224 
 { NULL, 0 } };
225 
 
226 
/* itlbmr register */
227 
static const struct spr_bit_def spr_itlbmr[] = {
228 
 { "ITLBMR_V", SPR_ITLBMR_V },
229 
 { "ITLBMR_PL1", SPR_ITLBMR_PL1 },
230 
 { "ITLBMR_CID", SPR_ITLBMR_CID },
231 
 { "ITLBMR_LRU", SPR_ITLBMR_LRU },
232 
 { "ITLBMR_VPN", SPR_ITLBMR_VPN },
233 
 { NULL, 0 } };
234 
 
235 
/* itlbtr register */
236 
static const struct spr_bit_def spr_itlbtr[] = {
237 
 { "ITLBTR_CC", SPR_ITLBTR_CC },
238 
 { "ITLBTR_CI", SPR_ITLBTR_CI },
239 
 { "ITLBTR_WBC", SPR_ITLBTR_WBC },
240 
 { "ITLBTR_WOM", SPR_ITLBTR_WOM },
241 
 { "ITLBTR_A", SPR_ITLBTR_A },
242 
 { "ITLBTR_D", SPR_ITLBTR_D },
243 
 { "ITLBTR_URE", SPR_ITLBTR_SXE },
244 
 { "ITLBTR_UWE", SPR_ITLBTR_UXE },
245 
 { "ITLBTR_PPN", SPR_ITLBTR_PPN },
246 
 { NULL, 0 } };
247 
 
248 
/* IMMU group */
249 
static const struct spr_def spr_immu_group[] = {
250 
 /* 000-000 */ { 0, 0, "SPR_IMMUCR", spr_immucr },
251 
 /* 200-27f */ { 0x200, 0x27f, "SPR_ITLBMR way 0 set %i", spr_itlbmr },
252 
 /* 280-2ff */ { 0x280, 0x2ff, "SPR_ITLBTR way 0 set %i", spr_itlbtr },
253 
 /* 300-37f */ { 0x300, 0x37f, "SPR_ITLBMR way 1 set %i", spr_itlbmr },
254 
 /* 380-3ff */ { 0x380, 0x3ff, "SPR_ITLBTR way 1 set %i", spr_itlbtr },
255 
 /* 400-47f */ { 0x400, 0x47f, "SPR_ITLBMR way 2 set %i", spr_itlbmr },
256 
 /* 480-4ff */ { 0x480, 0x4ff, "SPR_ITLBTR way 2 set %i", spr_itlbtr },
257 
 /* 500-57f */ { 0x500, 0x57f, "SPR_ITLBMR way 3 set %i", spr_itlbmr },
258 
 /* 580-5ff */ { 0x580, 0x5ff, "SPR_ITLBTR way 3 set %i", spr_itlbtr },
259 
 /* ------- */ { -1, -1, NULL, NULL } };
260 
 
261 
/*-----------------------------------------------------[ Data cache group ]---*/
262 
static const struct spr_bit_def spr_dccr[] = {
263 
 { "DCCR_EW", SPR_DCCR_EW },
264 
 { NULL, 0 } };
265 
 
266 
static const struct spr_def spr_dc_group[] = {
267 
 /* 000-000 */ { 0x000, 0x000, "SPR_DCCR", spr_dccr },
268 
 /* 001-001 */ { 0x001, 0x001, "SPR_DCBPR", spr_one_val },
269 
 /* 002-002 */ { 0x002, 0x002, "SPR_DCBFR", spr_one_val },
270 
 /* 003-003 */ { 0x003, 0x003, "SPR_DCBIR", spr_one_val },
271 
 /* 004-004 */ { 0x004, 0x004, "SPR_DCBWR", spr_one_val },
272 
 /* 005-005 */ { 0x005, 0x005, "SPR_DCBLR", spr_one_val },
273 
 /* 200-3ff */ { 0x200, 0x3ff, "SPR_DCR way 0 set %i", spr_one_val },
274 
 /* 400-5ff */ { 0x400, 0x5ff, "SPR_DCR way 1 set %i", spr_one_val },
275 
 /* 600-7ff */ { 0x600, 0x7ff, "SPR_DCR way 2 set %i", spr_one_val },
276 
 /* 800-9ff */ { 0x800, 0x9ff, "SPR_DCR way 3 set %i", spr_one_val },
277 
 /* ------- */ { -1, -1, NULL, NULL } };
278 
 
279 
/*----------------------------------------------[ Instruction cache group ]---*/
280 
static const struct spr_bit_def spr_iccr[] = {
281 
 { "ICCR_EW", SPR_ICCR_EW },
282 
 { NULL, 0 } };
283 
 
284 
static const struct spr_def spr_ic_group[] = {
285 
 /* 000-000 */ { 0x000, 0x000, "SPR_ICCR", spr_iccr },
286 
 /* 001-001 */ { 0x001, 0x001, "SPR_ICBPR", spr_one_val },
287 
 /* 002-002 */ { 0x002, 0x002, "SPR_ICBFR", spr_one_val },
288 
 /* 003-003 */ { 0x003, 0x003, "SPR_ICBIR", spr_one_val },
289 
 /* 200-3ff */ { 0x200, 0x3ff, "SPR_ICR way 0 set %i", spr_one_val },
290 
 /* 400-5ff */ { 0x400, 0x5ff, "SPR_ICR way 1 set %i", spr_one_val },
291 
 /* 600-7ff */ { 0x600, 0x7ff, "SPR_ICR way 2 set %i", spr_one_val },
292 
 /* 800-9ff */ { 0x800, 0x9ff, "SPR_ICR way 3 set %i", spr_one_val },
293 
 /* ------- */ { -1, -1, NULL, NULL } };
294 
 
295 
/*------------------------------------------------------------[ MAC group ]---*/
296 
static const struct spr_def spr_mac_group[] = {
297 
 /* 1-1 */ { 0x1, 0x1, "SPR_MACLO", spr_one_val },
298 
 /* 2-2 */ { 0x2, 0x2, "SPR_MACHI", spr_one_val },
299 
 /* ------- */ { -1, -1, NULL, NULL } };
300 
 
301 
/*----------------------------------------------------------[ Debug group ]---*/
302 
/* dmr1 register */
303 
static const struct spr_bit_def spr_dmr1[] = {
304 
 { "DMR1_CW0", SPR_DMR1_CW0 },
305 
 { "DMR1_CW1", SPR_DMR1_CW1 },
306 
 { "DMR1_CW2", SPR_DMR1_CW2 },
307 
 { "DMR1_CW3", SPR_DMR1_CW3 },
308 
 { "DMR1_CW4", SPR_DMR1_CW4 },
309 
 { "DMR1_CW5", SPR_DMR1_CW5 },
310 
 { "DMR1_CW6", SPR_DMR1_CW6 },
311 
 { "DMR1_CW7", SPR_DMR1_CW7 },
312 
 { "DMR1_CW8", SPR_DMR1_CW8 },
313 
 { "DMR1_CW9", SPR_DMR1_CW9 },
314 
 { "DMR1_CW10", SPR_DMR1_CW10 },
315 
 { "DMR1_ST", SPR_DMR1_ST },
316 
 { "DMR1_BT", SPR_DMR1_BT },
317 
 { "DMR1_DXFW", SPR_DMR1_DXFW },
318 
 { NULL, 0 } };
319 
 
320 
/* dmr2 register */
321 
static const struct spr_bit_def spr_dmr2[] = {
322 
 { "DMR2_WCE0", SPR_DMR2_WCE0 },
323 
 { "DMR2_WCE1", SPR_DMR2_WCE1 },
324 
 { "DMR2_AWTC", SPR_DMR2_AWTC },
325 
 { "DMR2_WGB", SPR_DMR2_WGB },
326 
 { NULL, 0 } };
327 
 
328 
/* dwcr register */
329 
static const struct spr_bit_def spr_dwcr[] = {
330 
 { "DWCR_COUNT", SPR_DWCR_COUNT },
331 
 { "DWCR_MATCH", SPR_DWCR_MATCH },
332 
 { NULL, 0 } };
333 
 
334 
/* dsr register */
335 
static const struct spr_bit_def spr_dsr[] = {
336 
 { "DSR_RSTE", SPR_DSR_RSTE },
337 
 { "DSR_BUSE", SPR_DSR_BUSEE },
338 
 { "DSR_DPFE", SPR_DSR_DPFE },
339 
 { "DSR_IPFE", SPR_DSR_IPFE },
340 
 { "DSR_TTE", SPR_DSR_TTE },
341 
 { "DSR_AE", SPR_DSR_AE },
342 
 { "DSR_IIE", SPR_DSR_IIE },
343 
 { "DSR_IE", SPR_DSR_IE },
344 
 { "DSR_DME", SPR_DSR_DME },
345 
 { "DSR_IME", SPR_DSR_IME },
346 
 { "DSR_RE", SPR_DSR_RE },
347 
 { "DSR_SCE", SPR_DSR_SCE },
348 
 { "DSR_SSE", SPR_DSR_SSE },
349 
 { "DSR_TE", SPR_DSR_TE },
350 
 { NULL, 0 } };
351 
 
352 
/* drr register */
353 
static const struct spr_bit_def spr_drr[] = {
354 
 { "DRR_RSTE", SPR_DRR_RSTE },
355 
 { "DRR_BUSE", SPR_DRR_BUSEE },
356 
 { "DRR_DPFE", SPR_DRR_DPFE },
357 
 { "DRR_IPFE", SPR_DRR_IPFE },
358 
 { "DRR_TTE", SPR_DRR_TTE },
359 
 { "DRR_AE", SPR_DRR_AE },
360 
 { "DRR_IIE", SPR_DRR_IIE },
361 
 { "DRR_IE", SPR_DRR_IE },
362 
 { "DRR_DME", SPR_DRR_DME },
363 
 { "DRR_IME", SPR_DRR_IME },
364 
 { "DRR_RE", SPR_DRR_RE },
365 
 { "DRR_SCE", SPR_DRR_SCE },
366 
 { "DRR_TE", SPR_DRR_TE },
367 
 { NULL, 0 } };
368 
 
369 
/* Debug group */
370 
static const struct spr_def spr_d_group[] = {
371 
#if 0
372 
 /* 00-07 */ { 0x00, 0x07, "SPR_DVR(%i)", spr_dvr },
373 
 /* 08-0f */ { 0x08, 0x0f, "SPR_DCR(%i)", spr_dcr },
374 
#endif
375 
 /* 10-10 */ { 0x10, 0x10, "SPR_DMR1", spr_dmr1 },
376 
 /* 11-11 */ { 0x11, 0x11, "SPR_DMR2", spr_dmr2 },
377 
 /* 12-12 */ { 0x12, 0x12, "SPR_DWCR0", spr_dwcr },
378 
 /* 13-13 */ { 0x13, 0x13, "SPR_DWCR1", spr_dwcr },
379 
 /* 14-14 */ { 0x14, 0x14, "SPR_DSR", spr_dsr },
380 
 /* 15-15 */ { 0x15, 0x15, "SPR_DRR", spr_drr },
381 
 /* ----- */ { -1, -1, NULL, NULL } };
382 
 
383 
/*-------------------------------------------[ Performance counters group ]---*/
384 
static const struct spr_bit_def spr_pcmr[] = {
385 
 { "PCMR_CP", SPR_PCMR_CP },
386 
 { "PCMR_UMRA", SPR_PCMR_UMRA },
387 
 { "PCMR_CISM", SPR_PCMR_CISM },
388 
 { "PCMR_CIUM", SPR_PCMR_CIUM },
389 
 { "PCMR_LA", SPR_PCMR_LA },
390 
 { "PCMR_SA", SPR_PCMR_SA },
391 
 { "PCMR_IF", SPR_PCMR_IF },
392 
 { "PCMR_DCM", SPR_PCMR_DCM },
393 
 { "PCMR_ICM", SPR_PCMR_ICM },
394 
 { "PCMR_IFS", SPR_PCMR_IFS },
395 
 { "PCMR_LSUS", SPR_PCMR_LSUS },
396 
 { "PCMR_BS", SPR_PCMR_BS },
397 
 { "PCMR_DTLBM", SPR_PCMR_DTLBM },
398 
 { "PCMR_ITLBM", SPR_PCMR_ITLBM },
399 
 { "PCMR_DDS", SPR_PCMR_DDS },
400 
 { "PCMR_WPE", SPR_PCMR_WPE },
401 
 { NULL, 0 } };
402 
 
403 
static const struct spr_def spr_pc_group[] = {
404 
 /* 00-07 */ { 0x00, 0x07, "PCCR", spr_one_val },
405 
 /* 08-0f */ { 0x08, 0x0f, "PCMR", spr_pcmr },
406 
 /* ----- */ { -1, -1, NULL, NULL } };
407 
 
408 
/*------------------------------------------------[ Power managment group ]---*/
409 
static const struct spr_bit_def spr_pmr[] = {
410 
 { "PMR_SDF", SPR_PMR_SDF },
411 
 { "PMR_DME", SPR_PMR_DME },
412 
 { "PMR_SME", SPR_PMR_SME },
413 
 { "PMR_DCGE", SPR_PMR_DCGE },
414 
 { "PMR_SUME", SPR_PMR_SUME },
415 
 { NULL, 0 } };
416 
 
417 
static const struct spr_def spr_pm_group[] = {
418 
 /* 0-0 */ { 0x0, 0x0, "SPR_PMR", spr_pmr },
419 
 /* --- */ { -1, -1, NULL, NULL } };
420 
 
421 
/*------------------------------------------------------------[ PIC group ]---*/
422 
/* picmr register */
423 
static const struct spr_bit_def spr_picmr[] = {
424 
 { "PICMR_IUM", SPR_PICMR_IUM },
425 
 { NULL, 0 } };
426 
 
427 
static const struct spr_def spr_pic_group[] = {
428 
 /* 0-0 */ { 0, 0, "PICMR", spr_picmr },
429 
 /* 2-2 */ { 2, 2, "PICSR", spr_one_val },
430 
 /* --- */ { -1, -1, NULL, NULL } };
431 
 
432 
/*-----------------------------------------------------[ Tick timer group ]---*/
433 
static const struct spr_bit_def spr_ttmr[] = {
434 
 { "TTMR_PERIOD", SPR_TTMR_PERIOD },
435 
 { "TTMR_IP", SPR_TTMR_IP },
436 
 { "TTMR_IE", SPR_TTMR_IE },
437 
 { "TTMR_M", SPR_TTMR_M },
438 
 { NULL, 0 } };
439 
 
440 
static const struct spr_def spr_tt_group[] = {
441 
 /* 0-0 */ { 0, 0, "TTMR", spr_ttmr },
442 
 /* 1-1 */ { 0, 0, "TTCR", spr_one_val },
443 
 /* --- */ { -1, -1, NULL, NULL } };
444 
 
445 
/* Spr groups */
446 
static const struct spr_def *spr_groups[] = {
447 
 /* 00 */ spr_sys_group,
448 
 /* 01 */ spr_dmmu_group,
449 
 /* 02 */ spr_immu_group,
450 
 /* 03 */ spr_dc_group,
451 
 /* 04 */ spr_ic_group,
452 
 /* 05 */ spr_mac_group,
453 
 /* 06 */ spr_d_group,
454 
 /* 07 */ spr_pc_group,
455 
 /* 08 */ spr_pm_group,
456 
 /* 09 */ spr_pic_group,
457 
 /* 0a */ spr_tt_group };
458 
 
459 
/* Should be long enough for everything */
460 
static char ret_spr[1000];
461 
 
462 
/* Dumps the given spr in nice, human readable form */
463 
char *dump_spr(uint16_t spr, uorreg_t spr_val)
464 
{
465 
  const struct spr_def *spr_def;
466 
  uint16_t spr_in_group = spr & (MAX_SPRS_PER_GRP - 1);
467 
  uint16_t spr_group = spr >> MAX_SPRS_PER_GRP_BITS;
468 
  const struct spr_bit_def *spr_bit_def;
469 
 
470 
  int first_bit = 1;
471 
  int i;
472 
  uorreg_t tmp;
473 
 
474 
  spr_def = spr_groups[spr_group];
475 
 
476 
  /* Find the given spr */
477 
  for(; spr_def->from_spr != 0xffff; spr_def++) {
478 
    if((spr_def->from_spr <= spr_in_group) && (spr_def->to_spr >= spr_in_group))
479 
      break;
480 
  }
481 
 
482 
  if(spr_def->from_spr == 0xffff) {
483 
    sprintf(ret_spr, "Spr %"PRIx16", group %"PRIx16" = 0x%"PRIxREG"\n",
484 
            spr_in_group, spr_group, spr_val);
485 
    return ret_spr;
486 
  }
487 
 
488 
  /* Decode the spr bits and show them in a pretty format */
489 
  if(spr_def->from_spr == spr_def->to_spr)
490 
    sprintf(ret_spr, "%s", spr_def->name);
491 
  else
492 
    sprintf(ret_spr, spr_def->name, spr_in_group - spr_def->from_spr);
493 
  strcat(ret_spr, " = ");
494 
 
495 
  /* First get all the single-bit bit fields and dump them */
496 
  for(spr_bit_def = spr_def->bits; spr_bit_def->name; spr_bit_def++) {
497 
    if(!is_power2(spr_bit_def->mask))
498 
      continue;
499 
 
500 
    if(!(spr_bit_def->mask & spr_val))
501 
      continue;
502 
 
503 
    if(!first_bit)
504 
      strcat(ret_spr, " | ");
505 
    else
506 
      first_bit = 0;
507 
    strcat(ret_spr, spr_bit_def->name);
508 
  }
509 
 
510 
  /* Now dump all the multi-bit bit fields */
511 
  for(spr_bit_def = spr_def->bits; spr_bit_def->name; spr_bit_def++) {
512 
    if(is_power2(spr_bit_def->mask))
513 
      continue;
514 
    if(!first_bit)
515 
      strcat(ret_spr, " | ");
516 
    else
517 
      first_bit = 0;
518 
    for(tmp = spr_bit_def->mask, i = 0; !(tmp & 1); i++)
519 
      tmp >>= 1;
520 
 
521 
    sprintf(ret_spr, "%s%s = %x", ret_spr, spr_bit_def->name,
522 
            (spr_val >> i) & tmp);
523 
  }
524 
  return ret_spr;
525 
}
526 
 

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