1 |
879 |
markom |
/* verilog.c -- OpenRISC Custom Unit Compiler, verilog generator
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2 |
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* Copyright (C) 2002 Marko Mlinar, markom@opencores.org
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*
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* This file is part of OpenRISC 1000 Architectural Simulator.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdarg.h>
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#include <assert.h>
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#include "cuc.h"
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#include "insn.h"
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/* Find index of load/store */
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int find_ls_index (cuc_func *f, int ref)
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{
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int c = 0;
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int i;
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int load = II_IS_LOAD (f->INSN(ref).index);
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for (i = 0; i < f->nmsched; i++) {
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if (f->msched[i] == ref) break;
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if (load && (!(f->mtype[i] & MT_WRITE))
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|| !load && (f->mtype[i] & MT_WRITE)) c++;
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}
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return c;
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}
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/* Print out dependencies as verilog expression */
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void print_deps (FILE *fo, cuc_func *f, int b, dep_list *t, int registered)
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{
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44 |
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if (t) {
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int first = 0;
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while (t) {
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883 |
markom |
if (!(f->INSN(t->ref).type & IT_MEMORY)) printf ("print_deps: err %x\n", t->ref);
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879 |
markom |
assert (f->INSN(t->ref).type & IT_MEMORY);
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fprintf (fo, "%s%c_end[%i]", first ? " && " : "",
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II_IS_LOAD (f->INSN(t->ref).index) ? 'l' : 's', find_ls_index (f, t->ref));
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first = 1;
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t = t->next;
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}
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} else {
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if (registered) fprintf (fo, "bb_start_r[%i]", b);
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else fprintf (fo, "bb_start[%i]", b);
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}
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}
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char *print_op_v (cuc_func *f, char *s, int ref, int j)
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{
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unsigned long op = f->INSN(ref).op[j];
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unsigned long opt = f->INSN(ref).opt[j];
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switch (opt & ~OPT_DEST) {
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case OPT_NONE: assert (0); break;
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markom |
case OPT_CONST: if (f->INSN(ref).type & IT_COND) {
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assert (op == 0 || op == 1);
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sprintf (s, "1'b%x", op);
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} else sprintf (s, "32'h%x", op);
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break;
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879 |
markom |
case OPT_REGISTER:
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if (opt & OPT_DEST) sprintf (s, "t%x_%x", REF_BB(ref), REF_I(ref));
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else sprintf (s, "r%i_%c", op, opt & OPT_DEST ? 'o' : 'i');
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break;
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case OPT_REF: sprintf (s, "t%x_%x", REF_BB(op), REF_I(op)); break;
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}
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return s;
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}
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/* Prints out specified instruction */
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void print_insn_v (FILE *fo, cuc_func *f, int b, int i)
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{
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cuc_insn *ii = &f->bb[b].insn[i];
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char *s = known[ii->index].rtl;
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char tmp[200] = "";
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883 |
markom |
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879 |
markom |
while (*s) {
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if (*s <= MAX_OPERANDS) {
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char t[30];
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sprintf (tmp, "%s%s", tmp, print_op_v (f, t, REF(b, i), *s - 1));
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} else if (*s == '\b') sprintf (tmp, "%s%i", b);
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else sprintf (tmp, "%s%c", tmp, *s);
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s++;
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}
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fprintf (fo, "%-40s /* %s */\n", tmp, ii->disasm);
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if (ii->type & IT_MEMORY) {
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int j, nls = find_ls_index (f, REF (b, i));
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if (II_IS_LOAD (ii->index)) {
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int nm;
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for (nm = 0; nm < f->nmsched; nm++) if (f->msched[nm] == REF (b, i)) break;
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assert (nm < f->nmsched);
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fprintf (fo, " if (rst) t%x_%x <= #1 32'h0;\n", b, i);
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fprintf (fo, " else if (l_end[%i]) t%x_%x <= #1 ", nls, b, i);
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switch (f->mtype[nm] & (MT_WIDTH | MT_SIGNED)) {
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case 1: fprintf (fo, "lwb_dat_i & 32'hff;\n");
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break;
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case 2: fprintf (fo, "lwb_dat_i & 32'hffff;\n");
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break;
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case 4 | MT_SIGNED:
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case 4: fprintf (fo, "lwb_dat_i;\n");
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break;
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case 1 | MT_SIGNED:
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fprintf (fo, "{24{lwb_dat_i[7]}, lwb_dat_i[7:0]};\n");
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break;
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case 2 | MT_SIGNED:
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fprintf (fo, "{16{lwb_dat_i[15]}, lwb_dat_i[15:0]};\n");
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break;
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default: assert (0);
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}
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}
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} else if (ii->index == II_LRBB) {
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fprintf (fo, " if (rst) t%x_%x <= #1 1'b0;\n", b, i);
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assert (f->bb[b].prev[0] >= 0);
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fprintf (fo, " else if (bb_start[%i]) t%x_%x <= #1 bb_stb[%i];\n", b, b, i, f->bb[b].prev[0]);
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} else if (ii->index == II_REG) {
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fprintf (fo, " if (rst) t%x_%x <= #1 32'h0;\n", b, i);
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assert (ii->opt[1] == OPT_REF);
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fprintf (fo, " else if (");
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if (f->bb[b].mdep) print_deps (fo, f, b, f->bb[b].mdep, 0);
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else fprintf (fo, "bb_stb[%i]", b);
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fprintf (fo, ") t%x_%x <= #1 t%x_%x;\n", b, i,
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REF_BB (ii->op[1]), REF_I (ii->op[1]));
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}
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}
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/* Outputs binary number */
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char *bin_str (unsigned long x, int len)
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{
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static char bx[33];
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char *s = bx;
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while (len > 0) *s++ = '0' + ((x >> --len) & 1);
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*s = '\0';
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return bx;
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}
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147 |
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/* Returns index of branch instruction inside a block b */
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int branch_index (cuc_bb *bb)
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{
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int i;
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for (i = bb->ninsn - 1; i >= 0; i--)
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if (bb->insn[i].type & IT_BRANCH) return i;
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return -1;
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}
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156 |
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/* Generates verilog file out of insn dataflow */
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void output_verilog (cuc_func *f, char *filename)
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{
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FILE *fo;
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int b, i, j;
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int ci = 0, co = 0;
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int nloads = 0, nstores = 0;
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char tmp[256];
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cuc_bb *end_bb = NULL;
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int end_bb_no = -1;
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sprintf (tmp, "%s.v", filename);
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168 |
902 |
markom |
log ("Generating verilog file \"%s\"\n", tmp);
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printf ("Generating verilog file \"%s\"\n", tmp);
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170 |
879 |
markom |
if ((fo = fopen (tmp, "wt+")) == NULL) {
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fprintf (stderr, "Cannot open '%s'\n", tmp);
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exit (1);
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}
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175 |
883 |
markom |
for (b = 0; b < f->num_bb; b++)
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879 |
markom |
if (f->bb[b].type & BB_END) end_bb = &f->bb[end_bb_no = b];
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assert (end_bb && end_bb->type & BB_END);
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178 |
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179 |
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/* output header */
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180 |
902 |
markom |
fprintf (fo, "/* %s -- generated by OpenRISC Custom Unit Compiler\n", tmp);
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fprintf (fo, " (C) 2002 OpenCores.\n");
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182 |
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fprintf (fo, " function \"%s\"\n", filename);
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fprintf (fo, " at %08x - %08x\n", f->start_addr, f->end_addr);
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fprintf (fo, " num BBs %i */\n\n", f->num_bb);
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185 |
879 |
markom |
fprintf (fo, "module %s (clk, rst,\n", filename);
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186 |
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fprintf (fo, " lwb_adr_o, lwb_dat_i, lwb_cycstb_o,\n");
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187 |
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fprintf (fo, " lwb_sel_o, lwb_linbrst_o, lwb_ack_i,\n");
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188 |
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fprintf (fo, " swb_adr_o, swb_dat_o, swb_cycstb_o,\n");
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189 |
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fprintf (fo, " swb_sel_o, swb_linbrst_o, swb_ack_i,\n");
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190 |
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191 |
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fprintf (fo, "/* inputs */ ");
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192 |
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for (i = 0; i < MAX_REGS; i++)
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193 |
883 |
markom |
if (f->used_regs[i]) {
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194 |
879 |
markom |
fprintf (fo, "r%i_i, ", i);
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195 |
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ci++;
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196 |
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}
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197 |
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if (!ci) fprintf (fo, "/* NONE */");
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198 |
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199 |
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fprintf (fo, "\n/* outputs */ ");
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200 |
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for (i = 0; i < MAX_REGS; i++)
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201 |
883 |
markom |
if (f->lur[i] >= 0 && !f->saved_regs[i]) {
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202 |
879 |
markom |
fprintf (fo, "r%i_o, ", i);
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203 |
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co++;
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204 |
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}
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205 |
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206 |
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if (!co) fprintf (fo, "/* NONE */");
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207 |
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fprintf (fo, "\n start_i, end_o);\n\n");
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208 |
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209 |
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fprintf (fo, "input clk, rst;\n");
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210 |
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fprintf (fo, "input start_i;\t/* Module starts when set to 1 */ \n");
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211 |
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fprintf (fo, "output end_o;\t/* Set when module finishes, cleared upon start_i == 1 */\n\n");
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212 |
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fprintf (fo, "/* Bus signals */\n");
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213 |
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fprintf (fo, "output lwb_cycstb_o, swb_cycstb_o;\n");
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214 |
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fprintf (fo, "input lwb_ack_i, swb_ack_i;\n");
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215 |
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fprintf (fo, "output [3:0] lwb_sel_o, swb_sel_o;\n");
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216 |
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fprintf (fo, "output [31:0] lwb_adr_o, swb_adr_o;\n");
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217 |
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fprintf (fo, "output lwb_linbrst_o, swb_linbrst_o;\n");
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218 |
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fprintf (fo, "input [31:0] lwb_dat_i;\n");
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219 |
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fprintf (fo, "output [31:0] swb_dat_o;\n\n");
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220 |
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221 |
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fprintf (fo, "reg lwb_cycstb_o, swb_cycstb_o;\n");
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222 |
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fprintf (fo, "reg [31:0] lwb_adr_o, swb_adr_o;\n");
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223 |
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fprintf (fo, "reg [3:0] lwb_sel_o, swb_sel_o;\n");
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224 |
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fprintf (fo, "reg [31:0] swb_dat_o;\n");
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225 |
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fprintf (fo, "reg lwb_linbrst_o, swb_linbrst_o;\n");
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226 |
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227 |
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if (ci || co) fprintf (fo, "\n/* module ports */\n");
|
228 |
|
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if (ci) {
|
229 |
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int first = 1;
|
230 |
|
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fprintf (fo, "input [31:0]");
|
231 |
|
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for (i = 0; i < MAX_REGS; i++)
|
232 |
883 |
markom |
if (f->used_regs[i]) {
|
233 |
879 |
markom |
fprintf (fo, "%sr%i_i", first ? " " : ", ", i);
|
234 |
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first = 0;
|
235 |
|
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}
|
236 |
|
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fprintf (fo, ";\n");
|
237 |
|
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}
|
238 |
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|
239 |
|
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if (co) {
|
240 |
|
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int first = 1;
|
241 |
|
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fprintf (fo, "output [31:0]");
|
242 |
|
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for (i = 0; i < MAX_REGS; i++)
|
243 |
883 |
markom |
if (f->lur[i] >= 0 && !f->saved_regs[i]) {
|
244 |
879 |
markom |
fprintf (fo, "%sr%i_o", first ? " " : ", ", i);
|
245 |
|
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first = 0;
|
246 |
|
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}
|
247 |
|
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fprintf (fo, ";\n");
|
248 |
|
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}
|
249 |
|
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|
250 |
|
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/* Count loads & stores */
|
251 |
|
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for (i = 0; i < f->nmsched; i++)
|
252 |
|
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if (f->mtype[i] & MT_WRITE) nstores++;
|
253 |
|
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else nloads++;
|
254 |
|
|
|
255 |
|
|
/* Output internal registers for loads */
|
256 |
|
|
if (nloads) {
|
257 |
|
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int first = 1;
|
258 |
883 |
markom |
int num = 0;
|
259 |
879 |
markom |
fprintf (fo, "\n/* internal registers for loads */\n");
|
260 |
|
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for (i = 0; i < f->nmsched; i++)
|
261 |
|
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if (!(f->mtype[i] & MT_WRITE)) {
|
262 |
|
|
fprintf (fo, "%st%x_%x", first ? "reg [31:0] " : ", ",
|
263 |
|
|
REF_BB(f->msched[i]), REF_I(f->msched[i]));
|
264 |
883 |
markom |
|
265 |
|
|
if (num >= 8) {
|
266 |
|
|
fprintf (fo, ";\n");
|
267 |
|
|
first = 1;
|
268 |
|
|
num = 0;
|
269 |
|
|
} else {
|
270 |
|
|
first = 0;
|
271 |
|
|
num++;
|
272 |
|
|
}
|
273 |
879 |
markom |
}
|
274 |
|
|
if (!first) fprintf (fo, ";\n");
|
275 |
|
|
}
|
276 |
|
|
|
277 |
|
|
fprintf (fo, "\n/* 'zero or one' hot state machines */\n");
|
278 |
|
|
if (nloads) fprintf (fo, "reg [%i:0] l_stb; /* loads */\n", nloads - 1);
|
279 |
|
|
if (nstores) fprintf (fo, "reg [%i:0] s_stb; /* stores */\n", nstores - 1);
|
280 |
|
|
fprintf (fo, "reg [%i:0] bb_stb; /* basic blocks */\n", f->num_bb - 1);
|
281 |
|
|
|
282 |
|
|
{
|
283 |
883 |
markom |
int first = 2;
|
284 |
879 |
markom |
int num = 0;
|
285 |
|
|
for (b = 0; b < f->num_bb; b++)
|
286 |
|
|
for (i = 0; i < f->bb[b].ninsn; i++)
|
287 |
|
|
if (f->bb[b].insn[i].type & IT_COND
|
288 |
|
|
&& f->bb[b].insn[i].index != II_REG
|
289 |
|
|
&& f->bb[b].insn[i].index != II_LRBB) {
|
290 |
883 |
markom |
if (first == 2) fprintf (fo, "\n/* basic block condition wires */\n");
|
291 |
879 |
markom |
fprintf (fo, "%st%x_%x", first ? "wire " : ", ", b, i);
|
292 |
883 |
markom |
if (num >= 8) {
|
293 |
879 |
markom |
fprintf (fo, ";\n");
|
294 |
|
|
first = 1;
|
295 |
|
|
num = 0;
|
296 |
|
|
} else {
|
297 |
|
|
first = 0;
|
298 |
|
|
num++;
|
299 |
|
|
}
|
300 |
|
|
}
|
301 |
|
|
if (!first) fprintf (fo, ";\n");
|
302 |
|
|
|
303 |
|
|
fprintf (fo, "\n/* forward declaration of normal wires */\n");
|
304 |
|
|
num = 0;
|
305 |
|
|
first = 1;
|
306 |
|
|
for (b = 0; b < f->num_bb; b++)
|
307 |
|
|
for (i = 0; i < f->bb[b].ninsn; i++)
|
308 |
|
|
if (!(f->bb[b].insn[i].type & (IT_COND | IT_BRANCH))
|
309 |
|
|
&& f->bb[b].insn[i].index != II_REG
|
310 |
|
|
&& f->bb[b].insn[i].index != II_LRBB) {
|
311 |
|
|
/* Exclude loads */
|
312 |
|
|
if (f->bb[b].insn[i].type & IT_MEMORY && II_IS_LOAD (f->bb[b].insn[i].index)) continue;
|
313 |
|
|
fprintf (fo, "%st%x_%x", first ? "wire [31:0] " : ", ", b, i);
|
314 |
883 |
markom |
if (num >= 8) {
|
315 |
879 |
markom |
fprintf (fo, ";\n");
|
316 |
|
|
first = 1;
|
317 |
|
|
num = 0;
|
318 |
|
|
} else {
|
319 |
|
|
first = 0;
|
320 |
|
|
num++;
|
321 |
|
|
}
|
322 |
|
|
}
|
323 |
|
|
if (!first) fprintf (fo, ";\n");
|
324 |
|
|
|
325 |
|
|
fprintf (fo, "\n/* forward declaration registers */\n");
|
326 |
|
|
num = 0;
|
327 |
|
|
first = 1;
|
328 |
|
|
for (b = 0; b < f->num_bb; b++)
|
329 |
|
|
for (i = 0; i < f->bb[b].ninsn; i++)
|
330 |
|
|
if (f->bb[b].insn[i].index == II_REG
|
331 |
|
|
&& f->bb[b].insn[i].index != II_LRBB) {
|
332 |
|
|
fprintf (fo, "%st%x_%x", first ? "reg [31:0] " : ", ", b, i);
|
333 |
883 |
markom |
if (num >= 8) {
|
334 |
879 |
markom |
fprintf (fo, ";\n");
|
335 |
|
|
first = 1;
|
336 |
|
|
num = 0;
|
337 |
|
|
} else {
|
338 |
|
|
first = 0;
|
339 |
|
|
num++;
|
340 |
|
|
}
|
341 |
|
|
}
|
342 |
|
|
if (!first) fprintf (fo, ";\n");
|
343 |
|
|
|
344 |
|
|
num = 0;
|
345 |
|
|
first = 1;
|
346 |
|
|
for (b = 0; b < f->num_bb; b++)
|
347 |
|
|
for (i = 0; i < f->bb[b].ninsn; i++)
|
348 |
|
|
if (f->bb[b].insn[i].index != II_REG
|
349 |
|
|
&& f->bb[b].insn[i].index == II_LRBB) {
|
350 |
|
|
fprintf (fo, "%st%x_%x", first ? "reg " : ", ", b, i);
|
351 |
883 |
markom |
if (num >= 8) {
|
352 |
879 |
markom |
fprintf (fo, ";\n");
|
353 |
|
|
first = 1;
|
354 |
|
|
num = 0;
|
355 |
|
|
} else {
|
356 |
|
|
first = 0;
|
357 |
|
|
num++;
|
358 |
|
|
}
|
359 |
|
|
}
|
360 |
|
|
if (!first) fprintf (fo, ";\n");
|
361 |
|
|
}
|
362 |
|
|
|
363 |
|
|
if (nloads || nstores) fprintf (fo, "\n/* dependencies */\n");
|
364 |
|
|
if (nloads) fprintf (fo, "wire [%i:0] l_end = l_stb & {%i{lwb_ack_i}};\n",
|
365 |
|
|
nloads - 1, nloads);
|
366 |
|
|
if (nstores) fprintf (fo, "wire [%i:0] s_end = s_stb & {%i{swb_ack_i}};\n",
|
367 |
|
|
nstores - 1, nstores);
|
368 |
|
|
|
369 |
|
|
fprintf (fo, "\n/* last dependency */\n");
|
370 |
|
|
fprintf (fo, "wire end_o = bb_stb[%i]", end_bb_no);
|
371 |
|
|
if (end_bb->mdep) {
|
372 |
|
|
fprintf (fo, " && ");
|
373 |
|
|
print_deps (fo, f, end_bb_no, end_bb->mdep, 0);
|
374 |
|
|
}
|
375 |
|
|
/* Is there a loop right at end? */
|
376 |
|
|
if (end_bb->next[0] >= 0) {
|
377 |
|
|
int bidx = branch_index (end_bb);
|
378 |
|
|
char t[30];
|
379 |
|
|
print_op_v (f, t, REF (end_bb_no, bidx), 1);
|
380 |
|
|
fprintf (fo, " && !%s", t);
|
381 |
|
|
}
|
382 |
|
|
fprintf (fo, ";\n");
|
383 |
|
|
|
384 |
|
|
fprintf (fo, "\n/* Basic block triggers */\n");
|
385 |
|
|
fprintf (fo, "wire [%2i:0] bb_start = {\n", f->num_bb - 1);
|
386 |
|
|
for (b = f->num_bb - 1; b >= 0; b--) {
|
387 |
|
|
fprintf (fo, " /* bb_start[%2i] */ ", b);
|
388 |
|
|
if (f->bb[b].prev[0] < 0) fprintf (fo, "start_i");
|
389 |
|
|
else {
|
390 |
|
|
cuc_bb *prev = &f->bb[f->bb[b].prev[0]];
|
391 |
|
|
int t;
|
392 |
|
|
if (prev->mdep) {
|
393 |
|
|
print_deps (fo, f, f->bb[b].prev[0], prev->mdep, 0);
|
394 |
|
|
fprintf (fo, " && ");
|
395 |
|
|
}
|
396 |
|
|
fprintf (fo, "bb_stb[%i]", f->bb[b].prev[0]);
|
397 |
|
|
if (prev->next[0] >= 0 && prev->next[1] >= 0) {
|
398 |
|
|
int bidx = branch_index (&f->bb[f->bb[b].prev[0]]);
|
399 |
|
|
assert (bidx >= 0);
|
400 |
|
|
fprintf (fo, " && ");
|
401 |
|
|
t = prev->next[0] == b;
|
402 |
|
|
fprintf (fo, "%st%x_%x", t ? "" : "!", f->bb[b].prev[0], bidx);
|
403 |
|
|
}
|
404 |
|
|
if (f->bb[b].prev[1] >= 0) {
|
405 |
|
|
prev = &f->bb[f->bb[b].prev[1]];
|
406 |
|
|
fprintf (fo, "\n || ");
|
407 |
|
|
if (prev->mdep) {
|
408 |
|
|
print_deps (fo, f, f->bb[b].prev[1], prev->mdep, 0);
|
409 |
|
|
fprintf (fo, " && ");
|
410 |
|
|
}
|
411 |
|
|
fprintf (fo, "bb_stb[%i]", f->bb[b].prev[1]);
|
412 |
|
|
if (prev->next[0] >= 0 && prev->next[1] >= 0) {
|
413 |
|
|
int bidx = branch_index (&f->bb[f->bb[b].prev[1]]);
|
414 |
|
|
assert (bidx >= 0);
|
415 |
|
|
fprintf (fo, " && ");
|
416 |
|
|
t = prev->next[0] == b;
|
417 |
|
|
fprintf (fo, "%st%x_%x", t ? "" : "!", f->bb[b].prev[1], bidx);
|
418 |
|
|
}
|
419 |
|
|
}
|
420 |
|
|
}
|
421 |
|
|
if (b == 0) fprintf (fo, "};\n");
|
422 |
|
|
else fprintf (fo, ",\n");
|
423 |
|
|
}
|
424 |
|
|
|
425 |
|
|
fprintf (fo, "\n/* Register the bb_start */\n");
|
426 |
|
|
fprintf (fo, "reg [%2i:0] bb_start_r;\n\n", f->num_bb - 1);
|
427 |
|
|
fprintf (fo, "always @(posedge rst or posedge clk)\n");
|
428 |
|
|
fprintf (fo, "begin\n");
|
429 |
902 |
markom |
fprintf (fo, " if (rst) bb_start_r <= #1 %i'b0;\n", f->num_bb);
|
430 |
|
|
fprintf (fo, " else if (end_o) bb_start_r <= #1 %i'b0;\n", f->num_bb);
|
431 |
879 |
markom |
fprintf (fo, " else bb_start_r <= #1 bb_start;\n");
|
432 |
|
|
fprintf (fo, "end\n");
|
433 |
|
|
|
434 |
|
|
fprintf (fo, "\n/* Logic */\n");
|
435 |
|
|
/* output body */
|
436 |
|
|
for (b = 0; b < f->num_bb; b++) {
|
437 |
|
|
fprintf (fo, "\t\t/* BB%i */\n", b);
|
438 |
|
|
for (i = 0; i < f->bb[b].ninsn; i++)
|
439 |
|
|
print_insn_v (fo, f, b, i);
|
440 |
|
|
fprintf (fo, "\n");
|
441 |
|
|
}
|
442 |
|
|
|
443 |
|
|
if (co) {
|
444 |
|
|
fprintf (fo, "\n/* Outputs */\n");
|
445 |
|
|
for (i = 0; i < MAX_REGS; i++)
|
446 |
883 |
markom |
if (f->lur[i] >= 0 && !f->saved_regs[i])
|
447 |
|
|
fprintf (fo, "assign r%i_o = t%x_%x;\n", i, REF_BB(f->lur[i]),
|
448 |
|
|
REF_I(f->lur[i]));
|
449 |
879 |
markom |
}
|
450 |
|
|
|
451 |
|
|
if (nstores) {
|
452 |
|
|
int cur_store = 0;
|
453 |
|
|
fprintf (fo, "\n/* Memory stores */\n");
|
454 |
|
|
fprintf (fo, "always @(posedge clk or posedge rst)\nbegin\n");
|
455 |
|
|
fprintf (fo, " if (rst) swb_dat_o <= #1 32'h0;\n");
|
456 |
|
|
for (i = 0; i < f->nmsched; i++)
|
457 |
|
|
if (f->mtype[i] & MT_WRITE) {
|
458 |
|
|
char t[30];
|
459 |
|
|
fprintf (fo, " else if (s_stb[%i]) swb_dat_o <= #1 %s;\n", cur_store++,
|
460 |
|
|
print_op_v (f, t, f->msched[i], 0));
|
461 |
|
|
//printf ("msched[%i] = %x (mtype %x) %x\n", i, f->msched[i], f->mtype[i], f->INSN(f->msched[i]).op[0]);
|
462 |
|
|
}
|
463 |
|
|
fprintf (fo, "end\n");
|
464 |
|
|
}
|
465 |
|
|
|
466 |
|
|
if (nloads) {
|
467 |
|
|
int cur_load = 0;
|
468 |
|
|
fprintf (fo, "\n/* Load state machine */\n");
|
469 |
|
|
fprintf (fo, "always @(posedge clk or posedge rst)\n");
|
470 |
|
|
fprintf (fo, "begin\n");
|
471 |
|
|
fprintf (fo, " if (rst) begin\n");
|
472 |
|
|
fprintf (fo, " l_stb <= #1 %i'h0;\n", nloads);
|
473 |
|
|
fprintf (fo, " lwb_cycstb_o <= #1 1'b0;\n");
|
474 |
|
|
fprintf (fo, " lwb_sel_o[3:0] <= #1 4'b0000;\n");
|
475 |
|
|
fprintf (fo, " lwb_linbrst_o <= #1 1'b0;\n");
|
476 |
|
|
fprintf (fo, " lwb_adr_o <= #1 32'h0;\n");
|
477 |
|
|
fprintf (fo, " end else begin\n");
|
478 |
883 |
markom |
cucdebug (1, "loads \n");
|
479 |
879 |
markom |
for (i = 0; i < f->nmsched; i++) if (!(f->mtype[i] & MT_WRITE)) {
|
480 |
|
|
char t[30];
|
481 |
|
|
dep_list *dep = f->INSN(f->msched[i]).dep;
|
482 |
883 |
markom |
cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
|
483 |
879 |
markom |
assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
|
484 |
|
|
fprintf (fo, " if (");
|
485 |
|
|
print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
|
486 |
|
|
fprintf (fo, ") begin\n");
|
487 |
|
|
while (dep) {
|
488 |
|
|
assert (f->INSN(dep->ref).type & IT_MEMORY);
|
489 |
902 |
markom |
fprintf (fo, " %c_stb[%i] <= #1 1'b0;\n",
|
490 |
879 |
markom |
II_IS_LOAD (f->INSN(dep->ref).index) ? 'l' : 's', find_ls_index (f, dep->ref));
|
491 |
|
|
dep = dep->next;
|
492 |
|
|
}
|
493 |
|
|
fprintf (fo, " l_stb[%i] <= #1 1'b1;\n", cur_load++);
|
494 |
|
|
fprintf (fo, " lwb_cycstb_o <= #1 1'b1;\n");
|
495 |
|
|
fprintf (fo, " lwb_sel_o[3:0] <= #1 4'b");
|
496 |
|
|
switch (f->mtype[i] & MT_WIDTH) {
|
497 |
902 |
markom |
case 1: fprintf (fo, "0001 << (%s & 32'h3);\n",
|
498 |
879 |
markom |
print_op_v (f, t, f->msched[i], 1)); break;
|
499 |
902 |
markom |
case 2: fprintf (fo, "0011 << ((%s & 32'h1) << 1);\n",
|
500 |
879 |
markom |
print_op_v (f, t, f->msched[i], 1)); break;
|
501 |
|
|
case 4: fprintf (fo, "1111;\n"); break;
|
502 |
|
|
default: assert (0);
|
503 |
|
|
}
|
504 |
|
|
fprintf (fo, " lwb_linbrst_o <= #1 1'b%i;\n",
|
505 |
|
|
(f->mtype[i] & MT_BURST) && !(f->mtype[i] & MT_BURSTE) ? 1 : 0);
|
506 |
|
|
fprintf (fo, " lwb_adr_o <= #1 t%x_%x & ~32'h3;\n",
|
507 |
|
|
REF_BB(f->INSN(f->msched[i]).op[1]), REF_I(f->INSN(f->msched[i]).op[1]));
|
508 |
|
|
fprintf (fo, " end\n");
|
509 |
|
|
}
|
510 |
|
|
fprintf (fo, " if (l_end[%i]) begin\n", nloads - 1);
|
511 |
|
|
fprintf (fo, " l_stb <= #1 %i'h0;\n", nloads);
|
512 |
|
|
fprintf (fo, " lwb_cycstb_o <= #1 1'b0;\n");
|
513 |
|
|
fprintf (fo, " lwb_sel_o[3:0] <= #1 4'b0000;\n");
|
514 |
|
|
fprintf (fo, " lwb_linbrst_o <= #1 1'b0;\n");
|
515 |
|
|
fprintf (fo, " lwb_adr_o <= #1 32'h0;\n");
|
516 |
|
|
fprintf (fo, " end\n");
|
517 |
|
|
fprintf (fo, " end\n");
|
518 |
|
|
fprintf (fo, "end\n");
|
519 |
|
|
}
|
520 |
|
|
|
521 |
|
|
if (nstores) {
|
522 |
|
|
int cur_store = 0;
|
523 |
|
|
fprintf (fo, "\n/* Store state machine */\n");
|
524 |
|
|
fprintf (fo, "always @(posedge clk or posedge rst)\n");
|
525 |
|
|
fprintf (fo, "begin\n");
|
526 |
|
|
fprintf (fo, " if (rst) begin\n");
|
527 |
|
|
fprintf (fo, " s_stb <= #1 %i'h0;\n", nstores);
|
528 |
|
|
fprintf (fo, " swb_cycstb_o <= #1 1'b0;\n");
|
529 |
|
|
fprintf (fo, " swb_sel_o[3:0] <= #1 4'b0000;\n");
|
530 |
|
|
fprintf (fo, " swb_linbrst_o <= #1 1'b0;\n");
|
531 |
|
|
fprintf (fo, " swb_adr_o <= #1 32'h0;\n");
|
532 |
|
|
fprintf (fo, " end else begin\n");
|
533 |
883 |
markom |
cucdebug (1, "stores \n");
|
534 |
879 |
markom |
for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_WRITE) {
|
535 |
|
|
char t[30];
|
536 |
|
|
dep_list *dep = f->INSN(f->msched[i]).dep;
|
537 |
883 |
markom |
cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
|
538 |
879 |
markom |
assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
|
539 |
|
|
fprintf (fo, " if (");
|
540 |
|
|
print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
|
541 |
|
|
fprintf (fo, ") begin\n");
|
542 |
|
|
while (dep) {
|
543 |
|
|
assert (f->INSN(dep->ref).type & IT_MEMORY);
|
544 |
902 |
markom |
fprintf (fo, " %c_stb[%i] <= #1 1'b0;\n",
|
545 |
879 |
markom |
II_IS_LOAD (f->INSN(dep->ref).index) ? 'l' : 's', find_ls_index (f, dep->ref));
|
546 |
|
|
dep = dep->next;
|
547 |
|
|
}
|
548 |
|
|
fprintf (fo, " s_stb[%i] <= #1 1'b1;\n", cur_store++);
|
549 |
|
|
fprintf (fo, " swb_cycstb_o <= #1 1'b1;\n");
|
550 |
|
|
fprintf (fo, " swb_sel_o[3:0] <= #1 4'b");
|
551 |
|
|
switch (f->mtype[i] & MT_WIDTH) {
|
552 |
902 |
markom |
case 1: fprintf (fo, "0001 << (%s & 32'h3);\n",
|
553 |
879 |
markom |
print_op_v (f, t, f->msched[i], 1)); break;
|
554 |
902 |
markom |
case 2: fprintf (fo, "0011 << ((%s & 32'h1) << 1);\n",
|
555 |
879 |
markom |
print_op_v (f, t, f->msched[i], 1)); break;
|
556 |
|
|
case 4: fprintf (fo, "1111;\n"); break;
|
557 |
|
|
default: assert (0);
|
558 |
|
|
}
|
559 |
|
|
fprintf (fo, " swb_linbrst_o <= #1 1'b%i;\n",
|
560 |
|
|
(f->mtype[i] & MT_BURST) && !(f->mtype[i] & MT_BURSTE) ? 1 : 0);
|
561 |
|
|
fprintf (fo, " swb_adr_o <= #1 t%x_%x & ~32'h3;\n",
|
562 |
|
|
REF_BB(f->INSN(f->msched[i]).op[1]), REF_I(f->INSN(f->msched[i]).op[1]));
|
563 |
|
|
fprintf (fo, " end\n");
|
564 |
|
|
}
|
565 |
|
|
fprintf (fo, " if (s_end[%i]) begin\n", nstores - 1);
|
566 |
|
|
fprintf (fo, " s_stb <= #1 %i'h0;\n", nstores);
|
567 |
|
|
fprintf (fo, " swb_cycstb_o <= #1 1'b0;\n");
|
568 |
|
|
fprintf (fo, " swb_sel_o[3:0] <= #1 4'b0000;\n");
|
569 |
|
|
fprintf (fo, " swb_linbrst_o <= #1 1'b0;\n");
|
570 |
|
|
fprintf (fo, " swb_adr_o <= #1 32'h0;\n");
|
571 |
|
|
fprintf (fo, " end\n");
|
572 |
|
|
fprintf (fo, " end\n");
|
573 |
|
|
fprintf (fo, "end\n");
|
574 |
|
|
}
|
575 |
|
|
|
576 |
|
|
fprintf (fo, "\n/* Basic blocks state machine */\n");
|
577 |
|
|
fprintf (fo, "always @(posedge clk or posedge rst)\n");
|
578 |
|
|
fprintf (fo, "begin\n");
|
579 |
902 |
markom |
fprintf (fo, " if (rst) bb_stb <= #1 %i'h%x;\n", f->num_bb, 0);
|
580 |
|
|
fprintf (fo, " else if (end_o) bb_stb <= #1 %i'h%x;\n", f->num_bb, 0);
|
581 |
879 |
markom |
for (i = 0; i < f->num_bb; i++) {
|
582 |
902 |
markom |
fprintf (fo, " else if (bb_start[%i]) begin\n", i);
|
583 |
879 |
markom |
fprintf (fo, " bb_stb <= #1 %i'h%x;\n", f->num_bb, 1 << i);
|
584 |
|
|
}
|
585 |
|
|
fprintf (fo, " end else if (end_o) begin\n");
|
586 |
|
|
fprintf (fo, " bb_stb <= #1 %i'h%x;\n", f->num_bb, 0);
|
587 |
|
|
fprintf (fo, " end\n");
|
588 |
|
|
fprintf (fo, "end\n");
|
589 |
|
|
|
590 |
|
|
/* output footer */
|
591 |
|
|
fprintf (fo, "\nendmodule\n");
|
592 |
|
|
|
593 |
|
|
fclose (fo);
|
594 |
|
|
}
|
595 |
|
|
|