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/* mc.c -- Simulation of Memory Controller
         Copyright (C) 2001 by Marko Mlinar, markom@opencores.org
 
         This file is part of OpenRISC 1000 Architectural Simulator.
 
         This program is free software; you can redistribute it and/or modify
         it under the terms of the GNU General Public License as published by
         the Free Software Foundation; either version 2 of the License, or
         (at your option) any later version.
 
         This program is distributed in the hope that it will be useful,
         but WITHOUT ANY WARRANTY; without even the implied warranty of
         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.    See the
         GNU General Public License for more details.
 
         You should have received a copy of the GNU General Public License
         along with this program; if not, write to the Free Software
         Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
 
/* Enable memory controller, via:
  section mc
    enable = 1
    POC = 0x13243545
  end
 
   Limitations:
    - memory refresh is not simulated
*/
 
#include <string.h>
 
#include "config.h"
 
#ifdef HAVE_INTTYPES_H
#include <inttypes.h>
#endif
 
#include "port.h"
#include "arch.h"
#include "mc.h"
#include "abstract.h"
#include "sim-config.h"
#include "debug.h"
 
struct mc_area {
  struct dev_memarea *mem;
  unsigned int cs;
  int mc;
  struct mc_area *next;
};
 
struct mc {
  unsigned long csr;
  unsigned long poc;
  unsigned long ba_mask;
  unsigned long csc[N_CE];
  unsigned long tms[N_CE];
  oraddr_t baseaddr;
  int enabled;
 
  /* Index of this memory controler amongst all the memory controlers */
  int index;
  /* List of memory devices under this mc's control */
  struct mc_area *mc_areas;
 
  struct mc *next;
};
 
static struct mc *mcs = NULL;
 
/* List used to temporarily hold memory areas registered with the mc, while the
 * mc configureation has not been loaded */
static struct mc_area *mc_areas = NULL;
 
void set_csc_tms (int cs, unsigned long csc, unsigned long tms, struct mc *mc)
{
  struct mc_area *cur = mc->mc_areas;
 
  while (cur) {
    if (cur->cs == cs) {
      /* FIXME: No peripheral should _ever_ acess a dev_memarea structure
       * directly */
      cur->mem->addr_mask = mc->ba_mask << 22;
      cur->mem->addr_compare = ((csc >> MC_CSC_SEL_OFFSET) /* & 0xff*/) << 22;
      set_mem_valid(cur->mem, (csc >> MC_CSC_EN_OFFSET) & 0x01);
 
      if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {
        adjust_rw_delay(cur->mem, (tms & 0xff) + ((tms >> 8) & 0x0f),
                        ((tms >> 12)  & 0x0f) + ((tms >> 16) & 0x0f) + ((tms >> 20) & 0x3f));
      } else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {
        adjust_rw_delay(cur->mem, 3 + ((tms >> 4) & 0x03),
                        3 + ((tms >> 4) & 0x03));
      } else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SSRAM) {
        adjust_rw_delay(cur->mem, 2, 2);
      } else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
        adjust_rw_delay(cur->mem, 2, 2);
      }
      return;
    }
    cur = cur->next;
  }
}
 
/* Set a specific MC register with value. */
void mc_write_word(oraddr_t addr, uint32_t value, void *dat)
{
    struct mc *mc = dat;
        int chipsel;
 
        debug(5, "mc_write_word(%"PRIxADDR",%08"PRIx32")\n", addr, value);
 
        switch (addr) {
          case MC_CSR:
            mc->csr = value;
            break;
          case MC_POC:
            fprintf (stderr, "warning: write to MC's POC register!");
            break;
          case MC_BA_MASK:
            mc->ba_mask = value & MC_BA_MASK_VALID;
      for (chipsel = 0; chipsel < N_CE; chipsel++)
        set_csc_tms (chipsel, mc->csc[chipsel], mc->tms[chipsel], mc);
            break;
                default:
                  if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {
                    addr -= MC_CSC(0);
                    if ((addr >> 2) & 1)
                      mc->tms[addr >> 3] = value;
                    else
                      mc->csc[addr >> 3] = value;
 
                    set_csc_tms (addr >> 3, mc->csc[addr >> 3], mc->tms[addr >> 3], mc);
                    break;
                  } else
                        debug(1, "write out of range (addr %"PRIxADDR")\n", addr + mc->baseaddr);
        }
}
 
/* Read a specific MC register. */
uint32_t mc_read_word(oraddr_t addr, void *dat)
{
    struct mc *mc = dat;
        uint32_t value = 0;
 
        debug(5, "mc_read_word(%"PRIxADDR")", addr);
 
        switch (addr) {
          case MC_CSR:
            value = mc->csr;
            break;
          case MC_POC:
            value = mc->poc;
            break;
          case MC_BA_MASK:
            value = mc->ba_mask;
            break;
                default:
                  if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {
                    addr -= MC_CSC(0);
                    if ((addr >> 2) & 1)
                      value = mc->tms[addr >> 3];
                    else
                      value = mc->csc[addr >> 3];
                  } else
                        debug(1, " read out of range (addr %"PRIxADDR")\n", addr + mc->baseaddr);
            break;
        }
        debug(5, " value(%"PRIx32")\n", value);
        return value;
}
 
/* Read POC register and init memory controler regs. */
void mc_reset(void *dat)
{
  struct mc *mc = dat;
  struct mc_area *cur, *prev, *tmp;
 
  PRINTF("Resetting memory controller.\n");
 
  memset(mc->csc, 0, sizeof(mc->csc));
  memset(mc->tms, 0, sizeof(mc->tms));
 
  mc->csr = 0;
  mc->ba_mask = 0;
 
  /* Set CS0 */
  mc->csc[0] = (((mc->poc & 0x0c) >> 2) << MC_CSC_MEMTYPE_OFFSET) | ((mc->poc & 0x03) << MC_CSC_BW_OFFSET) | 1;
 
  if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {
    mc->tms[0] = MC_TMS_ASYNC_VALID;
  } else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {
    mc->tms[0] = MC_TMS_SDRAM_VALID;
  } else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SSRAM) {
    mc->tms[0] = MC_TMS_SSRAM_VALID;
  } else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
    mc->tms[0] = MC_TMS_SYNC_VALID;
  }
 
  /* Grab control over all the devices we are destined to control */
  cur = mc_areas;
  prev = NULL;
  while (cur) {
    if (cur->mc == mc->index) {
      if (prev) prev->next = cur->next;
      else mc_areas = cur->next;
      prev = cur;
      tmp = cur->next;
      cur->next = mc->mc_areas;
      mc->mc_areas = cur;
      cur = tmp;
    } else {
      prev = cur;
      cur = cur->next;
    }
  }
 
  for (cur = mc->mc_areas; cur; cur = cur->next)
    set_mem_valid(cur->mem, 0);
 
  set_csc_tms (0, mc->csc[0], mc->tms[0], mc);
}
 
void mc_status(void *dat)
{
    struct mc *mc = dat;
    int i;
 
    PRINTF( "\nMemory Controller at 0x%"PRIxADDR":\n", mc->baseaddr );
    PRINTF( "POC: 0x%08lX\n", mc->poc );
    PRINTF( "BAS: 0x%08lX\n", mc->ba_mask );
    PRINTF( "CSR: 0x%08lX\n", mc->csr );
 
    for (i=0; i<N_CE; i++) {
        PRINTF( "CE %02d -  CSC: 0x%08lX  TMS: 0x%08lX\n", i, mc->csc[i],
               mc->tms[i]);
    }
}
 
/*--------------------------------------------[ Peripheral<->MC interface ]---*/
/* Registers some memory to be under the memory controllers control */
void mc_reg_mem_area(struct dev_memarea *mem, unsigned int cs, int mc)
{
  struct mc_area *new;
 
  if(!(new = malloc(sizeof(struct mc_area)))) {
    fprintf(stderr, "Out-of-memory\n");
    exit(-1);
  }
  new->cs = cs;
  new->mem = mem;
  new->mc = mc;
 
  new->next = mc_areas;
  mc_areas = new;
}
 
/*-----------------------------------------------------[ MC configuration ]---*/
void mc_enabled(union param_val val, void *dat)
{
  struct mc *mc = dat;
  mc->enabled = val.int_val;
}
 
void mc_baseaddr(union param_val val, void *dat)
{
  struct mc *mc = dat;
  mc->baseaddr = val.addr_val;
}
 
void mc_POC(union param_val val, void *dat)
{
  struct mc *mc = dat;
  mc->poc = val.int_val;
}
 
void mc_index(union param_val val, void *dat)
{
  struct mc *mc = dat;
  mc->index = val.int_val;
}
 
void *mc_sec_start(void)
{
  struct mc *new = malloc(sizeof(struct mc));
 
  if(!new) {
    fprintf(stderr, "Peripheral MC: Run out of memory\n");
    exit(-1);
  }
 
  new->index = 0;
  new->enabled = 0;
  new->mc_areas = NULL;
 
  return new;
}
 
void mc_sec_end(void *dat)
{
  struct mc *mc = dat;
  struct mem_ops ops;
 
  if(!mc->enabled) {
    free(dat);
    return;
  }
 
  /* FIXME: Check to see that the index given to this mc is unique */
 
  mc->next = mcs;
  mcs = mc;
 
  memset(&ops, 0, sizeof(struct mem_ops));
 
  ops.readfunc32 = mc_read_word;
  ops.writefunc32 = mc_write_word;
  ops.write_dat32 = dat;
  ops.read_dat32 = dat;
 
  /* FIXME: Correct delays? */
  ops.delayr = 2;
  ops.delayw = 2;
 
  reg_mem_area(mc->baseaddr, MC_ADDR_SPACE, 1, &ops);
  reg_sim_reset(mc_reset, dat);
  reg_sim_stat(mc_status, dat);
}
 
void reg_mc_sec(void)
{
  struct config_section *sec = reg_config_sec("mc", mc_sec_start, mc_sec_end);
 
  reg_config_param(sec, "enabled", paramt_int, mc_enabled);
  reg_config_param(sec, "baseaddr", paramt_addr, mc_baseaddr);
  reg_config_param(sec, "POC", paramt_int, mc_POC);
  reg_config_param(sec, "index", paramt_int, mc_index);
}

Line No.	Rev	Author	Line
1	239	markom	`/* mc.c -- Simulation of Memory Controller`
2			`Copyright (C) 2001 by Marko Mlinar, markom@opencores.org`
3
4			`This file is part of OpenRISC 1000 Architectural Simulator.`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License as published by`
8			`the Free Software Foundation; either version 2 of the License, or`
9			`(at your option) any later version.`
10
11			`This program is distributed in the hope that it will be useful,`
12			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`GNU General Public License for more details.`
15
16			`You should have received a copy of the GNU General Public License`
17			`along with this program; if not, write to the Free Software`
18			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.`
19			`*/`
20
21			`/* Enable memory controller, via:`
22			`section mc`
23			`enable = 1`
24			`POC = 0x13243545`
25			`end`
26
27	261	markom	`Limitations:`
28			`- memory refresh is not simulated`
29	742	ivang	`*/`
30	239	markom
31	1308	phoenix	`#include <string.h>`
32
33	1350	nogj	`#include "config.h"`
34
35			`#ifdef HAVE_INTTYPES_H`
36			`#include <inttypes.h>`
37			`#endif`
38
39			`#include "port.h"`
40			`#include "arch.h"`
41	239	markom	`#include "mc.h"`
42			`#include "abstract.h"`
43	261	markom	`#include "sim-config.h"`
44	1308	phoenix	`#include "debug.h"`
45	261	markom
46	1486	nogj	`struct mc_area {`
47			`struct dev_memarea *mem;`
48			`unsigned int cs;`
49			`int mc;`
50			`struct mc_area *next;`
51			`};`
52	539	simons
53	1486	nogj	`struct mc {`
54			`unsigned long csr;`
55			`unsigned long poc;`
56			`unsigned long ba_mask;`
57			`unsigned long csc[N_CE];`
58			`unsigned long tms[N_CE];`
59			`oraddr_t baseaddr;`
60			`int enabled;`
61
62			`/* Index of this memory controler amongst all the memory controlers */`
63			`int index;`
64			`/* List of memory devices under this mc's control */`
65			`struct mc_area *mc_areas;`
66
67			`struct mc *next;`
68			`};`
69
70			`static struct mc *mcs = NULL;`
71
72			`/* List used to temporarily hold memory areas registered with the mc, while the`
73			`* mc configureation has not been loaded */`
74			`static struct mc_area *mc_areas = NULL;`
75
76			`void set_csc_tms (int cs, unsigned long csc, unsigned long tms, struct mc *mc)`
77			`{`
78			`struct mc_area *cur = mc->mc_areas;`
79	539	simons
80	1486	nogj	`while (cur) {`
81			`if (cur->cs == cs) {`
82			`/* FIXME: No peripheral should _ever_ acess a dev_memarea structure`
83			`* directly */`
84			`cur->mem->addr_mask = mc->ba_mask << 22;`
85			`cur->mem->addr_compare = ((csc >> MC_CSC_SEL_OFFSET) /* & 0xff*/) << 22;`
86			`set_mem_valid(cur->mem, (csc >> MC_CSC_EN_OFFSET) & 0x01);`
87	539	simons
88			`if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {`
89	1486	nogj	`adjust_rw_delay(cur->mem, (tms & 0xff) + ((tms >> 8) & 0x0f),`
90			`((tms >> 12) & 0x0f) + ((tms >> 16) & 0x0f) + ((tms >> 20) & 0x3f));`
91	539	simons	`} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {`
92	1486	nogj	`adjust_rw_delay(cur->mem, 3 + ((tms >> 4) & 0x03),`
93			`3 + ((tms >> 4) & 0x03));`
94	539	simons	`} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SSRAM) {`
95	1486	nogj	`adjust_rw_delay(cur->mem, 2, 2);`
96	539	simons	`} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {`
97	1486	nogj	`adjust_rw_delay(cur->mem, 2, 2);`
98	539	simons	`}`
99	543	simons	`return;`
100	539	simons	`}`
101	1486	nogj	`cur = cur->next;`
102	539	simons	`}`
103	261	markom	`}`
104
105			`/* Set a specific MC register with value. */`
106	1359	nogj	`void mc_write_word(oraddr_t addr, uint32_t value, void *dat)`
107	261	markom	`{`
108	1373	nogj	`struct mc *mc = dat;`
109	261	markom	`int chipsel;`
110
111	1350	nogj	`debug(5, "mc_write_word(%"PRIxADDR",%08"PRIx32")\n", addr, value);`
112	261	markom
113			`switch (addr) {`
114			`case MC_CSR:`
115	1373	nogj	`mc->csr = value;`
116	261	markom	`break;`
117			`case MC_POC:`
118			`fprintf (stderr, "warning: write to MC's POC register!");`
119			`break;`
120			`case MC_BA_MASK:`
121	1373	nogj	`mc->ba_mask = value & MC_BA_MASK_VALID;`
122	543	simons	`for (chipsel = 0; chipsel < N_CE; chipsel++)`
123	1373	nogj	`set_csc_tms (chipsel, mc->csc[chipsel], mc->tms[chipsel], mc);`
124	261	markom	`break;`
125			`default:`
126			`if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {`
127			`addr -= MC_CSC(0);`
128			`if ((addr >> 2) & 1)`
129	1373	nogj	`mc->tms[addr >> 3] = value;`
130	261	markom	`else`
131	1373	nogj	`mc->csc[addr >> 3] = value;`
132	261	markom
133	1373	nogj	`set_csc_tms (addr >> 3, mc->csc[addr >> 3], mc->tms[addr >> 3], mc);`
134	261	markom	`break;`
135			`} else`
136	1373	nogj	`debug(1, "write out of range (addr %"PRIxADDR")\n", addr + mc->baseaddr);`
137	261	markom	`}`
138			`}`
139
140			`/* Read a specific MC register. */`
141	1359	nogj	`uint32_t mc_read_word(oraddr_t addr, void *dat)`
142	261	markom	`{`
143	1373	nogj	`struct mc *mc = dat;`
144	1350	nogj	`uint32_t value = 0;`
145	261	markom
146	1350	nogj	`debug(5, "mc_read_word(%"PRIxADDR")", addr);`
147	261	markom
148			`switch (addr) {`
149			`case MC_CSR:`
150	1373	nogj	`value = mc->csr;`
151	261	markom	`break;`
152			`case MC_POC:`
153	1373	nogj	`value = mc->poc;`
154	261	markom	`break;`
155			`case MC_BA_MASK:`
156	1373	nogj	`value = mc->ba_mask;`
157	261	markom	`break;`
158			`default:`
159			`if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {`
160			`addr -= MC_CSC(0);`
161			`if ((addr >> 2) & 1)`
162	1373	nogj	`value = mc->tms[addr >> 3];`
163	261	markom	`else`
164	1373	nogj	`value = mc->csc[addr >> 3];`
165	261	markom	`} else`
166	1373	nogj	`debug(1, " read out of range (addr %"PRIxADDR")\n", addr + mc->baseaddr);`
167	261	markom	`break;`
168			`}`
169	1350	nogj	`debug(5, " value(%"PRIx32")\n", value);`
170	261	markom	`return value;`
171			`}`
172
173			`/* Read POC register and init memory controler regs. */`
174	1373	nogj	`void mc_reset(void *dat)`
175	261	markom	`{`
176	1373	nogj	`struct mc *mc = dat;`
177	1486	nogj	`struct mc_area cur, prev, *tmp;`
178	543	simons
179	1373	nogj	`PRINTF("Resetting memory controller.\n");`
180	261	markom
181	1373	nogj	`memset(mc->csc, 0, sizeof(mc->csc));`
182			`memset(mc->tms, 0, sizeof(mc->tms));`
183	539	simons
184	1373	nogj	`mc->csr = 0;`
185			`mc->ba_mask = 0;`
186	539	simons
187	1373	nogj	`/* Set CS0 */`
188			`mc->csc[0] = (((mc->poc & 0x0c) >> 2) << MC_CSC_MEMTYPE_OFFSET) \| ((mc->poc & 0x03) << MC_CSC_BW_OFFSET) \| 1;`
189	539	simons
190	1373	nogj	`if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {`
191			`mc->tms[0] = MC_TMS_ASYNC_VALID;`
192			`} else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {`
193			`mc->tms[0] = MC_TMS_SDRAM_VALID;`
194			`} else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SSRAM) {`
195			`mc->tms[0] = MC_TMS_SSRAM_VALID;`
196			`} else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {`
197			`mc->tms[0] = MC_TMS_SYNC_VALID;`
198			`}`
199	543	simons
200	1486	nogj	`/* Grab control over all the devices we are destined to control */`
201			`cur = mc_areas;`
202			`prev = NULL;`
203			`while (cur) {`
204			`if (cur->mc == mc->index) {`
205			`if (prev) prev->next = cur->next;`
206			`else mc_areas = cur->next;`
207			`prev = cur;`
208			`tmp = cur->next;`
209			`cur->next = mc->mc_areas;`
210			`mc->mc_areas = cur;`
211			`cur = tmp;`
212			`} else {`
213			`prev = cur;`
214			`cur = cur->next;`
215			`}`
216	261	markom	`}`
217
218	1486	nogj	`for (cur = mc->mc_areas; cur; cur = cur->next)`
219			`set_mem_valid(cur->mem, 0);`
220
221	1373	nogj	`set_csc_tms (0, mc->csc[0], mc->tms[0], mc);`
222	261	markom	`}`
223	742	ivang
224	1373	nogj	`void mc_status(void *dat)`
225	742	ivang	`{`
226	1373	nogj	`struct mc *mc = dat;`
227	742	ivang	`int i;`
228
229	1373	nogj	`PRINTF( "\nMemory Controller at 0x%"PRIxADDR":\n", mc->baseaddr );`
230			`PRINTF( "POC: 0x%08lX\n", mc->poc );`
231			`PRINTF( "BAS: 0x%08lX\n", mc->ba_mask );`
232			`PRINTF( "CSR: 0x%08lX\n", mc->csr );`
233	742	ivang
234			`for (i=0; i<N_CE; i++) {`
235	1373	nogj	`PRINTF( "CE %02d - CSC: 0x%08lX TMS: 0x%08lX\n", i, mc->csc[i],`
236			`mc->tms[i]);`
237	742	ivang	`}`
238			`}`
239	1358	nogj
240	1486	nogj	`/--------------------------------------------[ Peripheral<->MC interface ]---/`
241			`/* Registers some memory to be under the memory controllers control */`
242			`void mc_reg_mem_area(struct dev_memarea *mem, unsigned int cs, int mc)`
243			`{`
244			`struct mc_area *new;`
245
246			`if(!(new = malloc(sizeof(struct mc_area)))) {`
247			`fprintf(stderr, "Out-of-memory\n");`
248			`exit(-1);`
249			`}`
250			`new->cs = cs;`
251			`new->mem = mem;`
252			`new->mc = mc;`
253
254			`new->next = mc_areas;`
255			`mc_areas = new;`
256			`}`
257
258			`/-----------------------------------------------------[ MC configuration ]---/`
259	1358	nogj	`void mc_enabled(union param_val val, void *dat)`
260			`{`
261	1373	nogj	`struct mc *mc = dat;`
262			`mc->enabled = val.int_val;`
263	1358	nogj	`}`
264
265			`void mc_baseaddr(union param_val val, void *dat)`
266			`{`
267	1373	nogj	`struct mc *mc = dat;`
268			`mc->baseaddr = val.addr_val;`
269	1358	nogj	`}`
270
271			`void mc_POC(union param_val val, void *dat)`
272			`{`
273	1373	nogj	`struct mc *mc = dat;`
274			`mc->poc = val.int_val;`
275	1358	nogj	`}`
276
277	1486	nogj	`void mc_index(union param_val val, void *dat)`
278			`{`
279			`struct mc *mc = dat;`
280			`mc->index = val.int_val;`
281			`}`
282
283	1373	nogj	`void *mc_sec_start(void)`
284			`{`
285			`struct mc *new = malloc(sizeof(struct mc));`
286
287			`if(!new) {`
288			`fprintf(stderr, "Peripheral MC: Run out of memory\n");`
289			`exit(-1);`
290			`}`
291
292	1486	nogj	`new->index = 0;`
293	1373	nogj	`new->enabled = 0;`
294	1486	nogj	`new->mc_areas = NULL;`
295	1373	nogj
296			`return new;`
297			`}`
298
299			`void mc_sec_end(void *dat)`
300			`{`
301			`struct mc *mc = dat;`
302	1486	nogj	`struct mem_ops ops;`
303	1373	nogj
304	1461	nogj	`if(!mc->enabled) {`
305			`free(dat);`
306			`return;`
307	1373	nogj	`}`
308	1461	nogj
309	1486	nogj	`/* FIXME: Check to see that the index given to this mc is unique */`
310
311			`mc->next = mcs;`
312			`mcs = mc;`
313
314			`memset(&ops, 0, sizeof(struct mem_ops));`
315
316			`ops.readfunc32 = mc_read_word;`
317			`ops.writefunc32 = mc_write_word;`
318			`ops.write_dat32 = dat;`
319			`ops.read_dat32 = dat;`
320
321			`/* FIXME: Correct delays? */`
322			`ops.delayr = 2;`
323			`ops.delayw = 2;`
324
325			`reg_mem_area(mc->baseaddr, MC_ADDR_SPACE, 1, &ops);`
326	1461	nogj	`reg_sim_reset(mc_reset, dat);`
327			`reg_sim_stat(mc_status, dat);`
328	1373	nogj	`}`
329
330	1358	nogj	`void reg_mc_sec(void)`
331			`{`
332	1373	nogj	`struct config_section *sec = reg_config_sec("mc", mc_sec_start, mc_sec_end);`
333	1358	nogj
334			`reg_config_param(sec, "enabled", paramt_int, mc_enabled);`
335			`reg_config_param(sec, "baseaddr", paramt_addr, mc_baseaddr);`
336			`reg_config_param(sec, "POC", paramt_int, mc_POC);`
337	1486	nogj	`reg_config_param(sec, "index", paramt_int, mc_index);`
338	1358	nogj	`}`

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