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[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [cpu/] [common/] [abstract.c] - Blame information for rev 1487

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1 2 cvs 
/* abstract.c -- Abstract entities
2 
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
3 1486 nogj 
   Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org
4 2 cvs 
 
5 
This file is part of OpenRISC 1000 Architectural Simulator.
6 
 
7 
This program is free software; you can redistribute it and/or modify
8 
it under the terms of the GNU General Public License as published by
9 
the Free Software Foundation; either version 2 of the License, or
10 
(at your option) any later version.
11 
 
12 
This program is distributed in the hope that it will be useful,
13 
but WITHOUT ANY WARRANTY; without even the implied warranty of
14 
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 
GNU General Public License for more details.
16 
 
17 
You should have received a copy of the GNU General Public License
18 
along with this program; if not, write to the Free Software
19 
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
20 
 
21 66 lampret 
/* Abstract memory and routines that go with this. I need to
22 2 cvs 
add all sorts of other abstract entities. Currently we have
23 
only memory. */
24 
 
25 221 markom 
#include <stdlib.h>
26 2 cvs 
#include <stdio.h>
27 
#include <ctype.h>
28 
#include <string.h>
29 
 
30 6 lampret 
#include "config.h"
31 1350 nogj 
 
32 
#ifdef HAVE_INTTYPES_H
33 
#include <inttypes.h>
34 
#endif
35 
 
36 
#include "port.h"
37 6 lampret 
 
38 1350 nogj 
#include "arch.h"
39 2 cvs 
#include "parse.h"
40 
#include "abstract.h"
41 1358 nogj 
#include "sim-config.h"
42 261 markom 
#include "labels.h"
43 32 lampret 
#include "except.h"
44 123 markom 
#include "debug_unit.h"
45 134 markom 
#include "opcode/or32.h"
46 1432 nogj 
#include "spr_defs.h"
47 
#include "execute.h"
48 
#include "sprs.h"
49 547 markom 
#include "support/profile.h"
50 1308 phoenix 
#include "dmmu.h"
51 1446 nogj 
#include "immu.h"
52 1308 phoenix 
#include "dcache_model.h"
53 
#include "icache_model.h"
54 
#include "debug.h"
55 1344 nogj 
#include "stats.h"
56 2 cvs 
 
57 1452 nogj 
#if DYNAMIC_EXECUTION
58 
#include "dyn_rec.h"
59 
#endif
60 
 
61 138 markom 
extern char *disassembled;
62 2 cvs 
 
63 30 lampret 
/* Pointer to memory area descriptions that are assigned to individual
64 
   peripheral devices. */
65 
struct dev_memarea *dev_list;
66 
 
67 221 markom 
/* Temporary variable to increase speed.  */
68 
struct dev_memarea *cur_area;
69 
 
70 970 simons 
/* Pointer to memory controller device descriptor.  */
71 1486 nogj 
struct dev_memarea *mc_area = NULL;
72 970 simons 
 
73 638 simons 
/* These are set by mmu if cache inhibit bit is set for current acces.  */
74 
int data_ci, insn_ci;
75 
 
76 525 simons 
/* Virtual address of current access. */
77 1486 nogj 
static oraddr_t cur_vadd;
78 525 simons 
 
79 1486 nogj 
/* Read functions */
80 
uint32_t eval_mem_32_inv(oraddr_t, void *);
81 
uint16_t eval_mem_16_inv(oraddr_t, void *);
82 
uint8_t eval_mem_8_inv(oraddr_t, void *);
83 
uint32_t eval_mem_32_inv_direct(oraddr_t, void *);
84 
uint16_t eval_mem_16_inv_direct(oraddr_t, void *);
85 
uint8_t eval_mem_8_inv_direct(oraddr_t, void *);
86 
 
87 
/* Write functions */
88 
void set_mem_32_inv(oraddr_t, uint32_t, void *);
89 
void set_mem_16_inv(oraddr_t, uint16_t, void *);
90 
void set_mem_8_inv(oraddr_t, uint8_t, void *);
91 
void set_mem_32_inv_direct(oraddr_t, uint32_t, void *);
92 
void set_mem_16_inv_direct(oraddr_t, uint16_t, void *);
93 
void set_mem_8_inv_direct(oraddr_t, uint8_t, void *);
94 
 
95 261 markom 
/* Calculates bit mask to fit the data */
96 1486 nogj 
static unsigned int bit_mask (uint32_t data) {
97 261 markom 
  int i = 0;
98 
  data--;
99 382 markom 
  while (data >> i)
100 261 markom 
    data |= 1 << i++;
101 
  return data;
102 
}
103 
 
104 
/* Register read and write function for a memory area.
105 
   addr is inside the area, if addr & addr_mask == addr_compare
106 
   (used also by peripheral devices like 16450 UART etc.) */
107 1486 nogj 
struct dev_memarea *register_memoryarea_mask(oraddr_t addr_mask,
108 
                                             oraddr_t addr_compare,
109 
                                             uint32_t size, unsigned mc_dev)
110 30 lampret 
{
111 239 markom 
  struct dev_memarea **pptmp;
112 1350 nogj 
  unsigned int size_mask = bit_mask (size);
113 261 markom 
  int found_error = 0;
114 
  addr_compare &= addr_mask;
115 221 markom 
 
116 1486 nogj 
  debug(5, "addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %08"PRIx32"\n",
117 
        addr_mask, addr_compare, addr_compare | bit_mask (size), size);
118 239 markom 
  /* Go to the end of the list. */
119 261 markom 
  for(pptmp = &dev_list; *pptmp; pptmp = &(*pptmp)->next)
120 
    if ((addr_compare >= (*pptmp)->addr_compare) && (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)
121 
     || (addr_compare + size > (*pptmp)->addr_compare) && (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)) {
122 262 markom 
      if (!found_error) {
123 261 markom 
        fprintf (stderr, "ERROR: Overlapping memory area(s):\n");
124 1350 nogj 
        fprintf (stderr, "\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
125 1486 nogj 
                         ", size %08"PRIx32"\n",
126 
                 addr_mask, addr_compare, addr_compare | bit_mask (size), size);
127 262 markom 
      }
128 261 markom 
      found_error = 1;
129 1350 nogj 
      fprintf (stderr, "and\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
130 1486 nogj 
                       ", size %08"PRIx32"\n",
131 1308 phoenix 
               (*pptmp)->addr_mask, (*pptmp)->addr_compare,
132 1486 nogj 
               (*pptmp)->addr_compare | (*pptmp)->size_mask, (*pptmp)->size);
133 261 markom 
    }
134 
 
135 
  if (found_error)
136 
    exit (-1);
137 537 markom 
 
138 239 markom 
  cur_area = *pptmp = (struct dev_memarea *)malloc(sizeof(struct dev_memarea));
139 970 simons 
 
140 
  if (mc_dev)
141 
    mc_area = *pptmp;
142 
 
143 261 markom 
  (*pptmp)->addr_mask = addr_mask;
144 
  (*pptmp)->addr_compare = addr_compare;
145 239 markom 
  (*pptmp)->size = size;
146 261 markom 
  (*pptmp)->size_mask = size_mask;
147 1486 nogj 
  (*pptmp)->log = NULL;
148 
  (*pptmp)->valid = 1;
149 239 markom 
  (*pptmp)->next = NULL;
150 1486 nogj 
 
151 
  return *pptmp;
152 261 markom 
}
153 221 markom 
 
154 261 markom 
/* Register read and write function for a memory area.
155 
   Memory areas should be aligned. Memory area is rounded up to
156 
   fit the nearest 2^n aligment.
157 970 simons 
   (used also by peripheral devices like 16450 UART etc.)
158 1486 nogj 
   If mc_dev is 1, this device will be checked first for a match
159 
   and will be accessed in case of overlaping memory areas.
160 970 simons 
   Only one device can have this set to 1 (used for memory controller) */
161 1486 nogj 
struct dev_memarea *reg_mem_area(oraddr_t addr, uint32_t size, unsigned mc_dev,
162 
                                 struct mem_ops *ops)
163 261 markom 
{
164 1350 nogj 
  unsigned int size_mask = bit_mask (size);
165 
  unsigned int addr_mask = ~size_mask;
166 1486 nogj 
  struct dev_memarea *mem;
167 
 
168 
  mem = register_memoryarea_mask(addr_mask, addr & addr_mask, size_mask + 1,
169 
                                 mc_dev);
170 
 
171 
  memcpy(&mem->ops, ops, sizeof(struct mem_ops));
172 
  memcpy(&mem->direct_ops, ops, sizeof(struct mem_ops));
173 
 
174 
  if(!ops->readfunc32) {
175 
    mem->ops.readfunc32 = eval_mem_32_inv;
176 
    mem->direct_ops.readfunc32 = eval_mem_32_inv_direct;
177 
    mem->direct_ops.read_dat32 = mem;
178 
  }
179 
  if(!ops->readfunc16) {
180 
    mem->ops.readfunc16 = eval_mem_16_inv;
181 
    mem->direct_ops.readfunc16 = eval_mem_16_inv_direct;
182 
    mem->direct_ops.read_dat16 = mem;
183 
  }
184 
  if(!ops->readfunc8) {
185 
    mem->ops.readfunc8 = eval_mem_8_inv;
186 
    mem->direct_ops.readfunc8 = eval_mem_8_inv_direct;
187 
    mem->direct_ops.read_dat8 = mem;
188 
  }
189 
 
190 
  if(!ops->writefunc32) {
191 
    mem->ops.writefunc32 = set_mem_32_inv;
192 
    mem->direct_ops.writefunc32 = set_mem_32_inv_direct;
193 
    mem->direct_ops.write_dat32 = mem;
194 
  }
195 
  if(!ops->writefunc16) {
196 
    mem->ops.writefunc16 = set_mem_16_inv;
197 
    mem->direct_ops.writefunc16 = set_mem_16_inv_direct;
198 
    mem->direct_ops.write_dat16 = mem;
199 
  }
200 
  if(!ops->writefunc8) {
201 
    mem->ops.writefunc8 = set_mem_8_inv;
202 
    mem->direct_ops.writefunc8 = set_mem_8_inv_direct;
203 
    mem->direct_ops.write_dat8 = mem;
204 
  }
205 
 
206 
  if(!ops->writeprog) {
207 
    mem->ops.writeprog = mem->ops.writefunc32;
208 
    mem->ops.writeprog_dat = mem->ops.write_dat32;
209 
  }
210 
 
211 
  if(ops->log) {
212 
    if(!(mem->log = fopen(ops->log, "w")))
213 
      PRINTF("ERR: Unable to open %s to log memory acesses to\n", ops->log);
214 
  }
215 
 
216 
  return mem;
217 30 lampret 
}
218 
 
219 
/* Check if access is to registered area of memory. */
220 1350 nogj 
inline struct dev_memarea *verify_memoryarea(oraddr_t addr)
221 30 lampret 
{
222 239 markom 
  struct dev_memarea *ptmp;
223 221 markom 
 
224 970 simons 
  /* Check memory controller space first */
225 
  if (mc_area && (addr & mc_area->addr_mask) == (mc_area->addr_compare & mc_area->addr_mask))
226 
    return cur_area = mc_area;
227 
 
228 
  /* Check cached value */
229 560 markom 
  if (cur_area && (addr & cur_area->addr_mask) == (cur_area->addr_compare & cur_area->addr_mask))
230 
    return cur_area;
231 
 
232 
  /* When mc is enabled, we must check valid also, otherwise we assume it is nonzero */
233 1375 nogj 
  /* Check list of registered devices. */
234 
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next)
235 
    if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask) && ptmp->valid)
236 
      return cur_area = ptmp;
237 239 markom 
  return cur_area = NULL;
238 30 lampret 
}
239 
 
240 1486 nogj 
/* Sets the valid bit (Used only by memory controllers) */
241 
void set_mem_valid(struct dev_memarea *mem, int valid)
242 882 simons 
{
243 1486 nogj 
  mem->valid = valid;
244 882 simons 
}
245 
 
246 1486 nogj 
/* Adjusts the read and write delays for the memory area pointed to by mem. */
247 
void adjust_rw_delay(struct dev_memarea *mem, int delayr, int delayw)
248 560 markom 
{
249 1486 nogj 
  mem->ops.delayr = delayr;
250 
  mem->ops.delayw = delayw;
251 1319 phoenix 
}
252 560 markom 
 
253 1486 nogj 
uint8_t eval_mem_8_inv(oraddr_t memaddr, void *dat)
254 1319 phoenix 
{
255 1486 nogj 
  except_handle(EXCEPT_BUSERR, cur_vadd);
256 
  return 0;
257 1319 phoenix 
}
258 
 
259 1486 nogj 
uint16_t eval_mem_16_inv(oraddr_t memaddr, void *dat)
260 1319 phoenix 
{
261 1486 nogj 
  except_handle(EXCEPT_BUSERR, cur_vadd);
262 
  return 0;
263 
}
264 1319 phoenix 
 
265 1486 nogj 
uint32_t eval_mem_32_inv(oraddr_t memaddr, void *dat)
266 
{
267 
  except_handle(EXCEPT_BUSERR, cur_vadd);
268 
  return 0;
269 560 markom 
}
270 
 
271 1486 nogj 
void set_mem_8_inv(oraddr_t memaddr, uint8_t val, void *dat)
272 560 markom 
{
273 1486 nogj 
  except_handle(EXCEPT_BUSERR, cur_vadd);
274 1319 phoenix 
}
275 560 markom 
 
276 1486 nogj 
void set_mem_16_inv(oraddr_t memaddr, uint16_t val, void *dat)
277 1319 phoenix 
{
278 1486 nogj 
  except_handle(EXCEPT_BUSERR, cur_vadd);
279 1319 phoenix 
}
280 
 
281 1486 nogj 
void set_mem_32_inv(oraddr_t memaddr, uint32_t val, void *dat)
282 1319 phoenix 
{
283 1486 nogj 
  except_handle(EXCEPT_BUSERR, cur_vadd);
284 
}
285 1319 phoenix 
 
286 1486 nogj 
uint8_t eval_mem_8_inv_direct(oraddr_t memaddr, void *dat)
287 
{
288 
  struct dev_memarea *mem = dat;
289 
 
290 
  PRINTF("ERROR: Invalid 8-bit direct read from memory %"PRIxADDR"\n",
291 
         mem->addr_compare | memaddr);
292 
  return 0;
293 560 markom 
}
294 
 
295 1486 nogj 
uint16_t eval_mem_16_inv_direct(oraddr_t memaddr, void *dat)
296 560 markom 
{
297 1486 nogj 
  struct dev_memarea *mem = dat;
298 
 
299 
  PRINTF("ERROR: Invalid 16-bit direct read from memory %"PRIxADDR"\n",
300 
         mem->addr_compare | memaddr);
301 
  return 0;
302 1319 phoenix 
}
303 560 markom 
 
304 1486 nogj 
uint32_t eval_mem_32_inv_direct(oraddr_t memaddr, void *dat)
305 1319 phoenix 
{
306 1486 nogj 
  struct dev_memarea *mem = dat;
307 
 
308 
  PRINTF("ERROR: Invalid 32-bit direct read from memory %"PRIxADDR"\n",
309 
         mem->addr_compare | memaddr);
310 
  return 0;
311 1319 phoenix 
}
312 
 
313 1486 nogj 
void set_mem_8_inv_direct(oraddr_t memaddr, uint8_t val, void *dat)
314 1319 phoenix 
{
315 1486 nogj 
  struct dev_memarea *mem = dat;
316 1319 phoenix 
 
317 1486 nogj 
  PRINTF("ERROR: Invalid 32-bit direct write to memory %"PRIxADDR"\n",
318 
         mem->addr_compare | memaddr);
319 
}
320 
 
321 
void set_mem_16_inv_direct(oraddr_t memaddr, uint16_t val, void *dat)
322 
{
323 
  struct dev_memarea *mem = dat;
324 
 
325 
  PRINTF("ERROR: Invalid 16-bit direct write to memory %"PRIxADDR"\n",
326 
         mem->addr_compare | memaddr);
327 
}
328 
 
329 
void set_mem_32_inv_direct(oraddr_t memaddr, uint32_t val, void *dat)
330 
{
331 
  struct dev_memarea *mem = dat;
332 
 
333 
  PRINTF("ERROR: Invalid 32-bit direct write to memory %"PRIxADDR"\n",
334 
         mem->addr_compare | memaddr);
335 
}
336 
 
337 
/* For cpu accesses
338 
 *
339 
 * NOTE: This function _is_ only called from eval_mem32 below and
340 
 * {i,d}c_simulate_read.  _Don't_ call it from anywere else.
341 
 */
342 
inline uint32_t evalsim_mem32(oraddr_t memaddr, oraddr_t vaddr)
343 
{
344 
  struct dev_memarea *mem;
345 
 
346 
  if((mem = verify_memoryarea(memaddr))) {
347 
    runtime.sim.mem_cycles += mem->ops.delayr;
348 
    return mem->ops.readfunc32(memaddr & mem->size_mask, mem->ops.read_dat32);
349 
  } else {
350 
    PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
351 
           memaddr);
352 
    except_handle(EXCEPT_BUSERR, vaddr);
353 560 markom 
  }
354 1486 nogj 
 
355 
  return 0;
356 560 markom 
}
357 
 
358 1486 nogj 
/* For cpu accesses
359 
 *
360 
 * NOTE: This function _is_ only called from eval_mem16 below and
361 
 * {i,d}c_simulate_read.  _Don't_ call it from anywere else.
362 
 */
363 
inline uint16_t evalsim_mem16(oraddr_t memaddr, oraddr_t vaddr)
364 
{
365 
  struct dev_memarea *mem;
366 
 
367 
  if((mem = verify_memoryarea(memaddr))) {
368 
    runtime.sim.mem_cycles += mem->ops.delayr;
369 
    return mem->ops.readfunc16(memaddr & mem->size_mask, mem->ops.read_dat16);
370 
  } else {
371 
    PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR")\n",
372 
           memaddr);
373 
    except_handle(EXCEPT_BUSERR, vaddr);
374 
  }
375 
 
376 
  return 0;
377 
}
378 
 
379 
/* For cpu accesses
380 
 *
381 
 * NOTE: This function _is_ only called from eval_mem8 below and
382 
 * {i,d}c_simulate_read.  _Don't_ call it from anywere else.
383 
 */
384 
inline uint8_t evalsim_mem8(oraddr_t memaddr, oraddr_t vaddr)
385 
{
386 
  struct dev_memarea *mem;
387 
 
388 
  if((mem = verify_memoryarea(memaddr))) {
389 
    runtime.sim.mem_cycles += mem->ops.delayr;
390 
    return mem->ops.readfunc8(memaddr & mem->size_mask, mem->ops.read_dat8);
391 
  } else {
392 
    PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR")\n",
393 
           memaddr);
394 
    except_handle(EXCEPT_BUSERR, vaddr);
395 
  }
396 
 
397 
  return 0;
398 
}
399 
 
400 1319 phoenix 
/* Returns 32-bit values from mem array. Big endian version.
401 
 *
402 
 * STATISTICS OK (only used for cpu_access, that is architectural access)
403 
 */
404 1350 nogj 
uint32_t eval_mem32(oraddr_t memaddr,int* breakpoint)
405 2 cvs 
{
406 1350 nogj 
  uint32_t temp;
407 1486 nogj 
  oraddr_t phys_memaddr;
408 123 markom 
 
409 547 markom 
  if (config.sim.mprofile)
410 
    mprofile (memaddr, MPROF_32 | MPROF_READ);
411 
 
412 538 markom 
  if (memaddr & 3) {
413 
    except_handle (EXCEPT_ALIGN, memaddr);
414 
    return 0;
415 
  }
416 557 markom 
 
417 631 simons 
  if (config.debug.enabled)
418 
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
419 
 
420 1486 nogj 
  phys_memaddr = dmmu_translate(memaddr, 0);
421 1386 nogj 
  if (except_pending)
422 574 markom 
    return 0;
423 
 
424 992 simons 
  if (config.dc.enabled)
425 1486 nogj 
    temp = dc_simulate_read(phys_memaddr, memaddr, 4);
426 
  else
427 
    temp = evalsim_mem32(phys_memaddr, memaddr);
428 611 simons 
 
429 550 markom 
  if (config.debug.enabled)
430 270 markom 
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
431 1486 nogj 
 
432 239 markom 
  return temp;
433 66 lampret 
}
434 
 
435 1319 phoenix 
/* for simulator accesses, the ones that cpu wouldn't do
436 
 *
437 
 * STATISTICS OK
438 
 */
439 1487 nogj 
uint32_t eval_direct32(oraddr_t memaddr, int through_mmu, int through_dc)
440 1240 phoenix 
{
441 1486 nogj 
  oraddr_t phys_memaddr;
442 
  struct dev_memarea *mem;
443 1240 phoenix 
 
444 
  if (memaddr & 3) {
445 
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
446 1486 nogj 
    return 0;
447 1240 phoenix 
  }
448 
 
449 1486 nogj 
  phys_memaddr = memaddr;
450 1240 phoenix 
 
451 
  if (through_mmu)
452 1486 nogj 
    phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
453 1240 phoenix 
 
454 
  if (through_dc)
455 1486 nogj 
    return dc_simulate_read(phys_memaddr, memaddr, 4);
456 1240 phoenix 
  else {
457 1486 nogj 
    if((mem = verify_memoryarea(phys_memaddr)))
458 
      return mem->direct_ops.readfunc32(phys_memaddr & mem->size_mask,
459 
                                        mem->direct_ops.read_dat32);
460 
    else
461 
      PRINTF("ERR: 32-bit read out of memory area: %"PRIxADDR" (physical: %"
462 
             PRIxADDR"\n", memaddr, phys_memaddr);
463 1240 phoenix 
  }
464 
 
465 1486 nogj 
  return 0;
466 1240 phoenix 
}
467 
 
468 
 
469 1319 phoenix 
/* Returns 32-bit values from mem array. Big endian version.
470 
 *
471 
 * STATISTICS OK (only used for cpu_access, that is architectural access)
472 
 */
473 1386 nogj 
uint32_t eval_insn(oraddr_t memaddr, int* breakpoint)
474 349 simons 
{
475 1350 nogj 
  uint32_t temp;
476 1486 nogj 
  oraddr_t phys_memaddr;
477 349 simons 
 
478 547 markom 
  if (config.sim.mprofile)
479 
    mprofile (memaddr, MPROF_32 | MPROF_FETCH);
480 532 markom 
//  memaddr = simulate_ic_mmu_fetch(memaddr);
481 1244 hpanther 
 
482 1486 nogj 
  phys_memaddr = memaddr;
483 1452 nogj 
#if !(DYNAMIC_EXECUTION)
484 1486 nogj 
  phys_memaddr = immu_translate(memaddr);
485 1386 nogj 
 
486 
  if (except_pending)
487 
    return 0;
488 1452 nogj 
#endif
489 1386 nogj 
 
490 
  if (config.debug.enabled)
491 
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);
492 
 
493 631 simons 
  if (config.ic.enabled)
494 1486 nogj 
    temp = ic_simulate_fetch(phys_memaddr, memaddr);
495 
  else
496 
    temp = evalsim_mem32(phys_memaddr, memaddr);
497 611 simons 
 
498 1386 nogj 
  if (config.debug.enabled)
499 
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);
500 349 simons 
  return temp;
501 
}
502 
 
503 1452 nogj 
/* Returns 32-bit values from mem array. Big endian version.
504 
 *
505 
 * STATISTICS OK
506 
 */
507 1487 nogj 
uint32_t eval_insn_direct(oraddr_t memaddr, int through_mmu)
508 1452 nogj 
{
509 
  if(through_mmu)
510 
    memaddr = peek_into_itlb(memaddr);
511 
 
512 1487 nogj 
  return eval_direct32(memaddr, 0, 0);
513 1452 nogj 
}
514 
 
515 
 
516 1319 phoenix 
/* Returns 16-bit values from mem array. Big endian version.
517 
 *
518 
 * STATISTICS OK (only used for cpu_access, that is architectural access)
519 
 */
520 1350 nogj 
uint16_t eval_mem16(oraddr_t memaddr,int* breakpoint)
521 2 cvs 
{
522 1350 nogj 
  uint16_t temp;
523 1486 nogj 
  oraddr_t phys_memaddr;
524 547 markom 
 
525 
  if (config.sim.mprofile)
526 
    mprofile (memaddr, MPROF_16 | MPROF_READ);
527 
 
528 538 markom 
  if (memaddr & 1) {
529 
    except_handle (EXCEPT_ALIGN, memaddr);
530 
    return 0;
531 
  }
532 574 markom 
 
533 631 simons 
  if (config.debug.enabled)
534 
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
535 
 
536 1486 nogj 
  phys_memaddr = dmmu_translate(memaddr, 0);
537 1386 nogj 
  if (except_pending)
538 574 markom 
    return 0;
539 66 lampret 
 
540 992 simons 
  if (config.dc.enabled)
541 1486 nogj 
    temp = dc_simulate_read(phys_memaddr, memaddr, 2);
542 
  else
543 
    temp = evalsim_mem16(phys_memaddr, memaddr);
544 611 simons 
 
545 550 markom 
  if (config.debug.enabled)
546 270 markom 
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
547 1486 nogj 
 
548 239 markom 
  return temp;
549 66 lampret 
}
550 
 
551 1319 phoenix 
/* for simulator accesses, the ones that cpu wouldn't do
552 
 *
553 
 * STATISTICS OK.
554 
 */
555 1487 nogj 
uint16_t eval_direct16(oraddr_t memaddr, int through_mmu, int through_dc)
556 1240 phoenix 
{
557 1486 nogj 
  oraddr_t phys_memaddr;
558 
  struct dev_memarea *mem;
559 1240 phoenix 
 
560 1324 phoenix 
  if (memaddr & 1) {
561 1240 phoenix 
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
562 1486 nogj 
    return 0;
563 1240 phoenix 
  }
564 
 
565 1486 nogj 
  phys_memaddr = memaddr;
566 1240 phoenix 
 
567 
  if (through_mmu)
568 1486 nogj 
    phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
569 1240 phoenix 
 
570 
  if (through_dc)
571 1486 nogj 
    return dc_simulate_read(phys_memaddr, memaddr, 2);
572 1240 phoenix 
  else {
573 1486 nogj 
    if((mem = verify_memoryarea(phys_memaddr)))
574 
      return mem->direct_ops.readfunc16(phys_memaddr & mem->size_mask,
575 
                                        mem->direct_ops.read_dat16);
576 
    else
577 
      PRINTF("ERR: 16-bit read out of memory area: %"PRIxADDR" (physical: %"
578 
             PRIxADDR"\n", memaddr, phys_memaddr);
579 1240 phoenix 
  }
580 
 
581 1486 nogj 
  return 0;
582 1240 phoenix 
}
583 
 
584 1319 phoenix 
/* Returns 8-bit values from mem array.
585 
 *
586 
 * STATISTICS OK (only used for cpu_access, that is architectural access)
587 
 */
588 1350 nogj 
uint8_t eval_mem8(oraddr_t memaddr,int* breakpoint)
589 221 markom 
{
590 1350 nogj 
  uint8_t temp;
591 1486 nogj 
  oraddr_t phys_memaddr;
592 547 markom 
 
593 
  if (config.sim.mprofile)
594 
    mprofile (memaddr, MPROF_8 | MPROF_READ);
595 
 
596 631 simons 
  if (config.debug.enabled)
597 
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);  /* 28/05/01 CZ */
598 
 
599 1486 nogj 
  phys_memaddr = dmmu_translate(memaddr, 0);
600 1386 nogj 
  if (except_pending)
601 458 simons 
    return 0;
602 6 lampret 
 
603 992 simons 
  if (config.dc.enabled)
604 1486 nogj 
    temp = dc_simulate_read(phys_memaddr, memaddr, 1);
605 
  else
606 
    temp = evalsim_mem8(phys_memaddr, memaddr);
607 611 simons 
 
608 550 markom 
  if (config.debug.enabled)
609 270 markom 
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
610 239 markom 
  return temp;
611 66 lampret 
}
612 
 
613 1319 phoenix 
/* for simulator accesses, the ones that cpu wouldn't do
614 
 *
615 
 * STATISTICS OK.
616 
 */
617 1487 nogj 
uint8_t eval_direct8(oraddr_t memaddr, int through_mmu, int through_dc)
618 1240 phoenix 
{
619 1486 nogj 
  oraddr_t phys_memaddr;
620 
  struct dev_memarea *mem;
621 1240 phoenix 
 
622 1486 nogj 
  phys_memaddr = memaddr;
623 1240 phoenix 
 
624 
  if (through_mmu)
625 1486 nogj 
    phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
626 1240 phoenix 
 
627 
  if (through_dc)
628 1486 nogj 
    return dc_simulate_read(phys_memaddr, memaddr, 1);
629 1240 phoenix 
  else {
630 1486 nogj 
    if((mem = verify_memoryarea(phys_memaddr)))
631 
      return mem->direct_ops.readfunc8(phys_memaddr & mem->size_mask,
632 
                                       mem->direct_ops.read_dat8);
633 
    else
634 
      PRINTF("ERR: 8-bit read out of memory area: %"PRIxADDR" (physical: %"
635 
             PRIxADDR"\n", memaddr, phys_memaddr);
636 1240 phoenix 
  }
637 
 
638 1486 nogj 
  return 0;
639 1319 phoenix 
}
640 1240 phoenix 
 
641 1486 nogj 
/* For cpu accesses
642 
 *
643 
 * NOTE: This function _is_ only called from set_mem32 below and
644 
 * dc_simulate_write.  _Don't_ call it from anywere else.
645 
 */
646 
inline void setsim_mem32(oraddr_t memaddr, oraddr_t vaddr, uint32_t value)
647 66 lampret 
{
648 1486 nogj 
  struct dev_memarea *mem;
649 1319 phoenix 
 
650 1486 nogj 
  if((mem = verify_memoryarea(memaddr))) {
651 
    cur_vadd = vaddr;
652 
    runtime.sim.mem_cycles += mem->ops.delayw;
653 
    mem->ops.writefunc32(memaddr & mem->size_mask, value, mem->ops.write_dat32);
654 1452 nogj 
#if DYNAMIC_EXECUTION
655 1486 nogj 
    dyn_checkwrite(memaddr);
656 1452 nogj 
#endif
657 239 markom 
  } else {
658 1350 nogj 
    PRINTF("EXCEPTION: write out of memory (32-bit access to %"PRIxADDR")\n",
659 
           memaddr);
660 1486 nogj 
    except_handle(EXCEPT_BUSERR, vaddr);
661 239 markom 
  }
662 2 cvs 
}
663 
 
664 1486 nogj 
/* For cpu accesses
665 
 *
666 
 * NOTE: This function _is_ only called from set_mem16 below and
667 
 * dc_simulate_write.  _Don't_ call it from anywere else.
668 
 */
669 
inline void setsim_mem16(oraddr_t memaddr, oraddr_t vaddr, uint16_t value)
670 66 lampret 
{
671 1486 nogj 
  struct dev_memarea *mem;
672 1319 phoenix 
 
673 1486 nogj 
  if((mem = verify_memoryarea(memaddr))) {
674 
    cur_vadd = vaddr;
675 
    runtime.sim.mem_cycles += mem->ops.delayw;
676 
    mem->ops.writefunc16(memaddr & mem->size_mask, value, mem->ops.write_dat16);
677 1452 nogj 
#if DYNAMIC_EXECUTION
678 1486 nogj 
    dyn_checkwrite(memaddr);
679 1452 nogj 
#endif
680 239 markom 
  } else {
681 1350 nogj 
    PRINTF("EXCEPTION: write out of memory (16-bit access to %"PRIxADDR")\n",
682 
           memaddr);
683 1486 nogj 
    except_handle(EXCEPT_BUSERR, vaddr);
684 239 markom 
  }
685 2 cvs 
}
686 
 
687 1486 nogj 
/* For cpu accesses
688 
 *
689 
 * NOTE: This function _is_ only called from set_mem8 below and
690 
 * dc_simulate_write.  _Don't_ call it from anywere else.
691 
 */
692 
inline void setsim_mem8(oraddr_t memaddr, oraddr_t vaddr, uint8_t value)
693 66 lampret 
{
694 1486 nogj 
  struct dev_memarea *mem;
695 1319 phoenix 
 
696 1486 nogj 
  if((mem = verify_memoryarea(memaddr))) {
697 
    cur_vadd = vaddr;
698 
    runtime.sim.mem_cycles += mem->ops.delayw;
699 
    mem->ops.writefunc8(memaddr & mem->size_mask, value, mem->ops.write_dat8);
700 1452 nogj 
#if DYNAMIC_EXECUTION
701 1486 nogj 
    dyn_checkwrite(memaddr);
702 1452 nogj 
#endif
703 239 markom 
  } else {
704 1350 nogj 
    PRINTF("EXCEPTION: write out of memory (8-bit access to %"PRIxADDR")\n",
705 
           memaddr);
706 1486 nogj 
    except_handle(EXCEPT_BUSERR, vaddr);
707 239 markom 
  }
708 2 cvs 
}
709 30 lampret 
 
710 1319 phoenix 
/* Set mem, 32-bit. Big endian version.
711 
 *
712 1446 nogj 
 * STATISTICS OK. (the only suspicious usage is in sim-cmd.c,
713 1319 phoenix 
 *                 where this instruction is used for patching memory,
714 
 *                 wether this is cpu or architectual access is yet to
715 
 *                 be decided)
716 
 */
717 1350 nogj 
void set_mem32(oraddr_t memaddr, uint32_t value, int* breakpoint)
718 587 markom 
{
719 1486 nogj 
  oraddr_t phys_memaddr;
720 
 
721 587 markom 
  if (config.sim.mprofile)
722 
    mprofile (memaddr, MPROF_32 | MPROF_WRITE);
723 
 
724 
  if (memaddr & 3) {
725 
    except_handle (EXCEPT_ALIGN, memaddr);
726 
    return;
727 
  }
728 
 
729 1486 nogj 
  phys_memaddr = dmmu_translate(memaddr, 1);;
730 587 markom 
  /* If we produced exception don't set anything */
731 1386 nogj 
  if (except_pending)
732 587 markom 
    return;
733 
 
734 
  if (config.debug.enabled) {
735 
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
736 
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
737 
  }
738 
 
739 1486 nogj 
  if(config.dc.enabled)
740 
    dc_simulate_write(phys_memaddr, memaddr, value, 4);
741 
  else
742 
    setsim_mem32(phys_memaddr, memaddr, value);
743 992 simons 
 
744 1218 phoenix 
  if (cur_area && cur_area->log)
745 1350 nogj 
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %08"PRIx32"\n", memaddr,
746 
             value);
747 587 markom 
}
748 
 
749 1319 phoenix 
/*
750 
 * STATISTICS NOT OK.
751 
 */
752 1487 nogj 
void set_direct32(oraddr_t memaddr, uint32_t value, int through_mmu,
753 
                  int through_dc)
754 1240 phoenix 
{
755 1486 nogj 
  oraddr_t phys_memaddr;
756 
  struct dev_memarea *mem;
757 1240 phoenix 
 
758 
  if (memaddr & 3) {
759 
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
760 
    return;
761 
  }
762 
 
763 1486 nogj 
  phys_memaddr = memaddr;
764 1240 phoenix 
 
765 
  if (through_mmu) {
766 
    /* 0 - no write access, we do not want a DPF exception do we ;)
767 
     */
768 1486 nogj 
    phys_memaddr = peek_into_dtlb(memaddr, 1, through_dc);
769 1240 phoenix 
  }
770 
 
771 1486 nogj 
  if(through_dc)
772 
    dc_simulate_write(memaddr, memaddr, value, 4);
773 
  else {
774 
    if((mem = verify_memoryarea(phys_memaddr)))
775 
      mem->direct_ops.writefunc32(phys_memaddr & mem->size_mask, value,
776 
                                  mem->direct_ops.write_dat32);
777 
    else
778 
      PRINTF("ERR: 32-bit write out of memory area: %"PRIxADDR" (physical: %"
779 
             PRIxADDR")\n", memaddr, phys_memaddr);
780 
  }
781 1240 phoenix 
 
782 
  if (cur_area && cur_area->log)
783 1350 nogj 
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %08"PRIx32"\n",
784 
             memaddr, value);
785 1240 phoenix 
}
786 
 
787 
 
788 587 markom 
/* Set mem, 16-bit. Big endian version. */
789 
 
790 1350 nogj 
void set_mem16(oraddr_t memaddr, uint16_t value, int* breakpoint)
791 587 markom 
{
792 1486 nogj 
  oraddr_t phys_memaddr;
793 
 
794 587 markom 
  if (config.sim.mprofile)
795 
    mprofile (memaddr, MPROF_16 | MPROF_WRITE);
796 
 
797 
  if (memaddr & 1) {
798 
    except_handle (EXCEPT_ALIGN, memaddr);
799 
    return;
800 
  }
801 
 
802 1486 nogj 
  phys_memaddr = dmmu_translate(memaddr, 1);;
803 587 markom 
  /* If we produced exception don't set anything */
804 1386 nogj 
  if (except_pending)
805 587 markom 
    return;
806 
 
807 
  if (config.debug.enabled) {
808 
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
809 
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
810 
  }
811 
 
812 1486 nogj 
  if(config.dc.enabled)
813 
    dc_simulate_write(phys_memaddr, memaddr, value, 2);
814 
  else
815 
    setsim_mem16(phys_memaddr, memaddr, value);
816 992 simons 
 
817 1218 phoenix 
  if (cur_area && cur_area->log)
818 1350 nogj 
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %04"PRIx16"\n", memaddr,
819 
             value);
820 587 markom 
}
821 
 
822 1319 phoenix 
/*
823 
 * STATISTICS NOT OK.
824 
 */
825 1487 nogj 
void set_direct16(oraddr_t memaddr, uint16_t value, int through_mmu,
826 
                  int through_dc)
827 1240 phoenix 
{
828 1486 nogj 
  oraddr_t phys_memaddr;
829 
  struct dev_memarea *mem;
830 1240 phoenix 
 
831 1324 phoenix 
  if (memaddr & 1) {
832 1240 phoenix 
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
833 
    return;
834 
  }
835 
 
836 1486 nogj 
  phys_memaddr = memaddr;
837 1240 phoenix 
 
838 
  if (through_mmu) {
839 
    /* 0 - no write access, we do not want a DPF exception do we ;)
840 
     */
841 1486 nogj 
    phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
842 1240 phoenix 
  }
843 
 
844 1486 nogj 
  if(through_dc)
845 
    dc_simulate_write(memaddr, memaddr, value, 2);
846 
  else {
847 
    if((mem = verify_memoryarea(phys_memaddr)))
848 
      mem->direct_ops.writefunc16(phys_memaddr & mem->size_mask, value,
849 
                                  mem->direct_ops.write_dat16);
850 
    else
851 
      PRINTF("ERR: 16-bit write out of memory area: %"PRIxADDR" (physical: %"
852 
             PRIxADDR"\n", memaddr, phys_memaddr);
853 
  }
854 1240 phoenix 
 
855 
  if (cur_area && cur_area->log)
856 1350 nogj 
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %04"PRIx16"\n",
857 
             memaddr, value);
858 1240 phoenix 
}
859 
 
860 587 markom 
/* Set mem, 8-bit. */
861 1350 nogj 
void set_mem8(oraddr_t memaddr, uint8_t value, int* breakpoint)
862 587 markom 
{
863 1486 nogj 
  oraddr_t phys_memaddr;
864 
 
865 587 markom 
  if (config.sim.mprofile)
866 
    mprofile (memaddr, MPROF_8 | MPROF_WRITE);
867 
 
868 1486 nogj 
  phys_memaddr = memaddr;
869 
 
870 
  phys_memaddr = dmmu_translate(memaddr, 1);;
871 587 markom 
  /* If we produced exception don't set anything */
872 1386 nogj 
  if (except_pending) return;
873 587 markom 
 
874 
  if (config.debug.enabled) {
875 
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
876 
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
877 
  }
878 
 
879 1486 nogj 
  if(config.dc.enabled)
880 
    dc_simulate_write(phys_memaddr, memaddr, value, 1);
881 
  else
882 
    setsim_mem8(phys_memaddr, memaddr, value);
883 992 simons 
 
884 1218 phoenix 
  if (cur_area && cur_area->log)
885 1350 nogj 
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %02"PRIx8"\n", memaddr,
886 
             value);
887 587 markom 
}
888 
 
889 1319 phoenix 
/*
890 
 * STATISTICS NOT OK.
891 
 */
892 1487 nogj 
void set_direct8(oraddr_t memaddr, uint8_t value, int through_mmu,
893 
                 int through_dc)
894 1240 phoenix 
{
895 1486 nogj 
  oraddr_t phys_memaddr;
896 
  struct dev_memarea *mem;
897 1240 phoenix 
 
898 1486 nogj 
  phys_memaddr = memaddr;
899 1240 phoenix 
 
900 
  if (through_mmu) {
901 
    /* 0 - no write access, we do not want a DPF exception do we ;)
902 
     */
903 1486 nogj 
    phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
904 1240 phoenix 
  }
905 
 
906 1486 nogj 
  if(through_dc)
907 
    dc_simulate_write(phys_memaddr, memaddr, value, 1);
908 
  else {
909 
    if((mem = verify_memoryarea(phys_memaddr)))
910 
      mem->direct_ops.writefunc8(phys_memaddr & mem->size_mask, value,
911 
                                 mem->direct_ops.write_dat8);
912 
    else
913 
      PRINTF("ERR: 8-bit write out of memory area: %"PRIxADDR" (physical: %"
914 
             PRIxADDR"\n", memaddr, phys_memaddr);
915 
  }
916 1240 phoenix 
 
917 
  if (cur_area && cur_area->log)
918 1350 nogj 
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %02"PRIx8"\n",
919 
             memaddr, value);
920 1240 phoenix 
}
921 
 
922 
 
923 1486 nogj 
/* set_program32 - same as set_direct32, but it also writes to memory that is
924 
 *                 non-writeable to the rest of the sim.  Used to do program
925 
 *                 loading.
926 
 */
927 
void set_program32(oraddr_t memaddr, uint32_t value)
928 
{
929 
  struct dev_memarea *mem;
930 
 
931 
  if (memaddr & 3) {
932 
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
933 
    return;
934 
  }
935 
 
936 
  if((mem = verify_memoryarea(memaddr))) {
937 
    mem->ops.writeprog(memaddr & mem->size_mask, value, mem->ops.writeprog_dat);
938 
  } else
939 
    PRINTF("ERR: 32-bit program load out of memory area: %"PRIxADDR"\n",
940 
           memaddr);
941 
}
942 
 
943 1350 nogj 
void dumpmemory(oraddr_t from, oraddr_t to, int disasm, int nl)
944 361 markom 
{
945 1350 nogj 
  oraddr_t i, j;
946 361 markom 
  struct label_entry *tmp;
947 
  int ilen = disasm ? 4 : 16;
948 
 
949 
  for(i = from; i < to; i += ilen) {
950 1350 nogj 
    PRINTF("%"PRIxADDR": ", i);
951 361 markom 
    for (j = 0; j < ilen;) {
952 
      if (!disasm) {
953 
        tmp = NULL;
954 1350 nogj 
        if (verify_memoryarea(i + j)) {
955 361 markom 
          struct label_entry *entry;
956 
          entry = get_label(i + j);
957 
          if (entry)
958 997 markom 
            PRINTF("(%s)", entry->name);
959 1487 nogj 
          PRINTF("%02"PRIx8" ", eval_direct8(i + j, 0, 0));
960 997 markom 
        } else PRINTF("XX ");
961 361 markom 
        j++;
962 
      } else {
963 1487 nogj 
        uint32_t _insn = eval_direct32(i, 0, 0);
964 361 markom 
        int index = insn_decode (_insn);
965 
        int len = insn_len (index);
966 
 
967 
        tmp = NULL;
968 1350 nogj 
        if (verify_memoryarea(i + j)) {
969 361 markom 
          struct label_entry *entry;
970 
          entry = get_label(i + j);
971 
          if (entry)
972 997 markom 
            PRINTF("(%s)", entry->name);
973 361 markom 
 
974 1350 nogj 
          PRINTF(": %08"PRIx32" ", _insn);
975 361 markom 
          if (index >= 0) {
976 
            disassemble_insn (_insn);
977 997 markom 
            PRINTF(" %s", disassembled);
978 361 markom 
          } else
979 997 markom 
            PRINTF("<invalid>");
980 
        } else PRINTF("XXXXXXXX");
981 361 markom 
        j += len;
982 
      }
983 
    }
984 
    if (nl)
985 997 markom 
      PRINTF ("\n");
986 361 markom 
  }
987 
}
988 
 
989 426 markom 
/* Closes files, etc. */
990 
 
991 1486 nogj 
void done_memory_table (void)
992 426 markom 
{
993 
  struct dev_memarea *ptmp;
994 
 
995 
  /* Check list of registered devices. */
996 
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
997 
    if (ptmp->log)
998 
      fclose (ptmp->log);
999 
  }
1000 
}
1001 427 markom 
 
1002 
/* Displays current memory configuration */
1003 
 
1004 1486 nogj 
void memory_table_status (void)
1005 427 markom 
{
1006 
  struct dev_memarea *ptmp;
1007 
 
1008 
  /* Check list of registered devices. */
1009 
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
1010 1486 nogj 
    PRINTF ("addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %"PRIx32"\n",
1011 427 markom 
      ptmp->addr_mask, ptmp->addr_compare, ptmp->addr_compare | bit_mask (ptmp->size),
1012 1486 nogj 
      ptmp->size);
1013 997 markom 
    PRINTF ("\t");
1014 1486 nogj 
    if (ptmp->ops.delayr >= 0)
1015 
      PRINTF ("read delay = %i cycles, ", ptmp->ops.delayr);
1016 427 markom 
    else
1017 997 markom 
      PRINTF ("reads not possible, ");
1018 427 markom 
 
1019 1486 nogj 
    if (ptmp->ops.delayw >= 0)
1020 
      PRINTF ("write delay = %i cycles", ptmp->ops.delayw);
1021 427 markom 
    else
1022 997 markom 
      PRINTF ("writes not possible");
1023 427 markom 
 
1024 
    if (ptmp->log)
1025 997 markom 
      PRINTF (", (logged)\n");
1026 427 markom 
    else
1027 997 markom 
      PRINTF ("\n");
1028 427 markom 
  }
1029 
}
1030 433 markom 
 
1031 
/* Outputs time in pretty form to dest string */
1032 
 
1033 897 markom 
char *generate_time_pretty (char *dest, long time_ps)
1034 433 markom 
{
1035 
  int exp3 = 0;
1036 
  if (time_ps) {
1037 
    while ((time_ps % 1000) == 0) {
1038 
      time_ps /= 1000;
1039 
      exp3++;
1040 
    }
1041 
  }
1042 1308 phoenix 
  sprintf (dest, "%li%cs", time_ps, "pnum"[exp3]);
1043 897 markom 
  return dest;
1044 433 markom 
}

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