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[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [cpu/] [or32/] [insnset.c] - Blame information for rev 1780

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1 706 markom 
/* execute.c -- Instruction specific functions.
2 
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
3 
                 2000-2002 Marko Mlinar, markom@opencores.org
4 
 
5 
This file is part of OpenRISC 1000 Architectural Simulator.
6 
 
7 
This program is free software; you can redistribute it and/or modify
8 
it under the terms of the GNU General Public License as published by
9 
the Free Software Foundation; either version 2 of the License, or
10 
(at your option) any later version.
11 
 
12 
This program is distributed in the hope that it will be useful,
13 
but WITHOUT ANY WARRANTY; without even the implied warranty of
14 
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 
GNU General Public License for more details.
16 
 
17 
You should have received a copy of the GNU General Public License
18 
along with this program; if not, write to the Free Software
19 
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
20 
 
21 
INSTRUCTION (l_add) {
22 1350 nogj 
  orreg_t temp1, temp2, temp3;
23 
  int8_t temp4;
24 706 markom 
 
25 1350 nogj 
  temp2 = (orreg_t)PARAM2;
26 
  temp3 = (orreg_t)PARAM1;
27 1170 csanchez 
  temp1 = temp2 + temp3;
28 1342 nogj 
  SET_PARAM0(temp1);
29 706 markom 
  set_ov_flag (temp1);
30 
  if (ARITH_SET_FLAG) {
31 1513 nogj 
    if(!temp1)
32 1506 nogj 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
33 
    else
34 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
35 706 markom 
  }
36 1350 nogj 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
37 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
38 1170 csanchez 
  else
39 1506 nogj 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
40 706 markom 
 
41 
  temp4 = temp1;
42 
  if (temp4 == temp1)
43 1244 hpanther 
    or1k_mstats.byteadd++;
44 706 markom 
}
45 1170 csanchez 
INSTRUCTION (l_addc) {
46 1350 nogj 
  orreg_t temp1, temp2, temp3;
47 
  int8_t temp4;
48 1170 csanchez 
 
49 1350 nogj 
  temp2 = (orreg_t)PARAM2;
50 
  temp3 = (orreg_t)PARAM1;
51 1506 nogj 
  temp1 = temp2 + temp3;
52 
  if(cpu_state.sprs[SPR_SR] & SPR_SR_CY)
53 
    temp1++;
54 1342 nogj 
  SET_PARAM0(temp1);
55 1170 csanchez 
  set_ov_flag (temp1);
56 
  if (ARITH_SET_FLAG) {
57 1513 nogj 
    if(!temp1)
58 1506 nogj 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
59 
    else
60 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
61 1170 csanchez 
  }
62 1350 nogj 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
63 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
64 1170 csanchez 
  else
65 1506 nogj 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
66 1170 csanchez 
 
67 
  temp4 = temp1;
68 
  if (temp4 == temp1)
69 1244 hpanther 
    or1k_mstats.byteadd++;
70 1170 csanchez 
}
71 706 markom 
INSTRUCTION (l_sw) {
72 
  int old_cyc = 0;
73 1375 nogj 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
74 1342 nogj 
  set_mem32(PARAM0, PARAM1, &breakpoint);
75 706 markom 
  if (config.cpu.sbuf_len) {
76 884 markom 
    int t = runtime.sim.mem_cycles;
77 
    runtime.sim.mem_cycles = old_cyc;
78 706 markom 
    sbuf_store (t - old_cyc);
79 
  }
80 
}
81 
INSTRUCTION (l_sb) {
82 
  int old_cyc = 0;
83 1375 nogj 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
84 1342 nogj 
  set_mem8(PARAM0, PARAM1, &breakpoint);
85 706 markom 
  if (config.cpu.sbuf_len) {
86 884 markom 
    int t = runtime.sim.mem_cycles;
87 
    runtime.sim.mem_cycles = old_cyc;
88 706 markom 
    sbuf_store (t- old_cyc);
89 
  }
90 
}
91 
INSTRUCTION (l_sh) {
92 
  int old_cyc = 0;
93 1375 nogj 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
94 1342 nogj 
  set_mem16(PARAM0, PARAM1, &breakpoint);
95 706 markom 
  if (config.cpu.sbuf_len) {
96 884 markom 
    int t = runtime.sim.mem_cycles;
97 
    runtime.sim.mem_cycles = old_cyc;
98 706 markom 
    sbuf_store (t - old_cyc);
99 
  }
100 
}
101 
INSTRUCTION (l_lwz) {
102 1350 nogj 
  uint32_t val;
103 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
104 1342 nogj 
  val = eval_mem32(PARAM1, &breakpoint);
105 706 markom 
  /* If eval operand produced exception don't set anything */
106 1386 nogj 
  if (!except_pending)
107 1342 nogj 
    SET_PARAM0(val);
108 706 markom 
}
109 
INSTRUCTION (l_lbs) {
110 1350 nogj 
  int8_t val;
111 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
112 1342 nogj 
  val = eval_mem8(PARAM1, &breakpoint);
113 706 markom 
  /* If eval opreand produced exception don't set anything */
114 1386 nogj 
  if (!except_pending)
115 1342 nogj 
    SET_PARAM0(val);
116 706 markom 
}
117 
INSTRUCTION (l_lbz) {
118 1350 nogj 
  uint8_t val;
119 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
120 1342 nogj 
  val = eval_mem8(PARAM1, &breakpoint);
121 706 markom 
  /* If eval opreand produced exception don't set anything */
122 1386 nogj 
  if (!except_pending)
123 1342 nogj 
    SET_PARAM0(val);
124 706 markom 
}
125 
INSTRUCTION (l_lhs) {
126 1350 nogj 
  int16_t val;
127 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
128 1342 nogj 
  val = eval_mem16(PARAM1, &breakpoint);
129 706 markom 
  /* If eval opreand produced exception don't set anything */
130 1386 nogj 
  if (!except_pending)
131 1342 nogj 
    SET_PARAM0(val);
132 706 markom 
}
133 
INSTRUCTION (l_lhz) {
134 1350 nogj 
  uint16_t val;
135 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
136 1342 nogj 
  val = eval_mem16(PARAM1, &breakpoint);
137 706 markom 
  /* If eval opreand produced exception don't set anything */
138 1386 nogj 
  if (!except_pending)
139 1342 nogj 
    SET_PARAM0(val);
140 706 markom 
}
141 
INSTRUCTION (l_movhi) {
142 1342 nogj 
  SET_PARAM0(PARAM1 << 16);
143 706 markom 
}
144 
INSTRUCTION (l_and) {
145 1350 nogj 
  uorreg_t temp1;
146 1342 nogj 
  temp1 = PARAM1 & PARAM2;
147 
  set_ov_flag (temp1);
148 
  SET_PARAM0(temp1);
149 706 markom 
  if (ARITH_SET_FLAG) {
150 1513 nogj 
    if(!temp1)
151 1506 nogj 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
152 
    else
153 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
154 706 markom 
  }
155 
}
156 
INSTRUCTION (l_or) {
157 1350 nogj 
  uorreg_t temp1;
158 1342 nogj 
  temp1 = PARAM1 | PARAM2;
159 
  set_ov_flag (temp1);
160 
  SET_PARAM0(temp1);
161 706 markom 
}
162 
INSTRUCTION (l_xor) {
163 1350 nogj 
  uorreg_t temp1;
164 1342 nogj 
  temp1 = PARAM1 ^ PARAM2;
165 
  set_ov_flag (temp1);
166 
  SET_PARAM0(temp1);
167 706 markom 
}
168 
INSTRUCTION (l_sub) {
169 1350 nogj 
  orreg_t temp1;
170 
  temp1 = (orreg_t)PARAM1 - (orreg_t)PARAM2;
171 1342 nogj 
  set_ov_flag (temp1);
172 
  SET_PARAM0(temp1);
173 706 markom 
}
174 
/*int mcount = 0;*/
175 
INSTRUCTION (l_mul) {
176 1350 nogj 
  orreg_t temp1;
177 706 markom 
 
178 1350 nogj 
  temp1 = (orreg_t)PARAM1 * (orreg_t)PARAM2;
179 1342 nogj 
  set_ov_flag (temp1);
180 
  SET_PARAM0(temp1);
181 706 markom 
  /*if (!(mcount++ & 1023)) {
182 997 markom 
    PRINTF ("[%i]\n",mcount);
183 706 markom 
    }*/
184 
}
185 
INSTRUCTION (l_div) {
186 1350 nogj 
  orreg_t temp3, temp2, temp1;
187 706 markom 
 
188 1342 nogj 
  temp3 = PARAM2;
189 
  temp2 = PARAM1;
190 706 markom 
  if (temp3)
191 
    temp1 = temp2 / temp3;
192 
  else {
193 1432 nogj 
    except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
194 706 markom 
    return;
195 
  }
196 1342 nogj 
  set_ov_flag (temp1);
197 
  SET_PARAM0(temp1);
198 706 markom 
}
199 
INSTRUCTION (l_divu) {
200 1350 nogj 
  uorreg_t temp3, temp2, temp1;
201 706 markom 
 
202 1342 nogj 
  temp3 = PARAM2;
203 
  temp2 = PARAM1;
204 
  if (temp3)
205 
    temp1 = temp2 / temp3;
206 
  else {
207 1432 nogj 
    except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
208 1342 nogj 
    return;
209 
  }
210 
  set_ov_flag (temp1);
211 
  SET_PARAM0(temp1);
212 884 markom 
  /* runtime.sim.cycles += 16; */
213 706 markom 
}
214 
INSTRUCTION (l_sll) {
215 1350 nogj 
  uorreg_t temp1;
216 1342 nogj 
 
217 
  temp1 = PARAM1 << PARAM2;
218 
  set_ov_flag (temp1);
219 
  SET_PARAM0(temp1);
220 884 markom 
  /* runtime.sim.cycles += 2; */
221 706 markom 
}
222 
INSTRUCTION (l_sra) {
223 1350 nogj 
  orreg_t temp1;
224 706 markom 
 
225 1350 nogj 
  temp1 = (orreg_t)PARAM1 >> PARAM2;
226 1342 nogj 
  set_ov_flag (temp1);
227 
  SET_PARAM0(temp1);
228 884 markom 
  /* runtime.sim.cycles += 2; */
229 706 markom 
}
230 
INSTRUCTION (l_srl) {
231 1350 nogj 
  uorreg_t temp1;
232 1342 nogj 
  temp1 = PARAM1 >> PARAM2;
233 
  set_ov_flag (temp1);
234 
  SET_PARAM0(temp1);
235 884 markom 
  /* runtime.sim.cycles += 2; */
236 706 markom 
}
237 
INSTRUCTION (l_bf) {
238 
  if (config.bpb.enabled) {
239 1432 nogj 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
240 1513 nogj 
    or1k_mstats.bf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0][fwd]++;
241 
    bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0);
242 706 markom 
  }
243 1513 nogj 
  if(cpu_state.sprs[SPR_SR] & SPR_SR_F) {
244 1432 nogj 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
245 706 markom 
    btic_update(pcnext);
246 
    next_delay_insn = 1;
247 
  } else {
248 1432 nogj 
    btic_update(cpu_state.pc);
249 706 markom 
  }
250 
}
251 
INSTRUCTION (l_bnf) {
252 
  if (config.bpb.enabled) {
253 1432 nogj 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
254 1513 nogj 
    or1k_mstats.bnf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1][fwd]++;
255 
    bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1);
256 706 markom 
  }
257 1513 nogj 
  if (!(cpu_state.sprs[SPR_SR] & SPR_SR_F)) {
258 1432 nogj 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
259 706 markom 
    btic_update(pcnext);
260 
    next_delay_insn = 1;
261 
  } else {
262 1432 nogj 
    btic_update(cpu_state.pc);
263 706 markom 
  }
264 
}
265 
INSTRUCTION (l_j) {
266 1432 nogj 
  cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
267 706 markom 
  next_delay_insn = 1;
268 
}
269 
INSTRUCTION (l_jal) {
270 1432 nogj 
  cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
271 706 markom 
 
272 1432 nogj 
  set_reg(LINK_REGNO, cpu_state.pc + 8);
273 706 markom 
  next_delay_insn = 1;
274 
  if (config.sim.profile) {
275 
    struct label_entry *tmp;
276 1432 nogj 
    if (verify_memoryarea(cpu_state.pc_delay) && (tmp = get_label (cpu_state.pc_delay)))
277 1350 nogj 
      fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" %s\n",
278 1432 nogj 
               runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
279 
               tmp->name);
280 706 markom 
    else
281 1350 nogj 
      fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" @%"PRIxADDR"\n",
282 1432 nogj 
               runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
283 
               cpu_state.pc_delay);
284 706 markom 
  }
285 
}
286 
INSTRUCTION (l_jalr) {
287 1432 nogj 
  cpu_state.pc_delay = PARAM0;
288 
  set_reg(LINK_REGNO, cpu_state.pc + 8);
289 706 markom 
  next_delay_insn = 1;
290 
}
291 
INSTRUCTION (l_jr) {
292 1432 nogj 
  cpu_state.pc_delay = PARAM0;
293 706 markom 
  next_delay_insn = 1;
294 
  if (config.sim.profile)
295 1350 nogj 
    fprintf (runtime.sim.fprof, "-%08llX %"PRIxADDR"\n", runtime.sim.cycles,
296 1432 nogj 
             cpu_state.pc_delay);
297 706 markom 
}
298 
INSTRUCTION (l_rfe) {
299 1508 nogj 
  pcnext = cpu_state.sprs[SPR_EPCR_BASE];
300 
  mtspr(SPR_SR, cpu_state.sprs[SPR_ESR_BASE]);
301 706 markom 
}
302 
INSTRUCTION (l_nop) {
303 1350 nogj 
  oraddr_t stackaddr;
304 
  uint32_t k = PARAM0;
305 706 markom 
  switch (k) {
306 
    case NOP_NOP:
307 
      break;
308 
    case NOP_EXIT:
309 1350 nogj 
      PRINTF("exit(%"PRIdREG")\n", evalsim_reg (3));
310 1343 nogj 
      fprintf(stderr, "@reset : cycles %lld, insn #%lld\n",
311 
              runtime.sim.reset_cycles, runtime.cpu.reset_instructions);
312 
      fprintf(stderr, "@exit  : cycles %lld, insn #%lld\n", runtime.sim.cycles,
313 
              runtime.cpu.instructions);
314 
      fprintf(stderr, " diff  : cycles %lld, insn #%lld\n",
315 
              runtime.sim.cycles - runtime.sim.reset_cycles,
316 
              runtime.cpu.instructions - runtime.cpu.reset_instructions);
317 706 markom 
      if (config.debug.gdb_enabled)
318 
        set_stall_state (1);
319 
      else
320 1471 nogj 
        sim_done();
321 706 markom 
      break;
322 1319 phoenix 
    case NOP_CNT_RESET:
323 
      PRINTF("****************** counters reset ******************\n");
324 
      PRINTF("cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
325 
      PRINTF("****************** counters reset ******************\n");
326 
      runtime.sim.reset_cycles = runtime.sim.cycles;
327 
      runtime.cpu.reset_instructions = runtime.cpu.instructions;
328 
      break;
329 706 markom 
    case NOP_PRINTF:
330 1350 nogj 
      stackaddr = evalsim_reg(4);
331 
      simprintf(stackaddr, evalsim_reg(3));
332 706 markom 
      debug(5, "simprintf %x\n", stackaddr);
333 
      break;
334 
    case NOP_REPORT:
335 1438 nogj 
      PRINTF("report(0x%"PRIxREG");\n", evalsim_reg(3));
336 706 markom 
    default:
337 
      if (k >= NOP_REPORT_FIRST && k <= NOP_REPORT_LAST)
338 1350 nogj 
      PRINTF("report %i (0x%"PRIxREG");\n", k - NOP_REPORT_FIRST,
339 
             evalsim_reg(3));
340 706 markom 
      break;
341 
  }
342 
}
343 
INSTRUCTION (l_sfeq) {
344 1513 nogj 
  if(PARAM0 == PARAM1)
345 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
346 
  else
347 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
348 706 markom 
}
349 
INSTRUCTION (l_sfne) {
350 1513 nogj 
  if(PARAM0 != PARAM1)
351 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
352 
  else
353 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
354 706 markom 
}
355 
INSTRUCTION (l_sfgts) {
356 1513 nogj 
  if((orreg_t)PARAM0 > (orreg_t)PARAM1)
357 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
358 
  else
359 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
360 706 markom 
}
361 
INSTRUCTION (l_sfges) {
362 1513 nogj 
  if((orreg_t)PARAM0 >= (orreg_t)PARAM1)
363 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
364 
  else
365 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
366 706 markom 
}
367 
INSTRUCTION (l_sflts) {
368 1513 nogj 
  if((orreg_t)PARAM0 < (orreg_t)PARAM1)
369 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
370 
  else
371 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
372 706 markom 
}
373 
INSTRUCTION (l_sfles) {
374 1513 nogj 
  if((orreg_t)PARAM0 <= (orreg_t)PARAM1)
375 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
376 
  else
377 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
378 706 markom 
}
379 
INSTRUCTION (l_sfgtu) {
380 1513 nogj 
  if(PARAM0 > PARAM1)
381 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
382 
  else
383 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
384 706 markom 
}
385 
INSTRUCTION (l_sfgeu) {
386 1513 nogj 
  if(PARAM0 >= PARAM1)
387 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
388 
  else
389 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
390 706 markom 
}
391 
INSTRUCTION (l_sfltu) {
392 1513 nogj 
  if(PARAM0 < PARAM1)
393 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
394 
  else
395 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
396 706 markom 
}
397 
INSTRUCTION (l_sfleu) {
398 1513 nogj 
  if(PARAM0 <= PARAM1)
399 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
400 
  else
401 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
402 706 markom 
}
403 
INSTRUCTION (l_extbs) {
404 1350 nogj 
  int8_t x;
405 1342 nogj 
  x = PARAM1;
406 1350 nogj 
  SET_PARAM0((orreg_t)x);
407 706 markom 
}
408 
INSTRUCTION (l_extbz) {
409 1350 nogj 
  uint8_t x;
410 1342 nogj 
  x = PARAM1;
411 1350 nogj 
  SET_PARAM0((uorreg_t)x);
412 706 markom 
}
413 
INSTRUCTION (l_exths) {
414 1350 nogj 
  int16_t x;
415 1342 nogj 
  x = PARAM1;
416 1350 nogj 
  SET_PARAM0((orreg_t)x);
417 706 markom 
}
418 
INSTRUCTION (l_exthz) {
419 1350 nogj 
  uint16_t x;
420 1342 nogj 
  x = PARAM1;
421 1350 nogj 
  SET_PARAM0((uorreg_t)x);
422 706 markom 
}
423 
INSTRUCTION (l_extws) {
424 1350 nogj 
  int32_t x;
425 1342 nogj 
  x = PARAM1;
426 1350 nogj 
  SET_PARAM0((orreg_t)x);
427 706 markom 
}
428 
INSTRUCTION (l_extwz) {
429 1350 nogj 
  uint32_t x;
430 1342 nogj 
  x = PARAM1;
431 1350 nogj 
  SET_PARAM0((uorreg_t)x);
432 706 markom 
}
433 
INSTRUCTION (l_mtspr) {
434 1350 nogj 
  uint16_t regno = PARAM0 + PARAM2;
435 
  uorreg_t value = PARAM1;
436 706 markom 
 
437 1508 nogj 
  if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
438 706 markom 
    mtspr(regno, value);
439 
  else {
440 997 markom 
    PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");
441 1471 nogj 
    sim_done();
442 706 markom 
  }
443 
}
444 
INSTRUCTION (l_mfspr) {
445 1350 nogj 
  uint16_t regno = PARAM1 + PARAM2;
446 
  uorreg_t value = mfspr(regno);
447 706 markom 
 
448 1508 nogj 
  if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
449 1342 nogj 
    SET_PARAM0(value);
450 706 markom 
  else {
451 1342 nogj 
    SET_PARAM0(0);
452 997 markom 
    PRINTF("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");
453 1471 nogj 
    sim_done();
454 706 markom 
  }
455 
}
456 
INSTRUCTION (l_sys) {
457 1508 nogj 
  except_handle(EXCEPT_SYSCALL, cpu_state.sprs[SPR_EEAR_BASE]);
458 706 markom 
}
459 
INSTRUCTION (l_trap) {
460 
  /* TODO: some SR related code here! */
461 1508 nogj 
  except_handle(EXCEPT_TRAP, cpu_state.sprs[SPR_EEAR_BASE]);
462 706 markom 
}
463 
INSTRUCTION (l_mac) {
464 1508 nogj 
  uorreg_t lo, hi;
465 706 markom 
  LONGEST l;
466 1350 nogj 
  orreg_t x, y;
467 
 
468 1508 nogj 
  lo = cpu_state.sprs[SPR_MACLO];
469 
  hi = cpu_state.sprs[SPR_MACHI];
470 1342 nogj 
  x = PARAM0;
471 
  y = PARAM1;
472 1350 nogj 
  PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y);
473 706 markom 
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
474 
  l += (LONGEST) x * (LONGEST) y;
475 
 
476 
  /* This implementation is very fast - it needs only one cycle for mac.  */
477 
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
478 
  hi = ((LONGEST)l) >> 32;
479 1508 nogj 
  cpu_state.sprs[SPR_MACLO] = lo;
480 
  cpu_state.sprs[SPR_MACHI] = hi;
481 1557 nogj 
  PRINTF ("(%"PRIxREG",%"PRIxREG"\n", hi, lo);
482 706 markom 
}
483 
INSTRUCTION (l_msb) {
484 1508 nogj 
  uorreg_t lo, hi;
485 706 markom 
  LONGEST l;
486 1350 nogj 
  orreg_t x, y;
487 
 
488 1508 nogj 
  lo = cpu_state.sprs[SPR_MACLO];
489 
  hi = cpu_state.sprs[SPR_MACHI];
490 1342 nogj 
  x = PARAM0;
491 
  y = PARAM1;
492 1350 nogj 
 
493 
  PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y);
494 
 
495 706 markom 
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
496 1342 nogj 
  l -= x * y;
497 706 markom 
 
498 
  /* This implementation is very fast - it needs only one cycle for msb.  */
499 
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
500 
  hi = ((LONGEST)l) >> 32;
501 1508 nogj 
  cpu_state.sprs[SPR_MACLO] = lo;
502 
  cpu_state.sprs[SPR_MACHI] = hi;
503 1557 nogj 
  PRINTF ("(%"PRIxREG",%"PRIxREG")\n", hi, lo);
504 706 markom 
}
505 
INSTRUCTION (l_macrc) {
506 1508 nogj 
  uorreg_t lo, hi;
507 706 markom 
  LONGEST l;
508 
  /* No need for synchronization here -- all MAC instructions are 1 cycle long.  */
509 1508 nogj 
  lo =  cpu_state.sprs[SPR_MACLO];
510 
  hi =  cpu_state.sprs[SPR_MACHI];
511 706 markom 
  l = (ULONGEST) lo | ((LONGEST)hi << 32);
512 
  l >>= 28;
513 997 markom 
  //PRINTF ("<%08x>\n", (unsigned long)l);
514 1350 nogj 
  SET_PARAM0((orreg_t)l);
515 1508 nogj 
  cpu_state.sprs[SPR_MACLO] = 0;
516 
  cpu_state.sprs[SPR_MACHI] = 0;
517 706 markom 
}
518 
INSTRUCTION (l_cmov) {
519 1513 nogj 
  SET_PARAM0(cpu_state.sprs[SPR_SR] & SPR_SR_F ? PARAM1 : PARAM2);
520 706 markom 
}
521 1338 andreje 
INSTRUCTION (l_ff1) {
522 1342 nogj 
  SET_PARAM0(ffs(PARAM1));
523 1338 andreje 
}
524 720 markom 
/******* Floating point instructions *******/
525 
/* Single precision */
526 
INSTRUCTION (lf_add_s) {
527 1350 nogj 
  SET_PARAM0((float)PARAM1 + (float)PARAM2);
528 720 markom 
}
529 
INSTRUCTION (lf_div_s) {
530 1350 nogj 
  SET_PARAM0((float)PARAM1 / (float)PARAM2);
531 720 markom 
}
532 1303 phoenix 
INSTRUCTION (lf_ftoi_s) {
533 
//  set_operand32(0, freg[get_operand(1)], &breakpoint);
534 720 markom 
}
535 
INSTRUCTION (lf_itof_s) {
536 1303 phoenix 
//  freg[get_operand(0)] = eval_operand32(1, &breakpoint);
537 
}
538 720 markom 
INSTRUCTION (lf_madd_s) {
539 1350 nogj 
  SET_PARAM0((float)PARAM0 + (float)PARAM1 * (float)PARAM2);
540 720 markom 
}
541 
INSTRUCTION (lf_mul_s) {
542 1350 nogj 
  SET_PARAM0((float)PARAM1 * (float)PARAM2);
543 720 markom 
}
544 
INSTRUCTION (lf_rem_s) {
545 1342 nogj 
  float temp = (float)PARAM1 / (float)PARAM2;
546 1350 nogj 
  SET_PARAM0(temp - (uint32_t)temp);
547 720 markom 
}
548 
INSTRUCTION (lf_sfeq_s) {
549 1513 nogj 
  if((float)PARAM0 == (float)PARAM1)
550 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
551 
  else
552 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
553 720 markom 
}
554 
INSTRUCTION (lf_sfge_s) {
555 1513 nogj 
  if((float)PARAM0 >= (float)PARAM1)
556 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
557 
  else
558 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
559 720 markom 
}
560 
INSTRUCTION (lf_sfgt_s) {
561 1513 nogj 
  if((float)PARAM0 > (float)PARAM1)
562 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
563 
  else
564 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
565 720 markom 
}
566 
INSTRUCTION (lf_sfle_s) {
567 1513 nogj 
  if((float)PARAM0 <= (float)PARAM1)
568 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
569 
  else
570 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
571 720 markom 
}
572 
INSTRUCTION (lf_sflt_s) {
573 1513 nogj 
  if((float)PARAM0 < (float)PARAM1)
574 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
575 
  else
576 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
577 720 markom 
}
578 
INSTRUCTION (lf_sfne_s) {
579 1513 nogj 
  if((float)PARAM0 != (float)PARAM1)
580 1506 nogj 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
581 
  else
582 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
583 720 markom 
}
584 
INSTRUCTION (lf_sub_s) {
585 1350 nogj 
  SET_PARAM0((float)PARAM1 - (float)PARAM2);
586 720 markom 
}
587 
 
588 
/******* Custom instructions *******/
589 706 markom 
INSTRUCTION (l_cust1) {
590 713 markom 
  /*int destr = current->insn >> 21;
591 
    int src1r = current->insn >> 15;
592 
    int src2r = current->insn >> 9;*/
593 706 markom 
}
594 
INSTRUCTION (l_cust2) {
595 
}
596 
INSTRUCTION (l_cust3) {
597 
}
598 
INSTRUCTION (l_cust4) {
599 
}

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