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/* 16450.c -- Simulation of 8250/16450 serial UART
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
/* This is functional simulation of 8250/16450 UARTs. Since we RX/TX data
   via file streams, we can't simulate modem control lines coming from the
   DCE and similar details of communication with the DCE.
 
   This simulated UART device is intended for basic UART device driver
   verification. From device driver perspective this device looks like a
   regular UART but never reports any modem control lines changes (the
   only DCE responses are incoming characters from the file stream).
*/
 
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
 
#include "config.h"
 
#ifdef HAVE_INTTYPES_H
#include <inttypes.h>
#endif
 
#include "port.h"
#include "arch.h"
#include "abstract.h"
#include "16450.h"
#include "sim-config.h"
#include "pic.h"
#include "vapi.h"
#include "sched.h"
#include "channel.h"
#include "debug.h"
 
DEFAULT_DEBUG_CHANNEL(uart);
 
#define MIN(a,b) ((a) < (b) ? (a) : (b))
 
void uart_recv_break(void *dat);
void uart_recv_char(void *dat);
void uart_check_vapi(void *dat);
void uart_check_char(void *dat);
static void uart_sched_recv_check(struct dev_16450 *uart);
static void uart_vapi_cmd(void *dat);
static void uart_clear_int(struct dev_16450 *uart, int intr);
void uart_tx_send(void *dat);
 
/* Number of clock cycles (one clock cycle is when UART_CLOCK_DIVIDER simulator
 * cycles have elapsed) before a single character is transmitted or received. */
static unsigned long char_clks(int dll, int dlh, int lcr)
{
  unsigned int bauds_per_char = 2;
  unsigned long char_clks = ((dlh << 8) + dll);
 
  if (lcr & UART_LCR_PARITY)
    bauds_per_char += 2;
 
  /* stop bits 1 or two */
  if (lcr & UART_LCR_STOP)
    bauds_per_char += 4;
  else
    if ((lcr & 0x3) != 0)
      bauds_per_char += 2;
    else
      bauds_per_char += 3;
 
  bauds_per_char += 10 + ((lcr & 0x3) << 1);
 
  return (char_clks * bauds_per_char) >> 1;
}
 
/*---------------------------------------------------[ Interrupt handling ]---*/
/* Signals the specified interrupt.  If a higher priority interrupt is already
 * pending, do nothing */
static void uart_int_msi(void *dat)
{
  struct dev_16450 *uart = dat;
 
  uart->istat.ints |= 1 << UART_IIR_MSI;
 
  if(!(uart->regs.ier & UART_IER_MSI))
    return;
 
  if((uart->regs.iir & UART_IIR_NO_INT) || (uart->regs.iir == UART_IIR_MSI)) {
    TRACE("Raiseing modem status interrupt\n");
 
    if((uart->regs.iir != UART_IIR_MSI) && (uart->regs.iir != UART_IIR_NO_INT)) {
      uart_clear_int(uart, uart->regs.iir);
      uart->regs.iir = UART_IIR_MSI;
    } else {
      uart->regs.iir = UART_IIR_MSI;
      SCHED_ADD(uart_int_msi, dat, UART_CLOCK_DIVIDER);
      report_interrupt(uart->irq);
    }
  }
}
 
static void uart_int_thri(void *dat)
{
  struct dev_16450 *uart = dat;
 
  uart->istat.ints |= 1 << UART_IIR_THRI;
 
  if(!(uart->regs.ier & UART_IER_THRI))
    return;
 
  if((uart->regs.iir & UART_IIR_NO_INT) || (uart->regs.iir == UART_IIR_MSI) ||
     (uart->regs.iir == UART_IIR_THRI)) {
    TRACE("Raiseing transmitter holding register interrupt\n");
 
    if((uart->regs.iir != UART_IIR_THRI) && (uart->regs.iir != UART_IIR_NO_INT)) {
      uart_clear_int(uart, uart->regs.iir);
      uart->regs.iir = UART_IIR_THRI;
    } else {
      uart->regs.iir = UART_IIR_THRI;
      SCHED_ADD(uart_int_thri, dat, UART_CLOCK_DIVIDER);
      report_interrupt(uart->irq);
    }
  }
}
 
static void uart_int_cti(void *dat)
{
  struct dev_16450 *uart = dat;
 
  uart->istat.ints |= 1 << UART_IIR_CTI;
 
  if(!(uart->regs.ier & UART_IER_RDI))
    return;
 
  if((uart->regs.iir != UART_IIR_RLSI) && (uart->regs.iir != UART_IIR_RDI)) {
    TRACE("Raiseing character timeout interrupt\n");
 
    if((uart->regs.iir != UART_IIR_CTI) && (uart->regs.iir != UART_IIR_NO_INT)) {
      uart_clear_int(uart, uart->regs.iir);
      uart->regs.iir = UART_IIR_CTI;
    } else {
      uart->regs.iir = UART_IIR_CTI;
      SCHED_ADD(uart_int_cti, dat, UART_CLOCK_DIVIDER);
      report_interrupt(uart->irq);
    }
  }
}
 
static void uart_int_rdi(void *dat)
{
  struct dev_16450 *uart = dat;
 
  uart->istat.ints |= 1 << UART_IIR_RDI;
 
  if(!(uart->regs.ier & UART_IER_RDI))
    return;
 
  if(uart->regs.iir != UART_IIR_RLSI) {
    TRACE("Raiseing receiver data interrupt\n");
 
    if((uart->regs.iir != UART_IIR_RDI) && (uart->regs.iir != UART_IIR_NO_INT)) {
      uart_clear_int(uart, uart->regs.iir);
      uart->regs.iir = UART_IIR_RDI;
    } else {
      uart->regs.iir = UART_IIR_RDI;
      SCHED_ADD(uart_int_rdi, dat, UART_CLOCK_DIVIDER);
      report_interrupt(uart->irq);
    }
  }
}
 
static void uart_int_rlsi(void *dat)
{
  struct dev_16450 *uart = dat;
 
  uart->istat.ints |= 1 << UART_IIR_RLSI;
 
  if(!(uart->regs.ier & UART_IER_RLSI))
    return;
 
  TRACE("Raiseing receiver line status interrupt\n");
 
  /* Highest priority interrupt */
  if((uart->regs.iir != UART_IIR_RLSI) && (uart->regs.iir != UART_IIR_NO_INT)) {
    uart_clear_int(uart, uart->regs.iir);
    uart->regs.iir = UART_IIR_RLSI;
  } else {
    uart->regs.iir = UART_IIR_RLSI;
    SCHED_ADD(uart_int_rlsi, dat, UART_CLOCK_DIVIDER);
    report_interrupt(uart->irq);
  }
}
 
/* Checks to see if an RLSI interrupt is due and schedules one if need be */
static void uart_check_rlsi(void *dat)
{
  struct dev_16450 *uart = dat;
 
  if(uart->regs.lsr & (UART_LSR_OVRRUN | UART_LSR_PARITY | UART_LSR_FRAME |
                       UART_LSR_BREAK))
    uart_int_rlsi(uart);
}
 
/* Checks to see if an RDI interrupt is due and schedules one if need be */
static void uart_check_rdi(void *dat)
{
  struct dev_16450 *uart = dat;
 
  if(uart->istat.rxbuf_full >= UART_FIFO_TRIGGER(uart->regs.fcr >> 6)) {
    TRACE("FIFO trigger level reached %i\n",
          UART_FIFO_TRIGGER(uart->regs.fcr >> 6));
    uart_int_rdi(uart);
  }
}
 
/* Raises the next highest priority interrupt */
static void uart_next_int(void *dat)
{
  struct dev_16450 *uart = dat;
 
  /* Interrupt detection in proper priority order. */
  if((uart->istat.ints & (1 << UART_IIR_RLSI)) &&
     (uart->regs.ier & UART_IER_RLSI))
    uart_int_rlsi(uart);
  else if((uart->istat.ints & (1 << UART_IIR_RDI)) &&
          (uart->regs.ier & UART_IER_RDI))
    uart_int_rdi(uart);
  else if((uart->istat.ints & (1 << UART_IIR_CTI)) &&
          (uart->regs.ier & UART_IER_RDI))
    uart_int_cti(uart);
  else if((uart->istat.ints & (1 << UART_IIR_THRI)) &&
          (uart->regs.ier & UART_IER_THRI))
    uart_int_thri(uart);
  else if((uart->istat.ints & (1 << UART_IIR_MSI)) &&
          (uart->regs.ier & UART_IER_MSI))
    uart_int_msi(uart);
  else
    uart->regs.iir = UART_IIR_NO_INT;
}
 
/* Clears potentially pending interrupts */
static void uart_clear_int(struct dev_16450 *uart, int intr)
{
  uart->istat.ints &= ~(1 << intr);
 
  TRACE("Interrupt pending was %x\n", uart->regs.iir);
 
  /* Short-circuit most likely case */
  if(uart->regs.iir == UART_IIR_NO_INT)
    return;
 
  if(intr != uart->regs.iir)
    return;
 
  TRACE("Clearing interrupt 0x%x\n", intr);
 
  uart->regs.iir = UART_IIR_NO_INT;
 
  switch(intr) {
  case UART_IIR_RLSI:
    SCHED_FIND_REMOVE(uart_int_rlsi, uart);
    break;
  case UART_IIR_RDI:
    SCHED_FIND_REMOVE(uart_int_rdi, uart);
    break;
  case UART_IIR_CTI:
    SCHED_FIND_REMOVE(uart_int_cti, uart);
    break;
  case UART_IIR_THRI:
    SCHED_FIND_REMOVE(uart_int_thri, uart);
    break;
  case UART_IIR_MSI:
    SCHED_FIND_REMOVE(uart_int_msi, uart);
    break;
  }
 
  /* Schedule this job as there is no rush to send the next interrupt (the or.
   * code is probably still running with interrupts disabled and this function
   * is called from the uart_{read,write}_byte functions. */
  SCHED_ADD(uart_next_int, uart, 0);
}
 
/*----------------------------------------------------[ Loopback handling ]---*/
static void uart_loopback(struct dev_16450 *uart)
{
  if(!(uart->regs.mcr & UART_MCR_LOOP))
    return;
 
  if((uart->regs.mcr & UART_MCR_AUX2) != ((uart->regs.msr & UART_MSR_DCD) >> 4))
    uart->regs.msr |= UART_MSR_DDCD;
 
  if((uart->regs.mcr & UART_MCR_AUX1) < ((uart->regs.msr & UART_MSR_RI) >> 4))
    uart->regs.msr |= UART_MSR_TERI;
 
  if((uart->regs.mcr & UART_MCR_RTS) != ((uart->regs.msr & UART_MSR_CTS) >> 3))
    uart->regs.msr |= UART_MSR_DCTS;
 
  if((uart->regs.mcr & UART_MCR_DTR) != ((uart->regs.msr & UART_MSR_DSR) >> 5))
    uart->regs.msr |= UART_MSR_DDSR;
 
  uart->regs.msr &= ~(UART_MSR_DCD | UART_MSR_RI | UART_MSR_DSR | UART_MSR_CTS);
  uart->regs.msr |= ((uart->regs.mcr & UART_MCR_AUX2) << 4);
  uart->regs.msr |= ((uart->regs.mcr & UART_MCR_AUX1) << 4);
  uart->regs.msr |= ((uart->regs.mcr & UART_MCR_RTS) << 3);
  uart->regs.msr |= ((uart->regs.mcr & UART_MCR_DTR) << 5);
 
  if(uart->regs.msr & (UART_MSR_DCTS | UART_MSR_DDSR | UART_MSR_TERI |
                       UART_MSR_DDCD))
    uart_int_msi(uart);
}
 
/*----------------------------------------------------[ Transmitter logic ]---*/
/* Sends the data in the shift register to the outside world */
static void send_char (struct dev_16450 *uart, int bits_send)
{
  PRINTF ("%c", (char)uart->iregs.txser);
  TRACE("TX \'%c\' via UART at %"PRIxADDR"\n", (char)uart->iregs.txser,
        uart->baseaddr);
  if (uart->regs.mcr & UART_MCR_LOOP)
    uart->iregs.loopback = uart->iregs.txser;
  else {
    /* Send to either VAPI or to file */
    if (uart->vapi_id) {
      int par, pe, fe, nbits;
      int j, data;
      unsigned long packet = 0;
 
      nbits = MIN (bits_send, (uart->regs.lcr & UART_LCR_WLEN8) + 5);
      /* Encode a packet */
      packet = uart->iregs.txser & ((1 << nbits) - 1);
 
      /* Calculate parity */
      for (j = 0, par = 0; j < nbits; j++)
        par ^= (packet >> j) & 1;
 
      if (uart->regs.lcr & UART_LCR_PARITY) {
        if (uart->regs.lcr & UART_LCR_SPAR) {
          packet |= 1 << nbits;
        } else {
          if (uart->regs.lcr & UART_LCR_EPAR)
            packet |= par << nbits;
          else
            packet |= (par ^ 1) << nbits;
        }
        nbits++;
      }
      packet |= 1 << (nbits++);
      if (uart->regs.lcr & UART_LCR_STOP)
        packet |= 1 << (nbits++);
 
      /* Decode a packet */
      nbits = (uart->vapi.lcr & UART_LCR_WLEN8) + 5;
      data = packet & ((1 << nbits) - 1);
 
      /* Calculate parity, including parity bit */
      for (j = 0, par = 0; j < nbits + 1; j++)
        par ^= (packet >> j) & 1;
 
      if (uart->vapi.lcr & UART_LCR_PARITY) {
        if (uart->vapi.lcr & UART_LCR_SPAR) {
          pe = !((packet >> nbits) & 1);
        } else {
          if (uart->vapi.lcr & UART_LCR_EPAR)
            pe = par != 0;
          else
            pe = par != 1;
        }
        nbits++;
      } else
        pe = 0;
 
      fe = ((packet >> (nbits++)) & 1) ^ 1;
      if (uart->vapi.lcr & UART_LCR_STOP)
        fe |= ((packet >> (nbits++)) & 1) ^ 1;
 
      TRACE ("lcr vapi %02x, uart %02x\n", uart->vapi.lcr, uart->regs.lcr);
      data |= (uart->vapi.lcr << 8) | (pe << 16) | (fe << 17) | (uart->vapi.lcr << 8);
      TRACE ("vapi_send (%08lx, %08x)\n", uart->vapi_id, data);
      vapi_send (uart->vapi_id, data);
    } else {
      char buffer[1] = { uart->iregs.txser & 0xFF };
      channel_write(uart->channel, buffer, 1);
    }
  }
}
 
/* Called when all the bits have been shifted out of the shift register */
void uart_char_clock(void *dat)
{
  struct dev_16450 *uart = dat;
 
  TRACE("Sending data in shift reg: 0x%02"PRIx8"\n", uart->iregs.txser);
  /* We've sent all bits */
  send_char(uart, (uart->regs.lcr & UART_LCR_WLEN8) + 5);
 
  if(!uart->istat.txbuf_full)
    uart->regs.lsr |= UART_LSR_TXSERE;
  else
    uart_tx_send(uart);
}
 
/* Called when a break has been shifted out of the shift register */
void uart_send_break(void *dat)
{
  struct dev_16450 *uart = dat;
 
  TRACE("Sending break\n");
#if 0
  /* Send broken frame */
  int nbits_sent = ((uart->regs.lcr & UART_LCR_WLEN8) + 5) * (uart->istat.txser_clks - 1) / uart->char_clks;
  send_char(i, nbits_sent);
#endif
  /* Send one break signal */
  vapi_send (uart->vapi_id, UART_LCR_SBC << 8);
 
  /* Send the next char (if there is one) */
  if(!uart->istat.txbuf_full)
    uart->regs.lsr |= UART_LSR_TXSERE;
  else
    uart_tx_send(uart);
}
 
/* Scheduled whenever the TX buffer has characters in it and we aren't sending
 * a character. */
void uart_tx_send(void *dat)
{
  struct dev_16450 *uart = dat;
 
  uart->iregs.txser = uart->regs.txbuf[uart->istat.txbuf_tail];
  uart->istat.txbuf_tail = (uart->istat.txbuf_tail + 1) % uart->fifo_len;
  uart->istat.txbuf_full--;
  uart->regs.lsr &= ~UART_LSR_TXSERE;
 
  TRACE("Moveing head of TX fifo (fill: %i) to shift reg 0x%02"PRIx8"\n",
        uart->istat.txbuf_full, uart->iregs.txser);
 
  /* Schedules a char_clock to run in the correct amount of time */
  if(!(uart->regs.lcr & UART_LCR_SBC)) {
    SCHED_ADD(uart_char_clock, uart, uart->char_clks * UART_CLOCK_DIVIDER);
  } else {
    TRACE("Sending break not char\n");
    SCHED_ADD(uart_send_break, uart, 0);
  }
 
  /* When UART is in either character mode, i.e. 16450 emulation mode, or FIFO
   * mode, the THRE interrupt is raised when THR transitions from full to empty.
   */
  if (!uart->istat.txbuf_full) {
    uart->regs.lsr |= UART_LSR_TXBUFE;
    uart_int_thri(uart);
  }
}
 
/*-------------------------------------------------------[ Receiver logic ]---*/
/* Adds a character to the RX FIFO */
static void uart_add_char (struct dev_16450 *uart, int ch)
{
  uart->regs.lsr |= UART_LSR_RDRDY;
  uart_clear_int(uart, UART_IIR_CTI);
  SCHED_FIND_REMOVE(uart_int_cti, uart);
  SCHED_ADD(uart_int_cti, uart,
            uart->char_clks * UART_CHAR_TIMEOUT * UART_CLOCK_DIVIDER);
 
  if (uart->istat.rxbuf_full + 1 > uart->fifo_len) {
    uart->regs.lsr |= UART_LSR_OVRRUN | UART_LSR_RXERR;
    uart_int_rlsi(uart);
  } else {
    TRACE("add %02x\n", ch);
    uart->regs.rxbuf[uart->istat.rxbuf_head] = ch;
    uart->istat.rxbuf_head = (uart->istat.rxbuf_head + 1) % uart->fifo_len;
    if(!uart->istat.rxbuf_full++) {
      uart->regs.lsr |= ch >> 8;
      uart_check_rlsi(uart);
    }
  }
  uart_check_rdi(uart);
}
 
/* Called when a break sequence is about to start.  It stops receiveing
 * characters and schedules the uart_recv_break to send the break */
void uart_recv_break_start(void *dat)
{
  struct dev_16450 *uart = dat;
 
  uart->istat.receiveing = 0;
  uart->istat.recv_break = 1;
 
  SCHED_FIND_REMOVE(uart_recv_char, uart);
 
  if(uart->vapi_id && (uart->vapi_buf_head_ptr != uart->vapi_buf_tail_ptr))
    uart_vapi_cmd(uart);
 
  SCHED_ADD(uart_recv_break, uart,
            UART_BREAK_COUNT * uart->vapi.char_clks * UART_CLOCK_DIVIDER);
}
 
/* Stops sending breaks and starts receiveing characters */
void uart_recv_break_stop(void *dat)
{
  struct dev_16450 *uart = dat;
 
  uart->istat.recv_break = 0;
  SCHED_FIND_REMOVE(uart_recv_break, dat);
}
 
/* Receives a break */
void uart_recv_break(void *dat)
{
  struct dev_16450 *uart = dat;
  unsigned lsr = UART_LSR_BREAK | UART_LSR_RXERR | UART_LSR_RDRDY;
 
  uart_add_char(uart, lsr << 8);
}
 
/* Moves a character from the serial register to the RX FIFO */
void uart_recv_char(void *dat)
{
  struct dev_16450 *uart = dat;
  uint16_t char_to_add;
 
  /* Set unused character bits to zero and allow lsr register in fifo */
  char_to_add = uart->iregs.rxser & (((1 << ((uart->regs.lcr & 3) + 5)) - 1) | 0xff00);
 
  TRACE("Receiving 0x%02"PRIx16"'%c' via UART at %"PRIxADDR"\n",
              char_to_add, (char)char_to_add, uart->baseaddr);
  PRINTF ("%c", (char)char_to_add);
 
  if (uart->regs.mcr & UART_MCR_LOOP) {
    uart->iregs.rxser = uart->iregs.loopback;
    uart->istat.receiveing = 1;
    SCHED_ADD(uart_recv_char, uart, uart->char_clks * UART_CLOCK_DIVIDER);
  } else {
    uart->istat.receiveing = 0;
    uart_sched_recv_check(uart);
    if(uart->vapi_id && (uart->vapi_buf_head_ptr != uart->vapi_buf_tail_ptr))
      SCHED_ADD(uart_vapi_cmd, uart, 0);
  }
 
  uart_add_char(uart, char_to_add);
}
 
/* Checks if there is a character waiting to be received */
void uart_check_char(void *dat)
{
  struct dev_16450 *uart = dat;
  uint8_t buffer;
  int retval;
 
  /* Check if there is something waiting, and put it into rxser */
  retval = channel_read(uart->channel, (char *)&buffer, 1);
  if(retval > 0) {
    TRACE("Shifting 0x%02"PRIx8" (`%c') into shift reg\n", buffer, buffer);
    uart->iregs.rxser = buffer;
    uart->istat.receiveing = 1;
    SCHED_ADD(uart_recv_char, uart, uart->char_clks * UART_CLOCK_DIVIDER);
    return;
  }
 
  if(!retval) {
    SCHED_ADD(uart_check_char, uart, UART_FGETC_SLOWDOWN * UART_CLOCK_DIVIDER);
    return;
  }
 
  if(retval < 0)
    perror(uart->channel_str);
}
 
static void uart_sched_recv_check(struct dev_16450 *uart)
{
  if(!uart->vapi_id)
    SCHED_ADD(uart_check_char, uart, UART_FGETC_SLOWDOWN * UART_CLOCK_DIVIDER);
}
 
/*----------------------------------------------------[ UART I/O handling ]---*/
/* Set a specific UART register with value. */
void uart_write_byte(oraddr_t addr, uint8_t value, void *dat)
{
  struct dev_16450 *uart = dat;
 
  if (uart->regs.lcr & UART_LCR_DLAB) {
    switch (addr) {
      case UART_DLL:
        uart->regs.dll = value;
        uart->char_clks = char_clks(uart->regs.dll, uart->regs.dlh, uart->regs.lcr);
        TRACE("\tSetting char_clks to %li (%02x, %02x, %02x)\n", uart->char_clks,
              uart->regs.dll, uart->regs.dlh, uart->regs.lcr);
        return;
      case UART_DLH:
        TRACE("Setting dlh with %"PRIx8"\n", value);
        uart->regs.dlh = value;
        return;
    }
  }
 
  switch (addr) {
    case UART_TXBUF:
      TRACE("Adding %"PRIx8" to TX FIFO (fill %i)\n", value,
            uart->istat.txbuf_full);
      uart->regs.lsr &= ~UART_LSR_TXBUFE;
      if (uart->istat.txbuf_full < uart->fifo_len) {
        uart->regs.txbuf[uart->istat.txbuf_head] = value;
        uart->istat.txbuf_head = (uart->istat.txbuf_head + 1) % uart->fifo_len;
        if(!uart->istat.txbuf_full++ && (uart->regs.lsr & UART_LSR_TXSERE))
          SCHED_ADD(uart_tx_send, uart, 0);
      } else
        uart->regs.txbuf[uart->istat.txbuf_head] = value;
 
      uart_clear_int(uart, UART_IIR_THRI);
      break;
    case UART_FCR:
      TRACE("Setting FCR reg with %"PRIx8"\n", value);
      uart->regs.fcr = value & UART_VALID_FCR;
      if ((uart->fifo_len == 1 && (value & UART_FCR_FIE))
       || (uart->fifo_len != 1 && !(value & UART_FCR_FIE)))
        value |= UART_FCR_RRXFI | UART_FCR_RTXFI;
      uart->fifo_len = (value & UART_FCR_FIE) ? 16 : 1;
      if (value & UART_FCR_RTXFI) {
        uart->istat.txbuf_head = uart->istat.txbuf_tail = 0;
        uart->istat.txbuf_full = 0;
        uart->regs.lsr |= UART_LSR_TXBUFE;
 
        /* For FIFO-mode only, THRE interrupt is set when THR and FIFO are empty
         */
        if(uart->fifo_len == 16)
          SCHED_ADD(uart_int_thri, uart, 0);
 
        SCHED_FIND_REMOVE(uart_tx_send, uart);
      }
      if (value & UART_FCR_RRXFI) {
        uart->istat.rxbuf_head = uart->istat.rxbuf_tail = 0;
        uart->istat.rxbuf_full = 0;
        uart->regs.lsr &= ~UART_LSR_RDRDY;
        uart_clear_int(uart, UART_IIR_RDI);
        uart_clear_int(uart, UART_IIR_CTI);
      }
      break;
    case UART_IER:
      uart->regs.ier = value & UART_VALID_IER;
      TRACE("Enabling 0x%02x interrupts with 0x%x interrupts pending\n",
            value, uart->istat.ints);
      SCHED_ADD(uart_next_int, uart, 0);
      break;
    case UART_LCR:
      TRACE("Setting LCR reg with %"PRIx8"\n", value);
      if((uart->regs.lcr & UART_LCR_SBC) != (value & UART_LCR_SBC)) {
        if((value & UART_LCR_SBC) && !(uart->regs.lsr & UART_LSR_TXSERE)) {
          /* Schedule a job to send the break char */
          SCHED_FIND_REMOVE(uart_char_clock, uart);
          SCHED_ADD(uart_send_break, uart, 0);
        }
        if(!(value & UART_LCR_SBC) && !(uart->regs.lsr & UART_LSR_TXSERE)) {
          /* Schedule a job to start sending characters */
          SCHED_ADD(uart_tx_send, uart, 0);
          /* Remove the uart_send_break job just in case it has not run yet */
          SCHED_FIND_REMOVE(uart_char_clock, uart);
        }
      }
      uart->regs.lcr = value & UART_VALID_LCR;
      uart->char_clks = char_clks(uart->regs.dll, uart->regs.dlh, uart->regs.lcr);
      break;
    case UART_MCR:
      TRACE("Setting MCR reg with %"PRIx8"\n", value);
      uart->regs.mcr = value & UART_VALID_MCR;
      uart_loopback(uart);
      break;
    case UART_SCR:
      TRACE("Setting SCR reg with %"PRIx8"\n", value);
      uart->regs.scr = value;
      break;
    default:
      TRACE("write out of range (addr %"PRIxADDR")\n", addr);
  }
}
 
/* Read a specific UART register. */
uint8_t uart_read_byte(oraddr_t addr, void *dat)
{
  struct dev_16450 *uart = dat;
  uint8_t value = 0;
 
  if (uart->regs.lcr & UART_LCR_DLAB) {
    switch (addr) {
      case UART_DLL:
        value = uart->regs.dll;
        TRACE("reading DLL = %"PRIx8"\n", value);
        return value;
      case UART_DLH:
        value = uart->regs.dlh;
        TRACE("reading DLH = %"PRIx8"\n", value);
        return value;
    }
  }
 
  switch (addr) {
    case UART_RXBUF:
      { /* Print out FIFO for debugging */
        int i;
        TRACE("(%i/%i, %i, %i:", uart->istat.rxbuf_full, uart->fifo_len,
              uart->istat.rxbuf_head, uart->istat.rxbuf_tail);
        for (i = 0; i < uart->istat.rxbuf_full; i++)
          TRACE("%02x ",
                uart->regs.rxbuf[(uart->istat.rxbuf_tail + i) % uart->fifo_len]);
        TRACE(")\n");
      }
      if (uart->istat.rxbuf_full) {
        value = uart->regs.rxbuf[uart->istat.rxbuf_tail];
        uart->istat.rxbuf_tail = (uart->istat.rxbuf_tail + 1) % uart->fifo_len;
        uart->istat.rxbuf_full--;
        TRACE("Reading %"PRIx8" out of RX FIFO\n", value);
      } else
        TRACE("Trying to read out of RX FIFO but it's empty!\n");
 
      uart_clear_int(uart, UART_IIR_RDI);
      uart_clear_int(uart, UART_IIR_CTI);
      SCHED_FIND_REMOVE(uart_int_cti, uart);
 
      if(uart->istat.rxbuf_full) {
        uart->regs.lsr |= UART_LSR_RDRDY | uart->regs.rxbuf[uart->istat.rxbuf_tail] >> 8;
        SCHED_ADD(uart_int_cti, uart,
                  uart->char_clks * UART_CHAR_TIMEOUT * UART_CLOCK_DIVIDER);
        /* Since we're not allowed to raise interrupts from read/write functions
         * schedule them to run just after we have executed this read
         * instruction. */
        SCHED_ADD(uart_check_rlsi, uart, 0);
        SCHED_ADD(uart_check_rdi, uart, 0);
      } else {
        uart->regs.lsr &= ~UART_LSR_RDRDY;
      }
      break;
    case UART_IER:
      value = uart->regs.ier & UART_VALID_IER;
      TRACE("reading IER = %"PRIx8"\n", value);
      break;
    case UART_IIR:
      value = (uart->regs.iir & UART_VALID_IIR) | 0xc0;
      /* Only clear the thri interrupt if it is the one we are repporting */
      if(uart->regs.iir == UART_IIR_THRI)
        uart_clear_int(uart, UART_IIR_THRI);
      TRACE("reading IIR = %"PRIx8"\n", value);
      break;
    case UART_LCR:
      value = uart->regs.lcr & UART_VALID_LCR;
      TRACE("reading LCR = %"PRIx8"\n", value);
      break;
    case UART_MCR:
      value = 0;
      TRACE("reading MCR = %"PRIx8"\n", value);
      break;
    case UART_LSR:
      value = uart->regs.lsr & UART_VALID_LSR;
      uart->regs.lsr &=
        ~(UART_LSR_OVRRUN | UART_LSR_BREAK | UART_LSR_PARITY
         | UART_LSR_FRAME | UART_LSR_RXERR);
      /* Clear potentially pending RLSI interrupt */
      uart_clear_int(uart, UART_IIR_RLSI);
      TRACE("reading LSR = %"PRIx8"\n", value);
      break;
    case UART_MSR:
      value = uart->regs.msr & UART_VALID_MSR;
      uart->regs.msr = 0;
      uart_clear_int(uart, UART_IIR_MSI);
      uart_loopback(uart);
      TRACE("reading MSR = %"PRIx8"\n", value);
      break;
    case UART_SCR:
      value = uart->regs.scr;
      TRACE("reading SCR = %"PRIx8"\n", value);
      break;
    default:
      TRACE("read out of range (addr %"PRIxADDR")\n", addr);
  }
  return value;
}
 
/*--------------------------------------------------------[ VAPI handling ]---*/
/* Decodes the read vapi command */
static void uart_vapi_cmd(void *dat)
{
  struct dev_16450 *uart = dat;
  int received = 0;
 
  while (!received) {
    if (uart->vapi_buf_head_ptr != uart->vapi_buf_tail_ptr) {
      unsigned long data = uart->vapi_buf[uart->vapi_buf_tail_ptr];
      TRACE("\tHandling: %08lx (%i,%i)\n", data, uart->vapi_buf_head_ptr,
            uart->vapi_buf_tail_ptr);
      uart->vapi_buf_tail_ptr = (uart->vapi_buf_tail_ptr + 1) % UART_VAPI_BUF_LEN;
      switch (data >> 24) {
      case 0x00:
        uart->vapi.lcr = (data >> 8) & 0xff;
        /* Put data into rx fifo */
        uart->iregs.rxser = data & 0xff;
        uart->vapi.char_clks = char_clks (uart->vapi.dll, uart->vapi.dlh, uart->vapi.lcr);
        if((uart->vapi.lcr & ~UART_LCR_SBC) != (uart->regs.lcr & ~UART_LCR_SBC)
            || uart->vapi.char_clks != uart->char_clks
            || uart->vapi.skew < -MAX_SKEW || uart->vapi.skew > MAX_SKEW) {
          if((uart->vapi.lcr & ~UART_LCR_SBC) != (uart->regs.lcr & ~UART_LCR_SBC))
            WARN("unmatched VAPI (%02"PRIx8") and uart (%02"PRIx8") modes.\n",
                 uart->vapi.lcr & ~UART_LCR_SBC, uart->regs.lcr & ~UART_LCR_SBC);
          if(uart->vapi.char_clks != uart->char_clks) {
            WARN("unmatched VAPI (%li) and uart (%li) char clocks.\n",
                 uart->vapi.char_clks, uart->char_clks);
            WARN("VAPI: lcr: %02"PRIx8", dll: %02"PRIx8", dlh: %02"PRIx8"\n",
                 uart->vapi.lcr, uart->vapi.dll, uart->vapi.dlh);
            WARN("UART: lcr: %02"PRIx8", dll: %02"PRIx8", dlh: %02"PRIx8"\n",
                 uart->regs.lcr, uart->regs.dll, uart->vapi.dlh);
          }
          if(uart->vapi.skew < -MAX_SKEW || uart->vapi.skew > MAX_SKEW)
            WARN("VAPI skew is beyond max: %i\n", uart->vapi.skew);
          /* Set error bits */
          uart->iregs.rxser |= (UART_LSR_FRAME | UART_LSR_RXERR) << 8;
          if(uart->regs.lcr & UART_LCR_PARITY)
            uart->iregs.rxser |= UART_LSR_PARITY << 8;
        }
        if(!uart->istat.recv_break) {
          uart->istat.receiveing = 1;
          SCHED_ADD(uart_recv_char, uart, uart->char_clks * UART_CLOCK_DIVIDER);
        }
        received = 1;
        break;
      case 0x01:
        uart->vapi.dll = (data >> 0) & 0xff;
        uart->vapi.dlh = (data >> 8) & 0xff;
        break;
      case 0x02:
        uart->vapi.lcr = (data >> 8) & 0xff;
        break;
      case 0x03:
        uart->vapi.skew = (signed short)(data & 0xffff);
        break;
      case 0x04:
        if((data >> 16) & 1) {
          /* If data & 0xffff is 0 then set the break imediatly and handle the
           * following commands as appropriate */
          if(!(data & 0xffff))
            uart_recv_break_start(uart);
          else
            /* Schedule a job to start sending breaks */
            SCHED_ADD(uart_recv_break_start, uart,
                      (data & 0xffff) * UART_CLOCK_DIVIDER);
        } else {
          /* If data & 0xffff is 0 then release the break imediatly and handle
           * the following commands as appropriate */
          if(!(data & 0xffff))
            uart_recv_break_stop(uart);
          else
            /* Schedule a job to stop sending breaks */
            SCHED_ADD(uart_recv_break_stop, uart,
                      (data & 0xffff) * UART_CLOCK_DIVIDER);
        }
        break;
      default:
        WARN("WARNING: Invalid vapi command %02lx\n", data >> 24);
        break;
      }
    } else break;
  }
}
 
/* Function that handles incoming VAPI data.  */
void uart_vapi_read (unsigned long id, unsigned long data, void *dat)
{
  struct dev_16450 *uart = dat;
  TRACE("UART: id %08lx, data %08lx\n", id, data);
  uart->vapi_buf[uart->vapi_buf_head_ptr] = data;
  uart->vapi_buf_head_ptr = (uart->vapi_buf_head_ptr + 1) % UART_VAPI_BUF_LEN;
  if (uart->vapi_buf_tail_ptr == uart->vapi_buf_head_ptr) {
    fprintf (stderr, "FATAL: uart VAPI buffer to small.\n");
    exit (1);
  }
  if(!uart->istat.receiveing)
    uart_vapi_cmd(uart);
}
 
/*--------------------------------------------------------[ Sim callbacks ]---*/
/* Reset.  It initializes all registers of all UART devices to zero values,
 * (re)opens all RX/TX file streams and places devices in memory address
 * space.  */
void uart_reset(void *dat)
{
  struct dev_16450 *uart = dat;
 
  if(uart->vapi_id) {
    vapi_install_handler(uart->vapi_id, uart_vapi_read, dat);
  } else if (uart->channel_str && uart->channel_str[0]) { /* Try to create stream. */
    if(uart->channel)
      channel_close(uart->channel);
    else
      uart->channel = channel_init(uart->channel_str);
    if(channel_open(uart->channel) < 0) {
      WARN ("WARNING: problem with channel \"%s\" detected.\n", uart->channel_str);
    } else if (config.sim.verbose)
      PRINTF("UART at 0x%"PRIxADDR"\n", uart->baseaddr);
  } else {
    WARN ("WARNING: UART at %"PRIxADDR" has no vapi nor channel specified\n",
          uart->baseaddr);
  }
 
  if (uart->uart16550)
    uart->fifo_len = 16;
  else
    uart->fifo_len = 1;
 
  uart->istat.rxbuf_head = uart->istat.rxbuf_tail = 0;
  uart->istat.txbuf_head = uart->istat.txbuf_tail = 0;
 
  uart->istat.txbuf_full = uart->istat.rxbuf_full = 0;
 
  uart->char_clks = 0;
 
  uart->iregs.txser = 0;
  uart->iregs.rxser = 0;
  uart->iregs.loopback = 0;
  uart->istat.receiveing = 0;
  uart->istat.recv_break = 0;
  uart->istat.ints = 0;
 
  memset(uart->regs.txbuf, 0, sizeof(uart->regs.txbuf));
  memset(uart->regs.rxbuf, 0, sizeof(uart->regs.rxbuf));
 
  uart->regs.dll = 0;
  uart->regs.dlh = 0;
  uart->regs.ier = 0;
  uart->regs.iir = UART_IIR_NO_INT;
  uart->regs.fcr = 0;
  uart->regs.lcr = UART_LCR_RESET;
  uart->regs.mcr = 0;
  uart->regs.lsr = UART_LSR_TXBUFE | UART_LSR_TXSERE;
  uart->regs.msr = 0;
  uart->regs.scr = 0;
 
  uart->vapi.skew = 0;
  uart->vapi.lcr = 0;
  uart->vapi.dll = 0;
  uart->vapi.char_clks = 0;
 
  uart->vapi_buf_head_ptr = 0;
  uart->vapi_buf_tail_ptr = 0;
  memset(uart->vapi_buf, 0, sizeof(uart->vapi_buf));
 
  uart_sched_recv_check(uart);
}
 
/* Print register values on stdout. */
void uart_status(void *dat)
{
  struct dev_16450 *uart = dat;
  int i;
 
  PRINTF("\nUART visible registers at 0x%"PRIxADDR":\n", uart->baseaddr);
  PRINTF("RXBUF: ");
  for (i = uart->istat.rxbuf_head; i != uart->istat.rxbuf_tail; i = (i + 1) % uart->fifo_len)
    PRINTF (" %.2x", uart->regs.rxbuf[i]);
  PRINTF("TXBUF: ");
  for (i = uart->istat.txbuf_head; i != uart->istat.txbuf_tail; i = (i + 1) % uart->fifo_len)
    PRINTF (" %.2x", uart->regs.txbuf[i]);
  PRINTF("\n");
  PRINTF("DLL  : %.2x  DLH  : %.2x\n", uart->regs.dll, uart->regs.dlh);
  PRINTF("IER  : %.2x  IIR  : %.2x\n", uart->regs.ier, uart->regs.iir);
  PRINTF("LCR  : %.2x  MCR  : %.2x\n", uart->regs.lcr, uart->regs.mcr);
  PRINTF("LSR  : %.2x  MSR  : %.2x\n", uart->regs.lsr, uart->regs.msr);
  PRINTF("SCR  : %.2x\n", uart->regs.scr);
 
  PRINTF("\nInternal registers (sim debug):\n");
  PRINTF("RXSER: %.2"PRIx16"  TXSER: %.2"PRIx8"\n", uart->iregs.rxser,
         uart->iregs.txser);
 
  PRINTF("\nInternal status (sim debug):\n");
  PRINTF("char_clks: %ld\n", uart->char_clks);
  PRINTF("rxbuf_full: %d  txbuf_full: %d\n", uart->istat.rxbuf_full, uart->istat.txbuf_full);
  PRINTF("Using IRQ%i\n", uart->irq);
  if (uart->vapi_id)
    PRINTF ("Connected to vapi ID=%lx\n\n", uart->vapi_id);
  /* TODO: replace by a channel_status
  else
    PRINTF("RX fs: %p  TX fs: %p\n\n", uart->rxfs, uart->txfs);
  */
}
 
/*---------------------------------------------------[ UART configuration ]---*/
void uart_baseaddr(union param_val val, void *dat)
{
  struct dev_16450 *uart = dat;
  uart->baseaddr = val.addr_val;
}
 
void uart_jitter(union param_val val, void *dat)
{
  struct dev_16450 *uart = dat;
  uart->jitter = val.int_val;
}
 
void uart_irq(union param_val val, void *dat)
{
  struct dev_16450 *uart = dat;
  uart->irq = val.int_val;
}
 
void uart_16550(union param_val val, void *dat)
{
  struct dev_16450 *uart = dat;
  uart->uart16550 = val.int_val;
}
 
void uart_channel(union param_val val, void *dat)
{
  struct dev_16450 *uart = dat;
  if(!(uart->channel_str = strdup(val.str_val))) {
    fprintf(stderr, "Peripheral 16450: Run out of memory\n");
    exit(-1);
  }
}
 
void uart_newway(union param_val val, void *dat)
{
  CONFIG_ERROR(" txfile and rxfile and now obsolete.\n\tUse 'channel = \"file:rxfile,txfile\"' instead.");
  exit(1);
}
 
void uart_vapi_id(union param_val val, void *dat)
{
  struct dev_16450 *uart = dat;
  uart->vapi_id = val.int_val;
}
 
void uart_enabled(union param_val val, void *dat)
{
  struct dev_16450 *uart = dat;
  uart->enabled = val.int_val;
}
 
void *uart_sec_start(void)
{
  struct dev_16450 *new = malloc(sizeof(struct dev_16450));
 
  if(!new) {
    fprintf(stderr, "Peripheral 16450: Run out of memory\n");
    exit(-1);
  }
 
  new->enabled = 1;
  new->channel_str = NULL;
  new->channel = NULL;
  new->vapi_id = 0;
 
  return new;
}
 
void uart_sec_end(void *dat)
{
  struct dev_16450 *uart = dat;
  struct mem_ops ops;
 
  if(!uart->enabled) {
    free(dat);
    return;
  }
 
  memset(&ops, 0, sizeof(struct mem_ops));
 
  ops.readfunc8 = uart_read_byte;
  ops.writefunc8 = uart_write_byte;
  ops.read_dat8 = dat;
  ops.write_dat8 = dat;
 
  /* FIXME: What should these be? */
  ops.delayr = 2;
  ops.delayw = 2;
 
  reg_mem_area(uart->baseaddr, UART_ADDR_SPACE, 0, &ops);
 
  reg_sim_reset(uart_reset, dat);
  reg_sim_stat(uart_status, dat);
}
 
void reg_uart_sec(void)
{
  struct config_section *sec = reg_config_sec("uart", uart_sec_start,
                                              uart_sec_end);
 
  reg_config_param(sec, "baseaddr", paramt_addr, uart_baseaddr);
  reg_config_param(sec, "enabled", paramt_int, uart_enabled);
  reg_config_param(sec, "irq", paramt_int, uart_irq);
  reg_config_param(sec, "16550", paramt_int, uart_16550);
  reg_config_param(sec, "jitter", paramt_int, uart_jitter);
  reg_config_param(sec, "channel", paramt_str, uart_channel);
  reg_config_param(sec, "txfile", paramt_str, uart_newway);
  reg_config_param(sec, "rxfile", paramt_str, uart_newway);
  reg_config_param(sec, "vapi_id", paramt_int, uart_vapi_id);
}

Line No.	Rev	Author	Line
1	31	lampret	`/* 16450.c -- Simulation of 8250/16450 serial UART`
2			`Copyright (C) 1999 Damjan Lampret, lampret@opencores.org`
3
4			`This file is part of OpenRISC 1000 Architectural Simulator.`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License as published by`
8			`the Free Software Foundation; either version 2 of the License, or`
9			`(at your option) any later version.`
10
11			`This program is distributed in the hope that it will be useful,`
12			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`GNU General Public License for more details.`
15
16			`You should have received a copy of the GNU General Public License`
17			`along with this program; if not, write to the Free Software`
18			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */`
19
20			`/* This is functional simulation of 8250/16450 UARTs. Since we RX/TX data`
21			`via file streams, we can't simulate modem control lines coming from the`
22			`DCE and similar details of communication with the DCE.`
23
24			`This simulated UART device is intended for basic UART device driver`
25			`verification. From device driver perspective this device looks like a`
26	1549	nogj	`regular UART but never reports any modem control lines changes (the`
27	31	lampret	`only DCE responses are incoming characters from the file stream).`
28			`*/`
29
30			`#include <stdlib.h>`
31			`#include <stdio.h>`
32			`#include <string.h>`
33
34	1350	nogj	`#include "config.h"`
35
36			`#ifdef HAVE_INTTYPES_H`
37			`#include <inttypes.h>`
38			`#endif`
39
40			`#include "port.h"`
41			`#include "arch.h"`
42	235	erez	`#include "abstract.h"`
43	31	lampret	`#include "16450.h"`
44			`#include "sim-config.h"`
45	102	lampret	`#include "pic.h"`
46	336	markom	`#include "vapi.h"`
47	805	markom	`#include "sched.h"`
48	1073	rprescott	`#include "channel.h"`
49	1308	phoenix	`#include "debug.h"`
50	31	lampret
51	1392	nogj	`DEFAULT_DEBUG_CHANNEL(uart);`
52
53	409	markom	`#define MIN(a,b) ((a) < (b) ? (a) : (b))`
54
55	1501	nogj	`void uart_recv_break(void *dat);`
56			`void uart_recv_char(void *dat);`
57			`void uart_check_vapi(void *dat);`
58			`void uart_check_char(void *dat);`
59			`static void uart_sched_recv_check(struct dev_16450 *uart);`
60			`static void uart_vapi_cmd(void *dat);`
61	1502	nogj	`static void uart_clear_int(struct dev_16450 *uart, int intr);`
62	1499	nogj	`void uart_tx_send(void *dat);`
63
64	1503	nogj	`/* Number of clock cycles (one clock cycle is when UART_CLOCK_DIVIDER simulator`
65			`* cycles have elapsed) before a single character is transmitted or received. */`
66	355	markom	`static unsigned long char_clks(int dll, int dlh, int lcr)`
67	31	lampret	`{`
68	1396	nogj	`unsigned int bauds_per_char = 2;`
69	806	markom	`unsigned long char_clks = ((dlh << 8) + dll);`
70	355	markom
71			`if (lcr & UART_LCR_PARITY)`
72	1396	nogj	`bauds_per_char += 2;`
73	31	lampret
74	355	markom	`/* stop bits 1 or two */`
75			`if (lcr & UART_LCR_STOP)`
76	1396	nogj	`bauds_per_char += 4;`
77	355	markom	`else`
78			`if ((lcr & 0x3) != 0)`
79	1396	nogj	`bauds_per_char += 2;`
80	355	markom	`else`
81	1396	nogj	`bauds_per_char += 3;`
82	355	markom
83	1396	nogj	`bauds_per_char += 10 + ((lcr & 0x3) << 1);`
84	355	markom
85	1396	nogj	`return (char_clks * bauds_per_char) >> 1;`
86	31	lampret	`}`
87
88	1502	nogj	`/---------------------------------------------------[ Interrupt handling ]---/`
89			`/* Signals the specified interrupt. If a higher priority interrupt is already`
90			`* pending, do nothing */`
91			`static void uart_int_msi(void *dat)`
92			`{`
93			`struct dev_16450 *uart = dat;`
94
95			`uart->istat.ints \|= 1 << UART_IIR_MSI;`
96
97			`if(!(uart->regs.ier & UART_IER_MSI))`
98			`return;`
99
100			`if((uart->regs.iir & UART_IIR_NO_INT) \|\| (uart->regs.iir == UART_IIR_MSI)) {`
101			`TRACE("Raiseing modem status interrupt\n");`
102
103	1563	nogj	`if((uart->regs.iir != UART_IIR_MSI) && (uart->regs.iir != UART_IIR_NO_INT)) {`
104			`uart_clear_int(uart, uart->regs.iir);`
105			`uart->regs.iir = UART_IIR_MSI;`
106			`} else {`
107			`uart->regs.iir = UART_IIR_MSI;`
108			`SCHED_ADD(uart_int_msi, dat, UART_CLOCK_DIVIDER);`
109			`report_interrupt(uart->irq);`
110			`}`
111	1502	nogj	`}`
112			`}`
113
114			`static void uart_int_thri(void *dat)`
115			`{`
116			`struct dev_16450 *uart = dat;`
117
118			`uart->istat.ints \|= 1 << UART_IIR_THRI;`
119
120			`if(!(uart->regs.ier & UART_IER_THRI))`
121			`return;`
122
123			`if((uart->regs.iir & UART_IIR_NO_INT) \|\| (uart->regs.iir == UART_IIR_MSI) \|\|`
124			`(uart->regs.iir == UART_IIR_THRI)) {`
125			`TRACE("Raiseing transmitter holding register interrupt\n");`
126	1563	nogj
127			`if((uart->regs.iir != UART_IIR_THRI) && (uart->regs.iir != UART_IIR_NO_INT)) {`
128			`uart_clear_int(uart, uart->regs.iir);`
129			`uart->regs.iir = UART_IIR_THRI;`
130			`} else {`
131			`uart->regs.iir = UART_IIR_THRI;`
132			`SCHED_ADD(uart_int_thri, dat, UART_CLOCK_DIVIDER);`
133			`report_interrupt(uart->irq);`
134			`}`
135	1502	nogj	`}`
136			`}`
137
138			`static void uart_int_cti(void *dat)`
139			`{`
140			`struct dev_16450 *uart = dat;`
141
142			`uart->istat.ints \|= 1 << UART_IIR_CTI;`
143
144			`if(!(uart->regs.ier & UART_IER_RDI))`
145			`return;`
146
147			`if((uart->regs.iir != UART_IIR_RLSI) && (uart->regs.iir != UART_IIR_RDI)) {`
148			`TRACE("Raiseing character timeout interrupt\n");`
149
150	1563	nogj	`if((uart->regs.iir != UART_IIR_CTI) && (uart->regs.iir != UART_IIR_NO_INT)) {`
151			`uart_clear_int(uart, uart->regs.iir);`
152			`uart->regs.iir = UART_IIR_CTI;`
153			`} else {`
154			`uart->regs.iir = UART_IIR_CTI;`
155			`SCHED_ADD(uart_int_cti, dat, UART_CLOCK_DIVIDER);`
156			`report_interrupt(uart->irq);`
157			`}`
158	1502	nogj	`}`
159			`}`
160
161			`static void uart_int_rdi(void *dat)`
162			`{`
163			`struct dev_16450 *uart = dat;`
164
165			`uart->istat.ints \|= 1 << UART_IIR_RDI;`
166
167			`if(!(uart->regs.ier & UART_IER_RDI))`
168			`return;`
169
170			`if(uart->regs.iir != UART_IIR_RLSI) {`
171			`TRACE("Raiseing receiver data interrupt\n");`
172
173	1563	nogj	`if((uart->regs.iir != UART_IIR_RDI) && (uart->regs.iir != UART_IIR_NO_INT)) {`
174			`uart_clear_int(uart, uart->regs.iir);`
175			`uart->regs.iir = UART_IIR_RDI;`
176			`} else {`
177			`uart->regs.iir = UART_IIR_RDI;`
178			`SCHED_ADD(uart_int_rdi, dat, UART_CLOCK_DIVIDER);`
179			`report_interrupt(uart->irq);`
180			`}`
181	1502	nogj	`}`
182			`}`
183
184			`static void uart_int_rlsi(void *dat)`
185			`{`
186			`struct dev_16450 *uart = dat;`
187
188			`uart->istat.ints \|= 1 << UART_IIR_RLSI;`
189
190			`if(!(uart->regs.ier & UART_IER_RLSI))`
191			`return;`
192
193			`TRACE("Raiseing receiver line status interrupt\n");`
194
195			`/* Highest priority interrupt */`
196	1563	nogj	`if((uart->regs.iir != UART_IIR_RLSI) && (uart->regs.iir != UART_IIR_NO_INT)) {`
197			`uart_clear_int(uart, uart->regs.iir);`
198			`uart->regs.iir = UART_IIR_RLSI;`
199			`} else {`
200			`uart->regs.iir = UART_IIR_RLSI;`
201			`SCHED_ADD(uart_int_rlsi, dat, UART_CLOCK_DIVIDER);`
202			`report_interrupt(uart->irq);`
203			`}`
204	1502	nogj	`}`
205
206			`/* Checks to see if an RLSI interrupt is due and schedules one if need be */`
207			`static void uart_check_rlsi(void *dat)`
208			`{`
209			`struct dev_16450 *uart = dat;`
210
211			`if(uart->regs.lsr & (UART_LSR_OVRRUN \| UART_LSR_PARITY \| UART_LSR_FRAME \|`
212			`UART_LSR_BREAK))`
213			`uart_int_rlsi(uart);`
214			`}`
215
216			`/* Checks to see if an RDI interrupt is due and schedules one if need be */`
217			`static void uart_check_rdi(void *dat)`
218			`{`
219			`struct dev_16450 *uart = dat;`
220
221	1563	nogj	`if(uart->istat.rxbuf_full >= UART_FIFO_TRIGGER(uart->regs.fcr >> 6)) {`
222			`TRACE("FIFO trigger level reached %i\n",`
223			`UART_FIFO_TRIGGER(uart->regs.fcr >> 6));`
224	1502	nogj	`uart_int_rdi(uart);`
225	1563	nogj	`}`
226	1502	nogj	`}`
227
228			`/* Raises the next highest priority interrupt */`
229			`static void uart_next_int(void *dat)`
230			`{`
231			`struct dev_16450 *uart = dat;`
232
233			`/* Interrupt detection in proper priority order. */`
234			`if((uart->istat.ints & (1 << UART_IIR_RLSI)) &&`
235			`(uart->regs.ier & UART_IER_RLSI))`
236			`uart_int_rlsi(uart);`
237			`else if((uart->istat.ints & (1 << UART_IIR_RDI)) &&`
238			`(uart->regs.ier & UART_IER_RDI))`
239			`uart_int_rdi(uart);`
240			`else if((uart->istat.ints & (1 << UART_IIR_CTI)) &&`
241			`(uart->regs.ier & UART_IER_RDI))`
242			`uart_int_cti(uart);`
243			`else if((uart->istat.ints & (1 << UART_IIR_THRI)) &&`
244			`(uart->regs.ier & UART_IER_THRI))`
245			`uart_int_thri(uart);`
246			`else if((uart->istat.ints & (1 << UART_IIR_MSI)) &&`
247			`(uart->regs.ier & UART_IER_MSI))`
248			`uart_int_msi(uart);`
249			`else`
250			`uart->regs.iir = UART_IIR_NO_INT;`
251			`}`
252
253			`/* Clears potentially pending interrupts */`
254			`static void uart_clear_int(struct dev_16450 *uart, int intr)`
255			`{`
256			`uart->istat.ints &= ~(1 << intr);`
257
258	1563	nogj	`TRACE("Interrupt pending was %x\n", uart->regs.iir);`
259
260	1502	nogj	`/* Short-circuit most likely case */`
261			`if(uart->regs.iir == UART_IIR_NO_INT)`
262			`return;`
263
264			`if(intr != uart->regs.iir)`
265			`return;`
266
267			`TRACE("Clearing interrupt 0x%x\n", intr);`
268
269			`uart->regs.iir = UART_IIR_NO_INT;`
270
271			`switch(intr) {`
272			`case UART_IIR_RLSI:`
273			`SCHED_FIND_REMOVE(uart_int_rlsi, uart);`
274			`break;`
275			`case UART_IIR_RDI:`
276			`SCHED_FIND_REMOVE(uart_int_rdi, uart);`
277			`break;`
278			`case UART_IIR_CTI:`
279			`SCHED_FIND_REMOVE(uart_int_cti, uart);`
280			`break;`
281			`case UART_IIR_THRI:`
282			`SCHED_FIND_REMOVE(uart_int_thri, uart);`
283			`break;`
284			`case UART_IIR_MSI:`
285			`SCHED_FIND_REMOVE(uart_int_msi, uart);`
286			`break;`
287			`}`
288
289			`/* Schedule this job as there is no rush to send the next interrupt (the or.`
290			`* code is probably still running with interrupts disabled and this function`
291			`* is called from the uart_{read,write}_byte functions. */`
292			`SCHED_ADD(uart_next_int, uart, 0);`
293			`}`
294
295	1503	nogj	`/----------------------------------------------------[ Loopback handling ]---/`
296			`static void uart_loopback(struct dev_16450 *uart)`
297			`{`
298			`if(!(uart->regs.mcr & UART_MCR_LOOP))`
299			`return;`
300
301			`if((uart->regs.mcr & UART_MCR_AUX2) != ((uart->regs.msr & UART_MSR_DCD) >> 4))`
302			`uart->regs.msr \|= UART_MSR_DDCD;`
303
304			`if((uart->regs.mcr & UART_MCR_AUX1) < ((uart->regs.msr & UART_MSR_RI) >> 4))`
305			`uart->regs.msr \|= UART_MSR_TERI;`
306
307			`if((uart->regs.mcr & UART_MCR_RTS) != ((uart->regs.msr & UART_MSR_CTS) >> 3))`
308			`uart->regs.msr \|= UART_MSR_DCTS;`
309
310			`if((uart->regs.mcr & UART_MCR_DTR) != ((uart->regs.msr & UART_MSR_DSR) >> 5))`
311			`uart->regs.msr \|= UART_MSR_DDSR;`
312
313			`uart->regs.msr &= ~(UART_MSR_DCD \| UART_MSR_RI \| UART_MSR_DSR \| UART_MSR_CTS);`
314			`uart->regs.msr \|= ((uart->regs.mcr & UART_MCR_AUX2) << 4);`
315			`uart->regs.msr \|= ((uart->regs.mcr & UART_MCR_AUX1) << 4);`
316			`uart->regs.msr \|= ((uart->regs.mcr & UART_MCR_RTS) << 3);`
317			`uart->regs.msr \|= ((uart->regs.mcr & UART_MCR_DTR) << 5);`
318
319			`if(uart->regs.msr & (UART_MSR_DCTS \| UART_MSR_DDSR \| UART_MSR_TERI \|`
320			`UART_MSR_DDCD))`
321			`uart_int_msi(uart);`
322			`}`
323
324	1499	nogj	`/----------------------------------------------------[ Transmitter logic ]---/`
325			`/* Sends the data in the shift register to the outside world */`
326			`static void send_char (struct dev_16450 *uart, int bits_send)`
327			`{`
328			`PRINTF ("%c", (char)uart->iregs.txser);`
329			`TRACE("TX \'%c\' via UART at %"PRIxADDR"\n", (char)uart->iregs.txser,`
330			`uart->baseaddr);`
331			`if (uart->regs.mcr & UART_MCR_LOOP)`
332			`uart->iregs.loopback = uart->iregs.txser;`
333			`else {`
334			`/* Send to either VAPI or to file */`
335			`if (uart->vapi_id) {`
336			`int par, pe, fe, nbits;`
337			`int j, data;`
338			`unsigned long packet = 0;`
339
340			`nbits = MIN (bits_send, (uart->regs.lcr & UART_LCR_WLEN8) + 5);`
341			`/* Encode a packet */`
342			`packet = uart->iregs.txser & ((1 << nbits) - 1);`
343
344			`/* Calculate parity */`
345			`for (j = 0, par = 0; j < nbits; j++)`
346			`par ^= (packet >> j) & 1;`
347
348			`if (uart->regs.lcr & UART_LCR_PARITY) {`
349			`if (uart->regs.lcr & UART_LCR_SPAR) {`
350			`packet \|= 1 << nbits;`
351			`} else {`
352			`if (uart->regs.lcr & UART_LCR_EPAR)`
353			`packet \|= par << nbits;`
354			`else`
355			`packet \|= (par ^ 1) << nbits;`
356			`}`
357			`nbits++;`
358			`}`
359			`packet \|= 1 << (nbits++);`
360			`if (uart->regs.lcr & UART_LCR_STOP)`
361			`packet \|= 1 << (nbits++);`
362
363			`/* Decode a packet */`
364			`nbits = (uart->vapi.lcr & UART_LCR_WLEN8) + 5;`
365			`data = packet & ((1 << nbits) - 1);`
366
367			`/* Calculate parity, including parity bit */`
368			`for (j = 0, par = 0; j < nbits + 1; j++)`
369			`par ^= (packet >> j) & 1;`
370
371			`if (uart->vapi.lcr & UART_LCR_PARITY) {`
372			`if (uart->vapi.lcr & UART_LCR_SPAR) {`
373			`pe = !((packet >> nbits) & 1);`
374			`} else {`
375			`if (uart->vapi.lcr & UART_LCR_EPAR)`
376			`pe = par != 0;`
377			`else`
378			`pe = par != 1;`
379			`}`
380			`nbits++;`
381			`} else`
382			`pe = 0;`
383
384			`fe = ((packet >> (nbits++)) & 1) ^ 1;`
385			`if (uart->vapi.lcr & UART_LCR_STOP)`
386			`fe \|= ((packet >> (nbits++)) & 1) ^ 1;`
387
388			`TRACE ("lcr vapi %02x, uart %02x\n", uart->vapi.lcr, uart->regs.lcr);`
389			`data \|= (uart->vapi.lcr << 8) \| (pe << 16) \| (fe << 17) \| (uart->vapi.lcr << 8);`
390			`TRACE ("vapi_send (%08lx, %08x)\n", uart->vapi_id, data);`
391			`vapi_send (uart->vapi_id, data);`
392			`} else {`
393			`char buffer[1] = { uart->iregs.txser & 0xFF };`
394			`channel_write(uart->channel, buffer, 1);`
395			`}`
396			`}`
397			`}`
398
399			`/* Called when all the bits have been shifted out of the shift register */`
400			`void uart_char_clock(void *dat)`
401			`{`
402			`struct dev_16450 *uart = dat;`
403
404	1504	nogj	`TRACE("Sending data in shift reg: 0x%02"PRIx8"\n", uart->iregs.txser);`
405	1499	nogj	`/* We've sent all bits */`
406			`send_char(uart, (uart->regs.lcr & UART_LCR_WLEN8) + 5);`
407
408			`if(!uart->istat.txbuf_full)`
409			`uart->regs.lsr \|= UART_LSR_TXSERE;`
410			`else`
411			`uart_tx_send(uart);`
412			`}`
413
414			`/* Called when a break has been shifted out of the shift register */`
415			`void uart_send_break(void *dat)`
416			`{`
417			`struct dev_16450 *uart = dat;`
418
419			`TRACE("Sending break\n");`
420			`#if 0`
421			`/* Send broken frame */`
422			`int nbits_sent = ((uart->regs.lcr & UART_LCR_WLEN8) + 5) * (uart->istat.txser_clks - 1) / uart->char_clks;`
423			`send_char(i, nbits_sent);`
424			`#endif`
425			`/* Send one break signal */`
426			`vapi_send (uart->vapi_id, UART_LCR_SBC << 8);`
427
428			`/* Send the next char (if there is one) */`
429			`if(!uart->istat.txbuf_full)`
430			`uart->regs.lsr \|= UART_LSR_TXSERE;`
431			`else`
432			`uart_tx_send(uart);`
433			`}`
434
435			`/* Scheduled whenever the TX buffer has characters in it and we aren't sending`
436			`* a character. */`
437			`void uart_tx_send(void *dat)`
438			`{`
439			`struct dev_16450 *uart = dat;`
440
441			`uart->iregs.txser = uart->regs.txbuf[uart->istat.txbuf_tail];`
442			`uart->istat.txbuf_tail = (uart->istat.txbuf_tail + 1) % uart->fifo_len;`
443			`uart->istat.txbuf_full--;`
444			`uart->regs.lsr &= ~UART_LSR_TXSERE;`
445
446	1504	nogj	`TRACE("Moveing head of TX fifo (fill: %i) to shift reg 0x%02"PRIx8"\n",`
447	1499	nogj	`uart->istat.txbuf_full, uart->iregs.txser);`
448
449			`/* Schedules a char_clock to run in the correct amount of time */`
450			`if(!(uart->regs.lcr & UART_LCR_SBC)) {`
451			`SCHED_ADD(uart_char_clock, uart, uart->char_clks * UART_CLOCK_DIVIDER);`
452			`} else {`
453			`TRACE("Sending break not char\n");`
454			`SCHED_ADD(uart_send_break, uart, 0);`
455			`}`
456
457			`/* When UART is in either character mode, i.e. 16450 emulation mode, or FIFO`
458			`* mode, the THRE interrupt is raised when THR transitions from full to empty.`
459			`*/`
460			`if (!uart->istat.txbuf_full) {`
461			`uart->regs.lsr \|= UART_LSR_TXBUFE;`
462	1502	nogj	`uart_int_thri(uart);`
463	1499	nogj	`}`
464			`}`
465
466	1501	nogj	`/-------------------------------------------------------[ Receiver logic ]---/`
467			`/* Adds a character to the RX FIFO */`
468			`static void uart_add_char (struct dev_16450 *uart, int ch)`
469			`{`
470			`uart->regs.lsr \|= UART_LSR_RDRDY;`
471	1502	nogj	`uart_clear_int(uart, UART_IIR_CTI);`
472			`SCHED_FIND_REMOVE(uart_int_cti, uart);`
473			`SCHED_ADD(uart_int_cti, uart,`
474			`uart->char_clks * UART_CHAR_TIMEOUT * UART_CLOCK_DIVIDER);`
475	1501	nogj
476			`if (uart->istat.rxbuf_full + 1 > uart->fifo_len) {`
477			`uart->regs.lsr \|= UART_LSR_OVRRUN \| UART_LSR_RXERR;`
478	1502	nogj	`uart_int_rlsi(uart);`
479	1501	nogj	`} else {`
480			`TRACE("add %02x\n", ch);`
481			`uart->regs.rxbuf[uart->istat.rxbuf_head] = ch;`
482			`uart->istat.rxbuf_head = (uart->istat.rxbuf_head + 1) % uart->fifo_len;`
483			`if(!uart->istat.rxbuf_full++) {`
484			`uart->regs.lsr \|= ch >> 8;`
485	1502	nogj	`uart_check_rlsi(uart);`
486	1501	nogj	`}`
487			`}`
488	1502	nogj	`uart_check_rdi(uart);`
489	1501	nogj	`}`
490
491			`/* Called when a break sequence is about to start. It stops receiveing`
492			`* characters and schedules the uart_recv_break to send the break */`
493			`void uart_recv_break_start(void *dat)`
494			`{`
495			`struct dev_16450 *uart = dat;`
496
497			`uart->istat.receiveing = 0;`
498			`uart->istat.recv_break = 1;`
499
500			`SCHED_FIND_REMOVE(uart_recv_char, uart);`

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[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [peripheral/] [16450.c] - Blame information for rev 1780