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[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [peripheral/] [eth.c] - Blame information for rev 1487

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1 696 ivang 
/* ethernet.c -- Simulation of Ethernet MAC
2 
   Copyright (C) 2001 by Erez Volk, erez@opencores.org
3 
                         Ivan Guzvinec, ivang@opencores.org
4 
 
5 
   This file is part of OpenRISC 1000 Architectural Simulator.
6 
 
7 
   This program is free software; you can redistribute it and/or modify
8 
   it under the terms of the GNU General Public License as published by
9 
   the Free Software Foundation; either version 2 of the License, or
10 
   (at your option) any later version.
11 
 
12 
   This program is distributed in the hope that it will be useful,
13 
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14 
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 
   GNU General Public License for more details.
16 
 
17 
   You should have received a copy of the GNU General Public License
18 
   along with this program; if not, write to the Free Software
19 
   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 
*/
21 
 
22 
#include <stdlib.h>
23 
#include <stdio.h>
24 
#include <string.h>
25 
#include <sys/types.h>
26 
#include <sys/stat.h>
27 
#include <fcntl.h>
28 
#include <sys/poll.h>
29 
#include <sys/time.h>
30 
#include <unistd.h>
31 
#include <errno.h>
32 1308 phoenix 
#include <netinet/in.h>
33 696 ivang 
 
34 867 markom 
#include "config.h"
35 1350 nogj 
 
36 
#ifdef HAVE_INTTYPES_H
37 
#include <inttypes.h>
38 
#endif
39 
 
40 
#include "port.h"
41 
#include "arch.h"
42 
#include "config.h"
43 696 ivang 
#include "abstract.h"
44 
#include "ethernet_i.h"
45 
#include "dma.h"
46 
#include "sim-config.h"
47 
#include "fields.h"
48 
#include "crc32.h"
49 889 ivang 
#include "vapi.h"
50 1308 phoenix 
#include "pic.h"
51 1372 nogj 
#include "sched.h"
52 1308 phoenix 
#include "debug.h"
53 696 ivang 
 
54 1463 nogj 
DEFAULT_DEBUG_CHANNEL(eth);
55 
 
56 702 ivang 
/* simulator interface */
57 1366 nogj 
static void eth_vapi_read( unsigned long id, unsigned long data, void *dat);
58 696 ivang 
/* register interface */
59 1359 nogj 
static void eth_write32( oraddr_t addr, uint32_t value, void *dat );
60 
static uint32_t eth_read32( oraddr_t addr, void *dat );
61 696 ivang 
/* clock */
62 1372 nogj 
static void eth_controller_tx_clock( void * );
63 
static void eth_controller_rx_clock( void * );
64 696 ivang 
/* utility functions */
65 702 ivang 
static ssize_t eth_read_rx_file( struct eth_device *, void *, size_t );
66 
static void eth_skip_rx_file( struct eth_device *, off_t );
67 
static void eth_rewind_rx_file( struct eth_device *, off_t );
68 
static void eth_rx_next_packet( struct eth_device * );
69 
static void eth_write_tx_bd_num( struct eth_device *, unsigned long value );
70 696 ivang 
/* ========================================================================= */
71 702 ivang 
/*  TX LOGIC                                                                 */
72 696 ivang 
/*---------------------------------------------------------------------------*/
73 
 
74 
/*
75 
 * TX clock
76 
 * Responsible for starting and finishing TX
77 
 */
78 1372 nogj 
void eth_controller_tx_clock( void *dat )
79 696 ivang 
{
80 1372 nogj 
    struct eth_device *eth = dat;
81 702 ivang 
    int bAdvance   = 1;
82 867 markom 
#if HAVE_ETH_PHY
83 702 ivang 
    struct sockaddr_ll sll;
84 849 markom 
#endif /* HAVE_ETH_PHY */
85 1463 nogj 
    long nwritten = 0;
86 702 ivang 
    unsigned long read_word;
87 696 ivang 
 
88 
    switch (eth->tx.state) {
89 1372 nogj 
    case ETH_TXSTATE_IDLE:
90 1463 nogj 
        TRACE ("TX - entering state WAIT4BD (%ld)\n", eth->tx.bd_index);
91 1372 nogj 
        eth->tx.state = ETH_TXSTATE_WAIT4BD;
92 702 ivang 
        break;
93 696 ivang 
    case ETH_TXSTATE_WAIT4BD:
94 702 ivang 
        /* Read buffer descriptor */
95 
        eth->tx.bd = eth->regs.bd_ram[eth->tx.bd_index];
96 
        eth->tx.bd_addr = eth->regs.bd_ram[eth->tx.bd_index + 1];
97 
 
98 
        if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, READY ) ) {
99 
            /*****************/
100 
            /* initialize TX */
101 
            eth->tx.bytes_left = eth->tx.packet_length = GET_FIELD( eth->tx.bd, ETH_TX_BD, LENGTH );
102 
            eth->tx.bytes_sent = 0;
103 
 
104 
            /*   Initialize error status bits */
105 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, DEFER );
106 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, COLLISION );
107 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, RETRANSMIT );
108 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, UNDERRUN );
109 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, NO_CARRIER );
110 
            SET_FIELD ( eth->tx.bd, ETH_TX_BD, RETRY, 0 );
111 
 
112 
            /* Find out minimum length */
113 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, PAD ) ||
114 
                 TEST_FLAG( eth->regs.moder, ETH_MODER, PAD ) )
115 
                eth->tx.minimum_length = GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL );
116 
            else
117 
                eth->tx.minimum_length = eth->tx.packet_length;
118 
 
119 
            /* Find out maximum length */
120 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, HUGEN ) )
121 
                eth->tx.maximum_length = eth->tx.packet_length;
122 
            else
123 
                eth->tx.maximum_length = GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL );
124 
 
125 
            /* Do we need CRC on this packet? */
126 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, CRCEN ) ||
127 
                 (TEST_FLAG( eth->tx.bd, ETH_TX_BD, CRC) &&
128 
                  TEST_FLAG( eth->tx.bd, ETH_TX_BD, LAST)) )
129 
                eth->tx.add_crc = 1;
130 
            else
131 
                eth->tx.add_crc = 0;
132 
 
133 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, DLYCRCEN ) )
134 
                eth->tx.crc_dly = 1;
135 
            else
136 
                eth->tx.crc_dly = 0;
137 
            /* XXX - For now we skip CRC calculation */
138 
 
139 1463 nogj 
            TRACE( "Ethernet: Starting TX of %lu bytes (min. %u, max. %u)\n",
140 1350 nogj 
                   eth->tx.packet_length, eth->tx.minimum_length,
141 
                   eth->tx.maximum_length );
142 702 ivang 
 
143 
            if (eth->rtx_type == ETH_RTX_FILE) {
144 
                /* write packet length to file */
145 
                nwritten = write( eth->txfd, &(eth->tx.packet_length), sizeof(eth->tx.packet_length) );
146 
            }
147 
 
148 
            /************************************************/
149 
            /* start transmit with reading packet into FIFO */
150 1463 nogj 
                TRACE ("TX - entering state READFIFO\n");
151 702 ivang 
            eth->tx.state = ETH_TXSTATE_READFIFO;
152 
        }
153 
 
154 
        /* stay in this state if (TXEN && !READY) */
155 
        break;
156 696 ivang 
    case ETH_TXSTATE_READFIFO:
157 744 simons 
#if 1
158 702 ivang 
        if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
159 1487 nogj 
            read_word = eval_direct32(eth->tx.bytes_sent + eth->tx.bd_addr, 0, 0);
160 702 ivang 
            eth->tx_buff[eth->tx.bytes_sent]   = (unsigned char)(read_word >> 24);
161 
            eth->tx_buff[eth->tx.bytes_sent+1] = (unsigned char)(read_word >> 16);
162 
            eth->tx_buff[eth->tx.bytes_sent+2] = (unsigned char)(read_word >> 8);
163 
            eth->tx_buff[eth->tx.bytes_sent+3] = (unsigned char)(read_word);
164 
            eth->tx.bytes_sent += 4;
165 
        }
166 744 simons 
#else
167 
        if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
168 1487 nogj 
            eth->tx_buff[eth->tx.bytes_sent] = eval_direct8(eth->tx.bytes_sent + eth->tx.bd_addr, 0, 0);
169 744 simons 
            eth->tx.bytes_sent += 1;
170 
        }
171 
#endif
172 702 ivang 
        else {
173 1463 nogj 
            TRACE ("TX - entering state TRANSMIT\n");
174 702 ivang 
            eth->tx.state = ETH_TXSTATE_TRANSMIT;
175 
        }
176 
        break;
177 696 ivang 
    case ETH_TXSTATE_TRANSMIT:
178 702 ivang 
        /* send packet */
179 
        switch (eth->rtx_type) {
180 
        case ETH_RTX_FILE:
181 
            nwritten = write( eth->txfd, eth->tx_buff, eth->tx.packet_length );
182 
            break;
183 867 markom 
#if HAVE_ETH_PHY
184 702 ivang 
        case ETH_RTX_SOCK:
185 
            memset(&sll, 0, sizeof(sll));
186 705 ivang 
            sll.sll_ifindex = eth->ifr.ifr_ifindex;
187 
            nwritten = sendto(eth->rtx_sock, eth->tx_buff, eth->tx.packet_length, 0, (struct sockaddr *)&sll, sizeof(sll));
188 849 markom 
#endif /* HAVE_ETH_PHY */
189 702 ivang 
        }
190 
 
191 
        /* set BD status */
192 
        if (nwritten == eth->tx.packet_length) {
193 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
194 
            SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXB);
195 1463 nogj 
            TRACE ("ETH_INT_SOURCE = %0lx\n", eth->regs.int_source);
196 702 ivang 
 
197 1463 nogj 
            TRACE ("TX - entering state WAIT4BD\n");
198 1372 nogj 
            eth->tx.state = ETH_TXSTATE_WAIT4BD;
199 1463 nogj 
            TRACE ("send (%ld)bytes OK\n", nwritten);
200 702 ivang 
        }
201 
        else {
202 
            /* XXX - implement retry mechanism here! */
203 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
204 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, COLLISION);
205 
            SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXE);
206 1463 nogj 
            TRACE ("ETH_INT_SOURCE = %0lx\n", eth->regs.int_source);
207 702 ivang 
 
208 1463 nogj 
            TRACE ("TX - entering state WAIT4BD\n");
209 1372 nogj 
            eth->tx.state = ETH_TXSTATE_WAIT4BD;
210 1463 nogj 
            TRACE ("send FAILED!\n");
211 702 ivang 
        }
212 
 
213 
        eth->regs.bd_ram[eth->tx.bd_index] = eth->tx.bd;
214 
 
215 889 ivang 
        /* generate OK interrupt */
216 
        if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, TXE_M) ||
217 
             TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, TXB_M) )
218 
        {
219 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, IRQ ) )
220 
                report_interrupt( eth->mac_int );
221 
        }
222 
 
223 702 ivang 
        /* advance to next BD */
224 
        if (bAdvance) {
225 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, WRAP ) ||
226 
                            eth->tx.bd_index >= ETH_BD_COUNT )
227 
                eth->tx.bd_index = 0;
228 
            else
229 
                eth->tx.bd_index += 2;
230 
        }
231 
 
232 
        break;
233 696 ivang 
    }
234 1372 nogj 
 
235 
    /* Reschedule */
236 1390 nogj 
    SCHED_ADD( eth_controller_tx_clock, dat, 1 );
237 696 ivang 
}
238 
/* ========================================================================= */
239 
 
240 
 
241 
/* ========================================================================= */
242 702 ivang 
/*  RX LOGIC                                                                 */
243 696 ivang 
/*---------------------------------------------------------------------------*/
244 
 
245 
/*
246 
 * RX clock
247 
 * Responsible for starting and finishing RX
248 
 */
249 1372 nogj 
void eth_controller_rx_clock( void *dat )
250 696 ivang 
{
251 1372 nogj 
    struct eth_device *eth = dat;
252 702 ivang 
    long nread;
253 
    unsigned long send_word;
254 
 
255 
 
256 696 ivang 
    switch (eth->rx.state) {
257 
    case ETH_RXSTATE_IDLE:
258 1463 nogj 
        TRACE ("RX - entering state WAIT4BD (%ld)\n", eth->rx.bd_index);
259 1372 nogj 
        eth->rx.state = ETH_RXSTATE_WAIT4BD;
260 702 ivang 
        break;
261 
 
262 696 ivang 
    case ETH_RXSTATE_WAIT4BD:
263 702 ivang 
        eth->rx.bd = eth->regs.bd_ram[eth->rx.bd_index];
264 
        eth->rx.bd_addr = eth->regs.bd_ram[eth->rx.bd_index + 1];
265 
 
266 
        if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, READY ) ) {
267 
            /*****************/
268 
            /* Initialize RX */
269 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, MISS );
270 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, INVALID );
271 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, DRIBBLE );
272 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, UVERRUN );
273 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, COLLISION );
274 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG );
275 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT );
276 
 
277 1463 nogj 
            TRACE( "Ethernet: Starting RX\n" );
278 702 ivang 
 
279 
            /* Setup file to read from */
280 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, LOOPBCK ) ) {
281 
                eth->rx.fd = eth->txfd;
282 
                eth->rx.offset = &(eth->loopback_offset);
283 
            } else {
284 
                eth->rx.fd = eth->rxfd;
285 
                eth->rx.offset = 0;
286 
            }
287 1463 nogj 
            TRACE ("RX - entering state RECV\n");
288 702 ivang 
            eth->rx.state = ETH_RXSTATE_RECV;
289 
        }
290 705 ivang 
        else if (!TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN)) {
291 1463 nogj 
          TRACE ("RX - entering state IDLE\n");
292 705 ivang 
          eth->rx.state = ETH_RXSTATE_IDLE;
293 
        }
294 
        else {
295 744 simons 
            nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, /*MSG_PEEK | */MSG_DONTWAIT);
296 705 ivang 
            if (nread > 0) {
297 702 ivang 
                SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, BUSY);
298 723 ivang 
                if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, BUSY_M) )
299 
                  report_interrupt(eth->mac_int);
300 702 ivang 
            }
301 
        }
302 
        break;
303 
 
304 696 ivang 
    case ETH_RXSTATE_RECV:
305 702 ivang 
        switch (eth->rtx_type) {
306 
        case ETH_RTX_FILE:
307 
            /* Read packet length */
308 
            if ( eth_read_rx_file( eth, &(eth->rx.packet_length), sizeof(eth->rx.packet_length) )
309 
                     < sizeof(eth->rx.packet_length) ) {
310 
                /* TODO: just do what real ethernet would do (some kind of error state) */
311 1463 nogj 
                TRACE ("eth_start_rx(): File does not have a packet ready for RX (len = %ld)\n", eth->rx.packet_length );
312 
                sim_done();
313 702 ivang 
                break;
314 
            }
315 
 
316 
            /* Packet must be big enough to hold a header */
317 1244 hpanther 
            if ( eth->rx.packet_length < ETHER_HDR_LEN ){
318 1463 nogj 
                TRACE( "eth_start_rx(): Packet too small\n" );
319 702 ivang 
                eth_rx_next_packet( eth );
320 
 
321 1463 nogj 
                TRACE ("RX - entering state WAIT4BD\n");
322 1372 nogj 
                eth->rx.state = ETH_RXSTATE_WAIT4BD;
323 702 ivang 
                break;
324 
            }
325 
 
326 
            eth->rx.bytes_read = 0;
327 
            eth->rx.bytes_left = eth->rx.packet_length;
328 
 
329 
            /* for now Read entire packet into memory */
330 
            nread = eth_read_rx_file( eth, eth->rx_buff, eth->rx.bytes_left );
331 844 ivang 
            if ( nread < eth->rx.bytes_left ) {
332 1463 nogj 
                TRACE ("Read %ld from %ld. Error!\n", nread, eth->rx.bytes_left);
333 844 ivang 
                eth->rx.error = 1;
334 
                break;
335 
            }
336 
 
337 
            eth->rx.packet_length = nread;
338 
            eth->rx.bytes_left = nread;
339 
            eth->rx.bytes_read = 0;
340 
 
341 1463 nogj 
            TRACE ("RX - entering state WRITEFIFO\n");
342 844 ivang 
            eth->rx.state = ETH_RXSTATE_WRITEFIFO;
343 
 
344 702 ivang 
            break;
345 
 
346 
        case ETH_RTX_SOCK:
347 
            nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, MSG_DONTWAIT);
348 744 simons 
 
349 1463 nogj 
            if (nread == 0) {
350 
                TRACE("No data read\n");
351 744 simons 
                break;
352 1463 nogj 
            } else if (nread < 0) {
353 744 simons 
                if ( errno != EAGAIN ) {
354 1463 nogj 
                    TRACE ("recv() FAILED!\n");
355 889 ivang 
                    break;
356 
                }
357 1463 nogj 
                else
358 
                    break;
359 889 ivang 
            }
360 744 simons 
            /* If not promiscouos mode, check the destination address */
361 
            if (!TEST_FLAG(eth->regs.moder, ETH_MODER, PRO)) {
362 
                if (TEST_FLAG(eth->regs.moder, ETH_MODER, IAM) && (eth->rx_buff[0] & 1)) {
363 
                /* Nothing for now */
364 
                }
365 
 
366 
                if (eth->mac_address[5] != eth->rx_buff[0] ||
367 
                    eth->mac_address[4] != eth->rx_buff[1] ||
368 
                    eth->mac_address[3] != eth->rx_buff[2] ||
369 
                    eth->mac_address[2] != eth->rx_buff[3] ||
370 
                    eth->mac_address[1] != eth->rx_buff[4] ||
371 
                    eth->mac_address[0] != eth->rx_buff[5])
372 889 ivang 
                    break;
373 744 simons 
            }
374 
 
375 841 simons 
            eth->rx.packet_length = nread;
376 
            eth->rx.bytes_left = nread;
377 
            eth->rx.bytes_read = 0;
378 
 
379 1463 nogj 
            TRACE ("RX - entering state WRITEFIFO\n");
380 841 simons 
            eth->rx.state = ETH_RXSTATE_WRITEFIFO;
381 
 
382 702 ivang 
            break;
383 889 ivang 
        case ETH_RTX_VAPI:
384 1366 nogj 
            break;
385 702 ivang 
        }
386 841 simons 
        break;
387 
 
388 696 ivang 
    case ETH_RXSTATE_WRITEFIFO:
389 744 simons 
#if 1
390 702 ivang 
        send_word = ((unsigned long)eth->rx_buff[eth->rx.bytes_read]   << 24) |
391 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+1] << 16) |
392 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+2] << 8)  |
393 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+3] );
394 1487 nogj 
        set_direct32( eth->rx.bd_addr + eth->rx.bytes_read, send_word, 0, 0);
395 702 ivang 
        /* update counters */
396 1463 nogj 
        TRACE ("Write %ld, left %ld - %08lXd\n", eth->rx.bytes_read,
397 1350 nogj 
               eth->rx.bytes_left, send_word);
398 702 ivang 
        eth->rx.bytes_left -= 4;
399 
        eth->rx.bytes_read += 4;
400 744 simons 
#else
401 1487 nogj 
        set_direct8( eth->rx.bd_addr + eth->rx.bytes_read, eth->rx_buff[eth->rx.bytes_read], 0, 0);
402 744 simons 
        eth->rx.bytes_left -= 1;
403 
        eth->rx.bytes_read += 1;
404 
#endif
405 
 
406 702 ivang 
        if ( eth->rx.bytes_left <= 0 ) {
407 
            /* Write result to bd */
408 
            SET_FIELD( eth->rx.bd, ETH_RX_BD, LENGTH, eth->rx.packet_length );
409 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, READY);
410 705 ivang 
            SET_FLAG( eth->regs.int_source, ETH_INT_SOURCE, RXB);
411 1463 nogj 
            TRACE ("ETH_INT_SOURCE = %0lx\n", eth->regs.int_source);
412 702 ivang 
 
413 1068 simons 
            if ( eth->rx.packet_length < (GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL ) - 4) )
414 744 simons 
                SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT);
415 
            if ( eth->rx.packet_length > GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL ) )
416 702 ivang 
                SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG);
417 
 
418 
            eth->regs.bd_ram[eth->rx.bd_index] = eth->rx.bd;
419 
 
420 
            /* advance to next BD */
421 
            if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, WRAP ) || eth->rx.bd_index >= ETH_BD_COUNT )
422 1018 simons 
                eth->rx.bd_index = eth->regs.tx_bd_num << 1;
423 702 ivang 
            else
424 705 ivang 
                eth->rx.bd_index += 2;
425 702 ivang 
 
426 889 ivang 
            if ( ( TEST_FLAG( eth->regs.int_mask, ETH_INT_MASK, RXB_M ) ) &&
427 
                 ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, IRQ )              ) ) {
428 702 ivang 
                report_interrupt( eth->mac_int );
429 
            }
430 
 
431 
            /* ready to receive next packet */
432 1463 nogj 
                TRACE ("RX - entering state IDLE\n");
433 702 ivang 
            eth->rx.state = ETH_RXSTATE_IDLE;
434 
        }
435 
        break;
436 696 ivang 
    }
437 1372 nogj 
 
438 
    /* Reschedule */
439 1390 nogj 
    SCHED_ADD( eth_controller_rx_clock, dat, 1 );
440 696 ivang 
}
441 702 ivang 
 
442 696 ivang 
/* ========================================================================= */
443 702 ivang 
/* Move to next RX BD */
444 
void eth_rx_next_packet( struct eth_device *eth )
445 
{
446 
    /* Skip any possible leftovers */
447 
    if ( eth->rx.bytes_left )
448 
        eth_skip_rx_file( eth, eth->rx.bytes_left );
449 
}
450 
/* "Skip" bytes in RX file */
451 
void eth_skip_rx_file( struct eth_device *eth, off_t count )
452 
{
453 
    eth->rx.offset += count;
454 
}
455 696 ivang 
 
456 702 ivang 
/* Move RX file position back */
457 
void eth_rewind_rx_file( struct eth_device *eth, off_t count )
458 
{
459 
    eth->rx.offset -= count;
460 
}
461 
/*
462 
 * Utility function to read from the ethernet RX file
463 
 * This function moves the file pointer to the current place in the packet before reading
464 
 */
465 
ssize_t eth_read_rx_file( struct eth_device *eth, void *buf, size_t count )
466 
{
467 
    ssize_t result;
468 
 
469 
    if ( eth->rx.fd <= 0 ) {
470 1463 nogj 
        TRACE( "Ethernet: No RX file\n" );
471 702 ivang 
        return 0;
472 
    }
473 
 
474 
    if ( eth->rx.offset )
475 
        if ( lseek( eth->rx.fd, *(eth->rx.offset), SEEK_SET ) == (off_t)-1 ) {
476 1463 nogj 
            TRACE( "Ethernet: Error seeking RX file\n" );
477 702 ivang 
            return 0;
478 
        }
479 696 ivang 
 
480 702 ivang 
    result = read( eth->rx.fd, buf, count );
481 1463 nogj 
    TRACE ("Ethernet: read result = %d \n", result);
482 702 ivang 
    if ( eth->rx.offset && result >= 0 )
483 
        *(eth->rx.offset) += result;
484 
 
485 
    return result;
486 
}
487 
 
488 
/* ========================================================================= */
489 
 
490 696 ivang 
/*
491 702 ivang 
  Reset. Initializes all registers to default and places devices in
492 
         memory address space.
493 696 ivang 
*/
494 1372 nogj 
void eth_reset(void *dat)
495 696 ivang 
{
496 1372 nogj 
    struct eth_device *eth = dat;
497 1308 phoenix 
#if HAVE_ETH_PHY
498 702 ivang 
    int j;
499 
    struct sockaddr_ll sll;
500 849 markom 
#endif /* HAVE_ETH_PHY */
501 702 ivang 
 
502 
    if ( eth->baseaddr != 0 ) {
503 
        switch (eth->rtx_type) {
504 
        case ETH_RTX_FILE:
505 
            /* (Re-)open TX/RX files */
506 
            if ( eth->rxfd > 0 )
507 
                close( eth->rxfd );
508 
            if ( eth->txfd > 0 )
509 
                close( eth->txfd );
510 
            eth->rxfd = eth->txfd = -1;
511 
 
512 
            if ( (eth->rxfd = open( eth->rxfile, O_RDONLY )) < 0 )
513 
                fprintf( stderr, "Cannot open Ethernet RX file \"%s\"\n", eth->rxfile );
514 
            if ( (eth->txfd = open( eth->txfile,
515 1244 hpanther 
                                    O_RDWR | O_CREAT | O_APPEND
516 
 
517 
#if defined(O_SYNC)     /* BSD / Mac OS X manual doesn't know about O_SYNC */
518 
                                                                        | O_SYNC
519 
#endif
520 
                                                                        ,
521 702 ivang 
                                    S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH )) < 0 )
522 
                fprintf( stderr, "Cannot open Ethernet TX file \"%s\"\n", eth->txfile );
523 
            eth->loopback_offset = lseek( eth->txfd, 0, SEEK_END );
524 
 
525 
            break;
526 867 markom 
#if HAVE_ETH_PHY
527 702 ivang 
        case ETH_RTX_SOCK:
528 
            /* (Re-)open TX/RX sockets */
529 
            if (eth->rtx_sock != 0)
530 
                break;
531 
 
532 1463 nogj 
            TRACE ("RTX opening socket...\n");
533 702 ivang 
            eth->rtx_sock = socket(PF_PACKET, SOCK_RAW, htons(ETH_P_ALL));
534 
            if (eth->rtx_sock == -1) {
535 
                fprintf( stderr, "Cannot open rtx_sock.\n");
536 
                return;
537 
            }
538 
 
539 
            /* get interface index number */
540 1463 nogj 
            TRACE ("RTX getting interface...\n");
541 702 ivang 
            memset(&(eth->ifr), 0, sizeof(eth->ifr));
542 1372 nogj 
            strncpy(eth->ifr.ifr_name, eth->sockif, IFNAMSIZ);
543 702 ivang 
            if (ioctl(eth->rtx_sock, SIOCGIFINDEX, &(eth->ifr)) == -1) {
544 
                fprintf( stderr, "SIOCGIFINDEX failed!\n");
545 
                return;
546 
            }
547 1463 nogj 
            TRACE ("RTX Socket Interface : %d\n", eth->ifr.ifr_ifindex);
548 702 ivang 
 
549 
            /* Bind to interface... */
550 1463 nogj 
            TRACE ("Binding to the interface ifindex=%d\n", eth->ifr.ifr_ifindex);
551 702 ivang 
            memset(&sll, 0xff, sizeof(sll));
552 
            sll.sll_family = AF_PACKET;    /* allways AF_PACKET */
553 
            sll.sll_protocol = htons(ETH_P_ALL);
554 
            sll.sll_ifindex = eth->ifr.ifr_ifindex;
555 
            if (bind(eth->rtx_sock, (struct sockaddr *)&sll, sizeof(sll)) == -1) {
556 
                fprintf( stderr, "Error bind().\n");
557 
                return;
558 
            }
559 
 
560 
            /* first, flush all received packets. */
561 1463 nogj 
            TRACE ("Flush");
562 702 ivang 
            do {
563 
                fd_set fds;
564 
                struct timeval t;
565 
 
566 1463 nogj 
                TRACE( ".");
567 702 ivang 
                FD_ZERO(&fds);
568 
                FD_SET(eth->rtx_sock, &fds);
569 
                memset(&t, 0, sizeof(t));
570 
                j = select(FD_SETSIZE, &fds, NULL, NULL, &t);
571 
                if (j > 0)
572 
                    recv(eth->rtx_sock, eth->rx_buff, j, 0);
573 
            } while (j);
574 1463 nogj 
            TRACE ("\n");
575 702 ivang 
 
576 
            break;
577 1372 nogj 
#else /* HAVE_ETH_PHY */
578 
        case ETH_RTX_SOCK:
579 
            fprintf (stderr, "Ethernet phy not enabled in this configuration.  Configure with --enable-ethphy.\n");
580 
            exit (1);
581 
            break;
582 849 markom 
#endif /* HAVE_ETH_PHY */
583 702 ivang 
        }
584 
 
585 
        /* Set registers to default values */
586 
        memset( &(eth->regs), 0, sizeof(eth->regs) );
587 
        eth->regs.moder = 0x0000A000;
588 
        eth->regs.ipgt = 0x00000012;
589 
        eth->regs.ipgr1 = 0x0000000C;
590 
        eth->regs.ipgr2 = 0x00000012;
591 
        eth->regs.packetlen = 0x003C0600;
592 
        eth->regs.collconf = 0x000F003F;
593 
        eth->regs.miimoder = 0x00000064;
594 1018 simons 
        eth->regs.tx_bd_num = 0x00000040;
595 702 ivang 
 
596 
        /* Initialize TX/RX status */
597 
        memset( &(eth->tx), 0, sizeof(eth->tx) );
598 
        memset( &(eth->rx), 0, sizeof(eth->rx) );
599 1018 simons 
        eth->rx.bd_index = eth->regs.tx_bd_num << 1;
600 889 ivang 
 
601 
        /* Initialize VAPI */
602 1372 nogj 
        if (eth->base_vapi_id) {
603 
            vapi_install_multi_handler( eth->base_vapi_id, ETH_NUM_VAPI_IDS, eth_vapi_read, dat );
604 889 ivang 
        }
605 702 ivang 
    }
606 
}
607 
/* ========================================================================= */
608 
 
609 
 
610 696 ivang 
/*
611 
  Print register values on stdout
612 
*/
613 1372 nogj 
void eth_status( void *dat )
614 696 ivang 
{
615 1372 nogj 
    struct eth_device *eth = dat;
616 696 ivang 
 
617 1372 nogj 
    PRINTF( "\nEthernet MAC at 0x%"PRIxADDR":\n", eth->baseaddr );
618 
    PRINTF( "MODER        : 0x%08lX\n", eth->regs.moder );
619 
    PRINTF( "INT_SOURCE   : 0x%08lX\n", eth->regs.int_source );
620 
    PRINTF( "INT_MASK     : 0x%08lX\n", eth->regs.int_mask );
621 
    PRINTF( "IPGT         : 0x%08lX\n", eth->regs.ipgt );
622 
    PRINTF( "IPGR1        : 0x%08lX\n", eth->regs.ipgr1 );
623 
    PRINTF( "IPGR2        : 0x%08lX\n", eth->regs.ipgr2 );
624 
    PRINTF( "PACKETLEN    : 0x%08lX\n", eth->regs.packetlen );
625 
    PRINTF( "COLLCONF     : 0x%08lX\n", eth->regs.collconf );
626 
    PRINTF( "TX_BD_NUM    : 0x%08lX\n", eth->regs.tx_bd_num );
627 
    PRINTF( "CTRLMODER    : 0x%08lX\n", eth->regs.controlmoder );
628 
    PRINTF( "MIIMODER     : 0x%08lX\n", eth->regs.miimoder );
629 
    PRINTF( "MIICOMMAND   : 0x%08lX\n", eth->regs.miicommand );
630 
    PRINTF( "MIIADDRESS   : 0x%08lX\n", eth->regs.miiaddress );
631 
    PRINTF( "MIITX_DATA   : 0x%08lX\n", eth->regs.miitx_data );
632 
    PRINTF( "MIIRX_DATA   : 0x%08lX\n", eth->regs.miirx_data );
633 
    PRINTF( "MIISTATUS    : 0x%08lX\n", eth->regs.miistatus );
634 
    PRINTF( "MAC Address  : %02X:%02X:%02X:%02X:%02X:%02X\n",
635 
           eth->mac_address[0], eth->mac_address[1], eth->mac_address[2],
636 
           eth->mac_address[3], eth->mac_address[4], eth->mac_address[5] );
637 
    PRINTF( "HASH0        : 0x%08lX\n", eth->regs.hash0 );
638 
    PRINTF( "HASH1        : 0x%08lX\n", eth->regs.hash1 );
639 696 ivang 
}
640 
/* ========================================================================= */
641 
 
642 
 
643 
/*
644 
  Read a register
645 
*/
646 1359 nogj 
uint32_t eth_read32( oraddr_t addr, void *dat )
647 696 ivang 
{
648 1372 nogj 
    struct eth_device *eth = dat;
649 696 ivang 
 
650 
    switch( addr ) {
651 
    case ETH_MODER: return eth->regs.moder;
652 
    case ETH_INT_SOURCE: return eth->regs.int_source;
653 
    case ETH_INT_MASK: return eth->regs.int_mask;
654 
    case ETH_IPGT: return eth->regs.ipgt;
655 
    case ETH_IPGR1: return eth->regs.ipgr1;
656 
    case ETH_IPGR2: return eth->regs.ipgr2;
657 
    case ETH_PACKETLEN: return eth->regs.packetlen;
658 
    case ETH_COLLCONF: return eth->regs.collconf;
659 
    case ETH_TX_BD_NUM: return eth->regs.tx_bd_num;
660 
    case ETH_CTRLMODER: return eth->regs.controlmoder;
661 
    case ETH_MIIMODER: return eth->regs.miimoder;
662 
    case ETH_MIICOMMAND: return eth->regs.miicommand;
663 
    case ETH_MIIADDRESS: return eth->regs.miiaddress;
664 
    case ETH_MIITX_DATA: return eth->regs.miitx_data;
665 
    case ETH_MIIRX_DATA: return eth->regs.miirx_data;
666 
    case ETH_MIISTATUS: return eth->regs.miistatus;
667 
    case ETH_MAC_ADDR0: return (((unsigned long)eth->mac_address[3]) << 24) |
668 702 ivang 
                               (((unsigned long)eth->mac_address[2]) << 16) |
669 
                               (((unsigned long)eth->mac_address[1]) << 8) |
670 
                                 (unsigned long)eth->mac_address[0];
671 696 ivang 
    case ETH_MAC_ADDR1: return (((unsigned long)eth->mac_address[5]) << 8) |
672 702 ivang 
                                 (unsigned long)eth->mac_address[4];
673 744 simons 
    case ETH_HASH0: return eth->regs.hash0;
674 
    case ETH_HASH1: return eth->regs.hash1;
675 702 ivang 
    /*case ETH_DMA_RX_TX: return eth_rx( eth );*/
676 696 ivang 
    }
677 
 
678 
    if ( (addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE) )
679 702 ivang 
        return eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4];
680 696 ivang 
 
681 1350 nogj 
    PRINTF( "eth_read32( 0x%"PRIxADDR" ): Illegal address\n",
682 
            addr + eth->baseaddr );
683 696 ivang 
    return 0;
684 
}
685 
/* ========================================================================= */
686 
 
687 
 
688 
/*
689 
  Write a register
690 
*/
691 1359 nogj 
void eth_write32( oraddr_t addr, uint32_t value, void *dat )
692 696 ivang 
{
693 1372 nogj 
    struct eth_device *eth = dat;
694 
 
695 696 ivang 
    switch( addr ) {
696 1372 nogj 
    case ETH_MODER:
697 
 
698 
        if ( !TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN) &&
699 
             TEST_FLAG( value, ETH_MODER, RXEN) )
700 1390 nogj 
            SCHED_ADD( eth_controller_rx_clock, dat, 1 );
701 1372 nogj 
        else if ( !TEST_FLAG( value, ETH_MODER, RXEN) )
702 
            SCHED_FIND_REMOVE( eth_controller_rx_clock, dat);
703 
 
704 
        if ( !TEST_FLAG( eth->regs.moder, ETH_MODER, TXEN) &&
705 
             TEST_FLAG( value, ETH_MODER, TXEN) )
706 1390 nogj 
            SCHED_ADD( eth_controller_tx_clock, dat, 1 );
707 1372 nogj 
        else if ( !TEST_FLAG( value, ETH_MODER, TXEN) )
708 
            SCHED_FIND_REMOVE( eth_controller_tx_clock, dat);
709 
 
710 
        eth->regs.moder = value;
711 
 
712 
        if (TEST_FLAG(value, ETH_MODER, RST))
713 
            eth_reset( dat );
714 
        return;
715 744 simons 
    case ETH_INT_SOURCE: eth->regs.int_source &= ~value; return;
716 696 ivang 
    case ETH_INT_MASK: eth->regs.int_mask = value; return;
717 
    case ETH_IPGT: eth->regs.ipgt = value; return;
718 
    case ETH_IPGR1: eth->regs.ipgr1 = value; return;
719 
    case ETH_IPGR2: eth->regs.ipgr2 = value; return;
720 
    case ETH_PACKETLEN: eth->regs.packetlen = value; return;
721 
    case ETH_COLLCONF: eth->regs.collconf = value; return;
722 
    case ETH_TX_BD_NUM: eth_write_tx_bd_num( eth, value ); return;
723 
    case ETH_CTRLMODER: eth->regs.controlmoder = value; return;
724 
    case ETH_MIIMODER: eth->regs.miimoder = value; return;
725 
    case ETH_MIICOMMAND: eth->regs.miicommand = value; return;
726 
    case ETH_MIIADDRESS: eth->regs.miiaddress = value; return;
727 
    case ETH_MIITX_DATA: eth->regs.miitx_data = value; return;
728 
    case ETH_MIIRX_DATA: eth->regs.miirx_data = value; return;
729 
    case ETH_MIISTATUS: eth->regs.miistatus = value; return;
730 
    case ETH_MAC_ADDR0:
731 702 ivang 
        eth->mac_address[0] = value & 0xFF;
732 
        eth->mac_address[1] = (value >> 8) & 0xFF;
733 
        eth->mac_address[2] = (value >> 16) & 0xFF;
734 
        eth->mac_address[3] = (value >> 24) & 0xFF;
735 
        return;
736 696 ivang 
    case ETH_MAC_ADDR1:
737 702 ivang 
        eth->mac_address[4] = value & 0xFF;
738 
        eth->mac_address[5] = (value >> 8) & 0xFF;
739 
        return;
740 744 simons 
    case ETH_HASH0: eth->regs.hash0 = value; return;
741 
    case ETH_HASH1: eth->regs.hash1 = value; return;
742 702 ivang 
 
743 
    /*case ETH_DMA_RX_TX: eth_tx( eth, value ); return;*/
744 696 ivang 
    }
745 
 
746 
    if ( (addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE) ) {
747 702 ivang 
        eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4] = value;
748 
        return;
749 696 ivang 
    }
750 
 
751 1350 nogj 
    PRINTF( "eth_write32( 0x%"PRIxADDR" ): Illegal address\n",
752 
            addr + eth->baseaddr );
753 696 ivang 
    return;
754 
}
755 
/* ========================================================================= */
756 
 
757 
 
758 889 ivang 
/*
759 
 *   VAPI connection to outside
760 
 */
761 1366 nogj 
static void eth_vapi_read (unsigned long id, unsigned long data, void *dat)
762 889 ivang 
{
763 
    unsigned long which;
764 1372 nogj 
    struct eth_device *eth = dat;
765 889 ivang 
 
766 1372 nogj 
    which = id - eth->base_vapi_id;
767 
 
768 1463 nogj 
    TRACE( "ETH: id %08lx, data %08lx\n", id, data );
769 889 ivang 
 
770 
    if ( !eth ) {
771 1463 nogj 
        TRACE( "ETH: VAPI ID %08lx is not ours!\n", id );
772 889 ivang 
        return;
773 
    }
774 
 
775 
    switch( which ) {
776 
    case ETH_VAPI_DATA:
777 
        break;
778 
    case ETH_VAPI_CTRL:
779 
        break;
780 
    }
781 
}
782 
/* ========================================================================= */
783 
 
784 
 
785 702 ivang 
/* When TX_BD_NUM is written, also reset current RX BD index */
786 
void eth_write_tx_bd_num( struct eth_device *eth, unsigned long value )
787 
{
788 1018 simons 
    eth->regs.tx_bd_num = value & 0xFF;
789 
    eth->rx.bd_index = eth->regs.tx_bd_num << 1;
790 702 ivang 
}
791 1372 nogj 
 
792 702 ivang 
/* ========================================================================= */
793 
 
794 1372 nogj 
/*-----------------------------------------------[ Ethernet configuration ]---*/
795 
void eth_baseaddr(union param_val val, void *dat)
796 696 ivang 
{
797 1372 nogj 
  struct eth_device *eth = dat;
798 
  eth->baseaddr = val.addr_val;
799 696 ivang 
}
800 889 ivang 
 
801 1372 nogj 
void eth_dma(union param_val val, void *dat)
802 889 ivang 
{
803 1372 nogj 
  struct eth_device *eth = dat;
804 
  eth->dma = val.addr_val;
805 889 ivang 
}
806 1358 nogj 
 
807 1372 nogj 
void eth_rtx_type(union param_val val, void *dat)
808 
{
809 
  struct eth_device *eth = dat;
810 
  eth->rtx_type = val.int_val;
811 1358 nogj 
}
812 
 
813 1372 nogj 
void eth_rx_channel(union param_val val, void *dat)
814 
{
815 
  struct eth_device *eth = dat;
816 
  eth->rx_channel = val.int_val;
817 1358 nogj 
}
818 
 
819 1372 nogj 
void eth_tx_channel(union param_val val, void *dat)
820 
{
821 
  struct eth_device *eth = dat;
822 
  eth->tx_channel = val.int_val;
823 1358 nogj 
}
824 
 
825 1372 nogj 
void eth_rxfile(union param_val val, void *dat)
826 
{
827 
  struct eth_device *eth = dat;
828 
  if(!(eth->rxfile = strdup(val.str_val))) {
829 
    fprintf(stderr, "Peripheral Ethernet: Run out of memory\n");
830 
    exit(-1);
831 
  }
832 1358 nogj 
}
833 
 
834 
void eth_txfile(union param_val val, void *dat)
835 
{
836 1372 nogj 
  struct eth_device *eth = dat;
837 
  if(!(eth->txfile = strdup(val.str_val))) {
838 
    fprintf(stderr, "Peripheral Ethernet: Run out of memory\n");
839 
    exit(-1);
840 
  }
841 1358 nogj 
}
842 
 
843 
void eth_sockif(union param_val val, void *dat)
844 
{
845 1372 nogj 
  struct eth_device *eth = dat;
846 
  if(!(eth->sockif = strdup(val.str_val))) {
847 
    fprintf(stderr, "Peripheral Ethernet: Run out of memory\n");
848 
    exit(-1);
849 
  }
850 1358 nogj 
}
851 
 
852 
void eth_irq(union param_val val, void *dat)
853 
{
854 1372 nogj 
  struct eth_device *eth = dat;
855 
  eth->mac_int = val.int_val;
856 1358 nogj 
}
857 
 
858 
void eth_vapi_id(union param_val val, void *dat)
859 
{
860 1372 nogj 
  struct eth_device *eth = dat;
861 
  eth->base_vapi_id = val.int_val;
862 1358 nogj 
}
863 
 
864 1461 nogj 
void eth_enabled(union param_val val, void *dat)
865 
{
866 
  struct eth_device *eth = dat;
867 
  eth->enabled = val.int_val;
868 
}
869 
 
870 1372 nogj 
void *eth_sec_start(void)
871 
{
872 
  struct eth_device *new = malloc(sizeof(struct eth_device));
873 
 
874 
  if(!new) {
875 
    fprintf(stderr, "Peripheral Eth: Run out of memory\n");
876 
    exit(-1);
877 
  }
878 
 
879 1461 nogj 
  new->enabled = 1;
880 
 
881 1372 nogj 
  return new;
882 
}
883 
 
884 
void eth_sec_end(void *dat)
885 
{
886 
  struct eth_device *eth = dat;
887 1486 nogj 
  struct mem_ops ops;
888 1372 nogj 
 
889 1461 nogj 
  if(!eth->enabled) {
890 
    free(dat);
891 
    return;
892 
  }
893 
 
894 1486 nogj 
  memset(&ops, 0, sizeof(struct mem_ops));
895 
 
896 
  ops.readfunc32 = eth_read32;
897 
  ops.writefunc32 = eth_write32;
898 
  ops.read_dat32 = dat;
899 
  ops.write_dat32 = dat;
900 
 
901 
  /* FIXME: Correct delay? */
902 
  ops.delayr = 2;
903 
  ops.delayw = 2;
904 
  reg_mem_area( eth->baseaddr, ETH_ADDR_SPACE, 0, &ops );
905 1372 nogj 
  reg_sim_stat( eth_status, dat );
906 
  reg_sim_reset( eth_reset, dat );
907 
}
908 
 
909 1358 nogj 
void reg_ethernet_sec(void)
910 
{
911 1372 nogj 
  struct config_section *sec = reg_config_sec("ethernet", eth_sec_start, eth_sec_end);
912 1358 nogj 
 
913 
  reg_config_param(sec, "irq", paramt_int, eth_irq);
914 1461 nogj 
  reg_config_param(sec, "enabled", paramt_int, eth_enabled);
915 1358 nogj 
  reg_config_param(sec, "baseaddr", paramt_int, eth_baseaddr);
916 
  reg_config_param(sec, "dma", paramt_int, eth_dma);
917 
  reg_config_param(sec, "rtx_type", paramt_int, eth_rtx_type);
918 
  reg_config_param(sec, "rx_channel", paramt_int, eth_rx_channel);
919 
  reg_config_param(sec, "tx_channel", paramt_int, eth_tx_channel);
920 
  reg_config_param(sec, "rxfile", paramt_str, eth_rxfile);
921 
  reg_config_param(sec, "txfile", paramt_str, eth_txfile);
922 
  reg_config_param(sec, "sockif", paramt_str, eth_sockif);
923 
  reg_config_param(sec, "vapi_id", paramt_int, eth_vapi_id);
924 
}

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