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[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [cpu/] [or32/] [op.c] - Blame information for rev 1765

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/* op.c -- Micro operations for the recompiler
   Copyright (C) 2005 Gy�rgy `nog' Jeney, nog@sdf.lonestar.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
 
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
 
#include "config.h"
 
#ifdef HAVE_INTTYPES_H
#include <inttypes.h>
#endif
 
#include "port.h"
#include "arch.h"
#include "spr_defs.h"
#include "opcode/or32.h"
#include "sim-config.h"
#include "except.h"
#include "abstract.h"
#include "execute.h"
#include "sprs.h"
#include "sched.h"
 
#include "op_support.h"
 
#include "i386_regs.h"
 
#include "dyn_rec.h"
 
/* This must be here since the function in op_i386.h use this variable */
register struct cpu_state *env asm(CPU_STATE_REG);
 
#include "op_i386.h"
 
/*
 * WARNING: Before going of and wildly editing everything in this file remember
 * the following about its contents:
 * 1) The `functions' don't EVER return.  In otherwords haveing return state-
 *    ments _anywere_ in this file is likely not to work.  This is because
 *    dyngen just strips away the ret from the end of the function and just uses
 *    the function `body'.  If a ret statement is executed _anyware_ inside the
 *    dynamicly generated code, then it is undefined were we shall jump to.
 * 2) Because of 1), try not to have overly complicated functions.  In too
 *    complicated functions, gcc may decide to generate premature `exits'.  This
 *    is what passing the -fno-reorder-blocks command line switch to gcc helps
 *    with.  This is ofcourse not desired and is rather flaky as we don't (and
 *    can't) control the kind of code that gcc generates: It may work for one
 *    and break for another.  The less branches there are the less likely it is
 *    that a premature return shall occur.
 * 3) If gcc decides that it is going to be a basterd then it will optimise a
 *    very simple condition (if/switch) with a premature exit.  But gcc can't
 *    fuck ME over!  Just stick a FORCE_RET; at the END of the offending
 *    function.
 * 4) All operations must start with `op_'.  dyngen ignores all other functions.
 * 5) Local variables are depriciated: They hinder performance.
 * 6) Function calls are expensive as the stack has to be shifted (twice).
 */
 
/*#define __or_dynop __attribute__((noreturn))*/
#define __or_dynop
 
/* Temporaries to hold the (simulated) registers in */
register uint32_t t0 asm(T0_REG);
register uint32_t t1 asm(T1_REG);
register uint32_t t2 asm(T2_REG);
 
#define OP_PARAM1 ((uorreg_t)(&__op_param1))
#define OP_PARAM2 ((uorreg_t)(&__op_param2))
#define OP_PARAM3 ((uorreg_t)(&__op_param3))
 
extern uorreg_t __op_param1;
extern uorreg_t __op_param2;
extern uorreg_t __op_param3;
 
#define xglue(x, y) x ## y
#define glue(x, y) xglue(x, y)
 
/* Helper function.  Whenever we escape the recompiled code and there is a
 * potential that an exception may happen this function must be called */
static inline void save_t_temporary(void)
{
  env->t0 = t0;
  env->t1 = t1;
  env->t2 = t2;
}
 
/* Wrapper around do_scheduler.  This is needed because op_do_sched must be as
 * small as possible. */
void do_sched_wrap(void)
{
  save_t_temporary();
  upd_sim_cycles();
  do_scheduler();
}
 
/* do_scheduler wrapper for instructions that are in the delay slot */
void do_sched_wrap_delay(void)
{
  save_t_temporary();
  upd_sim_cycles();
  env->ts_current = 1;
  /* The PC gets set to the location of the jump, but do_sched increments that
   * so pull it back here to point to the right location again.  This could be
   * done in op_add_pc/op_set_pc_pc_delay but that would enlarge the recompiled
   * code. */
  //env->pc -= 4;
  do_scheduler();
  env->ts_current = 0;
}
 
void enter_dyn_code(oraddr_t addr, struct dyn_page *dp)
{
  uint16_t reg;
 
  addr &= config.immu.pagesize - 1;
  addr >>= 2;
 
  reg = dp->ts_bound[addr];
 
  if(reg & 0x1f)
    t0 = cpu_state.reg[reg & 0x1f];
 
  if((reg >> 5) & 0x1f)
    t1 = cpu_state.reg[(reg >> 5) & 0x1f];
 
  if((reg >> 10) & 0x1f)
    t2 = cpu_state.reg[(reg >> 10) & 0x1f];
 
  or_longjmp(dp->locs[addr]);
}
 
__or_dynop void op_t0_imm(void)
{
  t0 = OP_PARAM1;
}
 
__or_dynop void op_t1_imm(void)
{
  t1 = OP_PARAM1;
}
 
__or_dynop void op_t2_imm(void)
{
  t2 = OP_PARAM1;
}
 
__or_dynop void op_clear_t0(void)
{
  t0 = 0;
}
 
__or_dynop void op_clear_t1(void)
{
  t1 = 0;
}
 
__or_dynop void op_clear_t2(void)
{
  t2 = 0;
}
 
__or_dynop void op_move_t0_t1(void)
{
  t0 = t1;
}
 
__or_dynop void op_move_t0_t2(void)
{
  t0 = t2;
}
 
__or_dynop void op_move_t1_t0(void)
{
  t1 = t0;
}
 
__or_dynop void op_move_t1_t2(void)
{
  t1 = t2;
}
 
__or_dynop void op_move_t2_t0(void)
{
  t2 = t0;
}
 
__or_dynop void op_move_t2_t1(void)
{
  t2 = t1;
}
 
__or_dynop void op_set_pc_pc_delay(void)
{
  env->sprs[SPR_PPC] = get_pc();
  /* pc_delay is pulled back 4 since imediatly after this is run, the scheduler
   * runs which also increments it by 4 */
  set_pc(env->pc_delay - 4);
}
 
__or_dynop void op_set_pc_delay_imm(void)
{
  env->pc_delay = get_pc() + (orreg_t)OP_PARAM1;
  env->delay_insn = 1;
}
 
__or_dynop void op_set_pc_delay_pc(void)
{
  env->pc_delay = get_pc();
  env->delay_insn = 1;
}
 
__or_dynop void op_clear_pc_delay(void)
{
  env->pc_delay = 0;
  env->delay_insn = 1;
}
 
__or_dynop void op_do_jump(void)
{
  do_jump(get_pc());
}
 
__or_dynop void op_do_jump_delay(void)
{
  do_jump(env->pc_delay);
}
 
__or_dynop void op_clear_delay_insn(void)
{
  env->delay_insn = 0;
}
 
__or_dynop void op_set_delay_insn(void)
{
  env->delay_insn = 1;
}
 
__or_dynop void op_check_delay_slot(void)
{
  if(!env->delay_insn)
    OP_JUMP(OP_PARAM1);
}
 
__or_dynop void op_jmp_imm(void)
{
  OP_JUMP(OP_PARAM1);
}
 
__or_dynop void op_set_flag(void)
{
  env->sprs[SPR_SR] |= SPR_SR_F;
}
 
__or_dynop void op_clear_flag(void)
{
  env->sprs[SPR_SR] &= ~SPR_SR_F;
}
 
/* Used for the l.bf instruction.  Therefore if the flag is not set, jump over
 * all the jumping stuff */
__or_dynop void op_check_flag(void)
{
  if(!(env->sprs[SPR_SR] & SPR_SR_F)) {
    HANDLE_SCHED(do_sched_wrap, "no_sched_chk_flg");
    OP_JUMP(OP_PARAM1);
  }
}
 
/* Used for l.bf if the delay slot instruction is on another page */
__or_dynop void op_check_flag_delay(void)
{
  if(env->sprs[SPR_SR] & SPR_SR_F) {
    env->delay_insn = 1;
    env->pc_delay = get_pc() + (orreg_t)OP_PARAM1;
  }
}
 
/* Used for the l.bnf instruction.  Therefore if the flag is set, jump over all
 * the jumping stuff */
__or_dynop void op_check_not_flag(void)
{
  if(env->sprs[SPR_SR] & SPR_SR_F) {
    HANDLE_SCHED(do_sched_wrap, "no_sched_chk_not_flg");
    OP_JUMP(OP_PARAM1);
  }
}
 
/* Used for l.bnf if the delay slot instruction is on another page */
__or_dynop void op_check_not_flag_delay(void)
{
  if(!(env->sprs[SPR_SR] & SPR_SR_F)) {
    env->delay_insn = 1;
    env->pc_delay = get_pc() + (orreg_t)OP_PARAM1;
  }
}
 
__or_dynop void op_set_ts_current(void)
{
  env->ts_current = 1;
}
 
__or_dynop void op_add_pc(void)
{
  /* FIXME: Optimise */
  set_pc(get_pc() + OP_PARAM1);
}
 
__or_dynop void op_nop_exit(void)
{
  upd_sim_cycles();
  save_t_temporary();
  op_support_nop_exit();
  FORCE_RET;
}
 
__or_dynop void op_nop_reset(void)
{
  upd_sim_cycles();
  op_support_nop_reset();
  do_jump(EXCEPT_RESET);
}
 
__or_dynop void op_nop_printf(void)
{
  save_t_temporary();
  upd_sim_cycles();
  op_support_nop_printf();
  FORCE_RET;
}
 
__or_dynop void op_nop_report(void)
{
  save_t_temporary();
  upd_sim_cycles();
  op_support_nop_report();
  FORCE_RET;
}
 
__or_dynop void op_nop_report_imm(void)
{
  save_t_temporary();
  upd_sim_cycles();
  op_support_nop_report_imm(OP_PARAM1);
}
 
__or_dynop void op_check_null_except_t0_delay(void)
{
  if(!t0) {
    /* Do exception */
    env->sprs[SPR_EEAR_BASE] = get_pc() - 4;
    env->delay_insn = 0;
    do_jump(EXCEPT_ILLEGAL);
  }
}
 
 
__or_dynop void op_check_null_except_t0(void)
{
  if(!t0) {
    /* Do exception */
    env->sprs[SPR_EEAR_BASE] = get_pc();
    do_jump(EXCEPT_ILLEGAL);
  }
}
 
__or_dynop void op_check_null_except_t1_delay(void)
{
  if(!t1) {
    /* Do exception */
    env->sprs[SPR_EEAR_BASE] = get_pc() - 4;
    env->delay_insn = 0;
    do_jump(EXCEPT_ILLEGAL);
  }
}
 
 
__or_dynop void op_check_null_except_t1(void)
{
  if(!t1) {
    /* Do exception */
    env->sprs[SPR_EEAR_BASE] = get_pc();
    do_jump(EXCEPT_ILLEGAL);
  }
}
 
__or_dynop void op_check_null_except_t2_delay(void)
{
  if(!t2) {
    /* Do exception */
    env->sprs[SPR_EEAR_BASE] = get_pc() - 4;
    env->delay_insn = 0;
    do_jump(EXCEPT_ILLEGAL);
  }
}
 
__or_dynop void op_check_null_except_t2(void)
{
  if(!t2) {
    /* Do exception */
    env->sprs[SPR_EEAR_BASE] = get_pc();
    do_jump(EXCEPT_ILLEGAL);
  }
}
 
__or_dynop void op_analysis(void)
{
  env->iqueue.insn_index = OP_PARAM1;
  env->iqueue.insn = OP_PARAM2;
  env->iqueue.insn_addr = get_pc();
  save_t_temporary();
  op_support_analysis();
  FORCE_RET;
}
 
#define OP_EXTRA
 
#define OP /
#define OP_CAST(T) (orreg_t)T
#define OP_NAME div
#include "op_arith_op.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP /
#define OP_CAST(T) T
#define OP_NAME divu
#include "op_arith_op.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP *
#define OP_CAST(T) T
#define OP_NAME mulu
#include "op_arith_op.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP -
#define OP_CAST(T) (orreg_t)T
#define OP_NAME sub
#include "op_arith_op.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#undef OP_EXTRA
 
#define OP_HAS_IMM
 
#define OP_EXTRA + ((env->sprs[SPR_SR] & SPR_SR_CY) >> 10)
#define OP +
#define OP_CAST(T) (orreg_t)T
#define OP_NAME addc
#include "op_arith_op.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#undef OP_EXTRA
#define OP_EXTRA
 
#define OP +
#define OP_CAST(T) (orreg_t)T
#define OP_NAME add
#include "op_arith_op.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP &
#define OP_CAST(T) T
#define OP_NAME and
#include "op_arith_op.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP *
#define OP_CAST(T) (orreg_t)T
#define OP_NAME mul
#include "op_arith_op.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP |
#define OP_CAST(T) T
#define OP_NAME or
#include "op_arith_op.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP <<
#define OP_CAST(T) T
#define OP_NAME sll
#include "op_arith_op.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP >>
#define OP_CAST(T) (orreg_t)T
#define OP_NAME sra
#include "op_arith_op.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP >>
#define OP_CAST(T) T
#define OP_NAME srl
#include "op_arith_op.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP ^
#define OP_CAST(T) T
#define OP_NAME xor
#include "op_arith_op.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#undef OP_EXTRA
#undef OP_HAS_IMM
 
#define EXT_NAME extbs
#define EXT_TYPE int8_t
#define EXT_CAST (orreg_t)
#include "op_extend_op.h"
#undef EXT_CAST
#undef EXT_TYPE
#undef EXT_NAME
 
#define EXT_NAME extbz
#define EXT_TYPE uint8_t
#define EXT_CAST (uorreg_t)
#include "op_extend_op.h"
#undef EXT_CAST
#undef EXT_TYPE
#undef EXT_NAME
 
#define EXT_NAME exths
#define EXT_TYPE int16_t
#define EXT_CAST (orreg_t)
#include "op_extend_op.h"
#undef EXT_CAST
#undef EXT_TYPE
#undef EXT_NAME
 
#define EXT_NAME exthz
#define EXT_TYPE uint16_t
#define EXT_CAST (uorreg_t)
#include "op_extend_op.h"
#undef EXT_CAST
#undef EXT_TYPE
#undef EXT_NAME
 
#define COMP ==
#define COMP_NAME sfeq
#define COMP_CAST(t) t
#include "op_comp_op.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP !=
#define COMP_NAME sfne
#define COMP_CAST(t) t
#include "op_comp_op.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP >
#define COMP_NAME sfgtu
#define COMP_CAST(t) t
#include "op_comp_op.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP >=
#define COMP_NAME sfgeu
#define COMP_CAST(t) t
#include "op_comp_op.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP <
#define COMP_NAME sfltu
#define COMP_CAST(t) t
#include "op_comp_op.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP <=
#define COMP_NAME sfleu
#define COMP_CAST(t) t
#include "op_comp_op.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP >
#define COMP_NAME sfgts
#define COMP_CAST(t) (orreg_t)t
#include "op_comp_op.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP >=
#define COMP_NAME sfges
#define COMP_CAST(t) (orreg_t)t
#include "op_comp_op.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP <
#define COMP_NAME sflts
#define COMP_CAST(t) (orreg_t)t
#include "op_comp_op.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP <=
#define COMP_NAME sfles
#define COMP_CAST(t) (orreg_t)t
#include "op_comp_op.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define REG 1
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 2
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 3
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 4
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 5
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 6
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 7
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 8
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 9
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 10
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 11
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 12
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 13
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 14
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 15
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 16
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 17
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 18
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 19
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 20
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 21
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 22
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 23
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 24
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 25
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 26
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 27
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 28
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 29
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 30
#include "op_t_reg_mov_op.h"
#undef REG
 
#define REG 31
#include "op_t_reg_mov_op.h"
#undef REG
 
#define DST_T t0
#define SRC_T t0
#include "op_ff1_op.h"
#undef SRC_T
 
#define SRC_T t1
#include "op_ff1_op.h"
#undef SRC_T
 
#define SRC_T t2
#include "op_ff1_op.h"
#undef SRC_T
#undef DST_T
 
#define DST_T t1
#define SRC_T t0
#include "op_ff1_op.h"
#undef SRC_T
 
#define SRC_T t1
#include "op_ff1_op.h"
#undef SRC_T
 
#define SRC_T t2
#include "op_ff1_op.h"
#undef SRC_T
#undef DST_T
 
#define DST_T t2
#define SRC_T t0
#include "op_ff1_op.h"
#undef SRC_T
 
#define SRC_T t1
#include "op_ff1_op.h"
#undef SRC_T
 
#define SRC_T t2
#include "op_ff1_op.h"
#undef SRC_T
#undef DST_T
 
#define SPR_T_NAME SPR_T
#define GPR_T_NAME GPR_T
 
#define SPR_T t0
#define GPR_T t0
#include "op_mftspr_op.h"
#undef GPR_T
 
#define GPR_T t1
#include "op_mftspr_op.h"
#undef GPR_T
 
#define GPR_T t2
#include "op_mftspr_op.h"
#undef GPR_T
#undef SPR_T
 
#define SPR_T t1
#define GPR_T t0
#include "op_mftspr_op.h"
#undef GPR_T
 
#define GPR_T t1
#include "op_mftspr_op.h"
#undef GPR_T
 
#define GPR_T t2
#include "op_mftspr_op.h"
#undef GPR_T
#undef SPR_T
 
#define SPR_T t2
#define GPR_T t0
#include "op_mftspr_op.h"
#undef GPR_T
 
#define GPR_T t1
#include "op_mftspr_op.h"
#undef GPR_T
 
#define GPR_T t2
#include "op_mftspr_op.h"
#undef GPR_T
#undef SPR_T
 
#undef GPR_T_NAME
#undef SPR_T_NAME
 
#define SPR_T_NAME imm
#define GPR_T_NAME GPR_T
 
#define SPR_T 0
 
#define GPR_T t0
#include "op_mftspr_op.h"
#undef GPR_T
 
#define GPR_T t1
#include "op_mftspr_op.h"
#undef GPR_T
 
#define GPR_T t2
#include "op_mftspr_op.h"
#undef GPR_T
#undef SPR_T
 
#undef SPR_T_NAME
#undef GPR_T_NAME
 
#define ONLY_MTSPR
#define SPR_T_NAME SPR_T
#define GPR_T_NAME clear
 
#define GPR_T 0
 
#define SPR_T t0
#include "op_mftspr_op.h"
#undef SPR_T
 
#define SPR_T t1
#include "op_mftspr_op.h"
#undef SPR_T
 
#define SPR_T t2
#include "op_mftspr_op.h"
#undef SPR_T
 
#undef GPR_T
 
#undef SPR_T_NAME
#undef GPR_T_NAME
 
#define SPR_T_NAME imm
#define GPR_T_NAME clear
#define GPR_T 0
#define SPR_T 0
#include "op_mftspr_op.h"
#undef SPR_T
#undef GPR_T
#undef GPR_T_NAME
#undef SPR_T_NAME
 
#undef ONLY_MTSPR
 
#define OP +=
#define OP_NAME mac
#include "op_mac_op.h"
#undef OP_NAME
#undef OP
 
#define OP -=
#define OP_NAME msb
#include "op_mac_op.h"
#undef OP_NAME
#undef OP
 
#define LS_OP_NAME lbz
#define LS_OP_CAST
#define LS_OP_FUNC eval_mem8
#include "op_lwhb_op.h"
#undef LS_OP_FUNC
#undef LS_OP_CAST
#undef LS_OP_NAME
 
#define LS_OP_NAME lbs
#define LS_OP_CAST (int8_t)
#define LS_OP_FUNC eval_mem8
#include "op_lwhb_op.h"
#undef LS_OP_FUNC
#undef LS_OP_CAST
#undef LS_OP_NAME
 
#define LS_OP_NAME lhz
#define LS_OP_CAST
#define LS_OP_FUNC eval_mem16
#include "op_lwhb_op.h"
#undef LS_OP_FUNC
#undef LS_OP_CAST
#undef LS_OP_NAME
 
#define LS_OP_NAME lhs
#define LS_OP_CAST (int16_t)
#define LS_OP_FUNC eval_mem16
#include "op_lwhb_op.h"
#undef LS_OP_FUNC
#undef LS_OP_CAST
#undef LS_OP_NAME
 
#define LS_OP_NAME lwz
#define LS_OP_CAST
#define LS_OP_FUNC eval_mem32
#include "op_lwhb_op.h"
#undef LS_OP_FUNC
#undef LS_OP_CAST
#undef LS_OP_NAME
 
#define LS_OP_NAME lws
#define LS_OP_CAST (int32_t)
#define LS_OP_FUNC eval_mem32
#include "op_lwhb_op.h"
#undef LS_OP_FUNC
#undef LS_OP_CAST
#undef LS_OP_NAME
 
#define S_OP_NAME sb
#define S_FUNC set_mem8
#include "op_swhb_op.h"
#undef S_FUNC
#undef S_OP_NAME
 
#define S_OP_NAME sh
#define S_FUNC set_mem16
#include "op_swhb_op.h"
#undef S_FUNC
#undef S_OP_NAME
 
#define S_OP_NAME sw
#define S_FUNC set_mem32
#include "op_swhb_op.h"
#undef S_FUNC
#undef S_OP_NAME
 
__or_dynop void op_join_mem_cycles(void)
{
  join_mem_cycles();
}
 
__or_dynop void op_store_link_addr_gpr(void)
{
  env->reg[LINK_REGNO] = get_pc() + 8;
}
 
__or_dynop void op_prep_rfe(void)
{
  env->sprs[SPR_SR] = env->sprs[SPR_ESR_BASE] | SPR_SR_FO;
  env->sprs[SPR_PPC] = get_pc();
  env->ts_current = 1;
  set_pc(env->sprs[SPR_EPCR_BASE] - 4);
}
 
static inline void prep_except(oraddr_t epcr_base)
{
  env->sprs[SPR_EPCR_BASE] = epcr_base;
 
  env->sprs[SPR_ESR_BASE] = env->sprs[SPR_SR];
 
  /* Address translation is always disabled when starting exception. */
  env->sprs[SPR_SR] &= ~SPR_SR_DME;
  env->sprs[SPR_SR] &= ~SPR_SR_IME;
 
  env->sprs[SPR_SR] &= ~SPR_SR_OVE;   /* Disable overflow flag exception. */
 
  env->sprs[SPR_SR] |= SPR_SR_SM;     /* SUPV mode */
  env->sprs[SPR_SR] &= ~(SPR_SR_IEE | SPR_SR_TEE);    /* Disable interrupts. */
}
 
__or_dynop void op_set_except_pc(void)
{
  set_pc(OP_PARAM1);
}
 
/* Before the code in op_{sys,trap}{,_delay} gets run, the scheduler runs.
 * Therefore the pc will point to the instruction after the l.sys or l.trap
 * instruction */
__or_dynop void op_prep_sys_delay(void)
{
  env->delay_insn = 0;
  env->ts_current = 1;
  prep_except(get_pc() - 4);
  set_pc(EXCEPT_SYSCALL - 4);
}
 
__or_dynop void op_prep_sys(void)
{
  env->ts_current = 1;
  prep_except(get_pc() + 4);
  set_pc(EXCEPT_SYSCALL - 4);
}
 
__or_dynop void op_prep_trap_delay(void)
{
  env->ts_current = 1;
  env->delay_insn = 0;
  prep_except(get_pc() - 4);
  set_pc(EXCEPT_TRAP - 4);
}
 
__or_dynop void op_prep_trap(void)
{
  env->ts_current = 1;
  prep_except(get_pc());
  set_pc(EXCEPT_TRAP - 4);
}
 
/* FIXME: This `instruction' should be split up like the l.trap and l.sys
 * instructions are done */
__or_dynop void op_illegal_delay(void)
{
  env->delay_insn = 0;
  env->ts_current = 1;
  env->sprs[SPR_EEAR_BASE] = get_pc() - 4;
  do_jump(EXCEPT_ILLEGAL - 4);
}
 
__or_dynop void op_illegal(void)
{
  env->sprs[SPR_EEAR_BASE] = get_pc();
  do_jump(EXCEPT_ILLEGAL);
}
 
__or_dynop void op_do_sched(void)
{
  HANDLE_SCHED(do_sched_wrap, "no_sched");
}
 
__or_dynop void op_do_sched_delay(void)
{
  HANDLE_SCHED(do_sched_wrap_delay, "no_sched_delay");
}
 
__or_dynop void op_macc(void)
{
  env->sprs[SPR_MACLO] = 0;
  env->sprs[SPR_MACHI] = 0;
}
 
__or_dynop void op_store_insn_ea(void)
{
  env->insn_ea = OP_PARAM1;
}
 
__or_dynop void op_calc_insn_ea_t0(void)
{
  env->insn_ea = t0 + OP_PARAM1;
}
 
__or_dynop void op_calc_insn_ea_t1(void)
{
  env->insn_ea = t1 + OP_PARAM1;
}
 
__or_dynop void op_calc_insn_ea_t2(void)
{
  env->insn_ea = t2 + OP_PARAM1;
}
 
__or_dynop void op_macrc_t0(void)
{
  /* FIXME: How is this supposed to work?  The architechture manual says that
   * the low 32-bits shall be saved into rD.  I have just copied this code from
   * insnset.c to make testbench/mul pass */
  int64_t temp = env->sprs[SPR_MACLO] | ((int64_t)env->sprs[SPR_MACHI] << 32);
 
  t0 = (orreg_t)(temp >> 28);
  env->sprs[SPR_MACLO] = 0;
  env->sprs[SPR_MACHI] = 0;
}
 
__or_dynop void op_macrc_t1(void)
{
  /* FIXME: How is this supposed to work?  The architechture manual says that
   * the low 32-bits shall be saved into rD.  I have just copied this code from
   * insnset.c to make testbench/mul pass */
  int64_t temp = env->sprs[SPR_MACLO] | ((int64_t)env->sprs[SPR_MACHI] << 32);
 
  t1 = (orreg_t)(temp >> 28);
 
  env->sprs[SPR_MACLO] = 0;
  env->sprs[SPR_MACHI] = 0;
}
 
__or_dynop void op_macrc_t2(void)
{
  /* FIXME: How is this supposed to work?  The architechture manual says that
   * the low 32-bits shall be saved into rD.  I have just copied this code from
   * insnset.c to make testbench/mul pass */
  int64_t temp = env->sprs[SPR_MACLO] | ((int64_t)env->sprs[SPR_MACHI] << 32);
 
  t2 = (orreg_t)(temp >> 28);
 
  env->sprs[SPR_MACLO] = 0;
  env->sprs[SPR_MACHI] = 0;
}
 
__or_dynop void op_mac_imm_t0(void)
{
  int64_t temp = env->sprs[SPR_MACLO] | ((int64_t)env->sprs[SPR_MACHI] << 32);
 
  temp += (int64_t)t0 * (int64_t)OP_PARAM1;
 
  env->sprs[SPR_MACLO] = temp & 0xffffffff;
  env->sprs[SPR_MACHI] = temp >> 32;
}
 
__or_dynop void op_mac_imm_t1(void)
{
  int64_t temp = env->sprs[SPR_MACLO] | ((int64_t)env->sprs[SPR_MACHI] << 32);
 
  temp += (int64_t)t1 * (int64_t)OP_PARAM1;
 
  env->sprs[SPR_MACLO] = temp & 0xffffffff;
  env->sprs[SPR_MACHI] = temp >> 32;
}
 
__or_dynop void op_mac_imm_t2(void)
{
  int64_t temp = env->sprs[SPR_MACLO] | ((int64_t)env->sprs[SPR_MACHI] << 32);
 
  temp += (int64_t)t2 * (int64_t)OP_PARAM1;
 
  env->sprs[SPR_MACLO] = temp & 0xffffffff;
  env->sprs[SPR_MACHI] = temp >> 32;
}
 
__or_dynop void op_cmov_t0_t0_t1(void)
{
  t0 = env->sprs[SPR_SR] & SPR_SR_F ? t0 : t1;
}
 
__or_dynop void op_cmov_t0_t0_t2(void)
{
  t0 = env->sprs[SPR_SR] & SPR_SR_F ? t0 : t2;
}
 
__or_dynop void op_cmov_t0_t1_t0(void)
{
  t0 = env->sprs[SPR_SR] & SPR_SR_F ? t1 : t0;
}
 
__or_dynop void op_cmov_t0_t1_t2(void)
{
  t0 = env->sprs[SPR_SR] & SPR_SR_F ? t1 : t2;
  FORCE_RET;
}
 
__or_dynop void op_cmov_t0_t2_t0(void)
{
  t0 = env->sprs[SPR_SR] & SPR_SR_F ? t2 : t0;
}
 
__or_dynop void op_cmov_t0_t2_t1(void)
{
  t0 = env->sprs[SPR_SR] & SPR_SR_F ? t2 : t1;
  FORCE_RET;
}
 
__or_dynop void op_cmov_t1_t0_t1(void)
{
  t1 = env->sprs[SPR_SR] & SPR_SR_F ? t0 : t1;
}
 
__or_dynop void op_cmov_t1_t0_t2(void)
{
  t1 = env->sprs[SPR_SR] & SPR_SR_F ? t0 : t2;
  FORCE_RET;
}
 
__or_dynop void op_cmov_t1_t1_t0(void)
{
  t1 = env->sprs[SPR_SR] & SPR_SR_F ? t1 : t0;
}
 
__or_dynop void op_cmov_t1_t1_t2(void)
{
  t1 = env->sprs[SPR_SR] & SPR_SR_F ? t1 : t2;
}
 
__or_dynop void op_cmov_t1_t2_t0(void)
{
  t1 = env->sprs[SPR_SR] & SPR_SR_F ? t2 : t0;
  FORCE_RET;
}
 
__or_dynop void op_cmov_t1_t2_t1(void)
{
  t1 = env->sprs[SPR_SR] & SPR_SR_F ? t2 : t1;
}
 
__or_dynop void op_cmov_t2_t0_t1(void)
{
  t2 = env->sprs[SPR_SR] & SPR_SR_F ? t0 : t1;
  FORCE_RET;
}
 
__or_dynop void op_cmov_t2_t0_t2(void)
{
  t2 = env->sprs[SPR_SR] & SPR_SR_F ? t0 : t2;
}
 
__or_dynop void op_cmov_t2_t1_t0(void)
{
  t2 = env->sprs[SPR_SR] & SPR_SR_F ? t1 : t0;
  FORCE_RET;
}
 
__or_dynop void op_cmov_t2_t1_t2(void)
{
  t2 = env->sprs[SPR_SR] & SPR_SR_F ? t1 : t2;
}
 
__or_dynop void op_cmov_t2_t2_t0(void)
{
  t2 = env->sprs[SPR_SR] & SPR_SR_F ? t2 : t0;
}
 
__or_dynop void op_cmov_t2_t2_t1(void)
{
  t2 = env->sprs[SPR_SR] & SPR_SR_F ? t2 : t1;
}
 
__or_dynop void op_neg_t0_t0(void)
{
  t0 = -t0;
}
 
__or_dynop void op_neg_t0_t1(void)
{
  t0 = -t1;
}
 
__or_dynop void op_neg_t0_t2(void)
{
  t0 = -t2;
}
 
__or_dynop void op_neg_t1_t0(void)
{
  t1 = -t0;
}
 
__or_dynop void op_neg_t1_t1(void)
{
  t1 = -t1;
}
 
__or_dynop void op_neg_t1_t2(void)
{
  t1 = -t2;
}
 
__or_dynop void op_neg_t2_t0(void)
{
  t2 = -t0;
}
 
__or_dynop void op_neg_t2_t1(void)
{
  t2 = -t1;
}
 
__or_dynop void op_neg_t2_t2(void)
{
  t2 = -t2;
}
 

Line No.	Rev	Author	Line
1	1452	nogj	`/* op.c -- Micro operations for the recompiler`
2			Copyright (C) 2005 Gy�rgy `nog' Jeney, nog@sdf.lonestar.org
3
4			`This file is part of OpenRISC 1000 Architectural Simulator.`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License as published by`
8			`the Free Software Foundation; either version 2 of the License, or`
9			`(at your option) any later version.`
10
11			`This program is distributed in the hope that it will be useful,`
12			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`GNU General Public License for more details.`
15
16			`You should have received a copy of the GNU General Public License`
17			`along with this program; if not, write to the Free Software`
18			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */`
19
20
21			`#include <stdio.h>`
22			`#include <stdint.h>`
23			`#include <stdlib.h>`
24
25			`#include "config.h"`
26
27			`#ifdef HAVE_INTTYPES_H`
28			`#include <inttypes.h>`
29			`#endif`
30
31			`#include "port.h"`
32			`#include "arch.h"`
33			`#include "spr_defs.h"`
34			`#include "opcode/or32.h"`
35			`#include "sim-config.h"`
36			`#include "except.h"`
37			`#include "abstract.h"`
38			`#include "execute.h"`
39			`#include "sprs.h"`
40			`#include "sched.h"`
41
42			`#include "op_support.h"`
43
44			`#include "i386_regs.h"`
45
46			`#include "dyn_rec.h"`
47
48			`/* This must be here since the function in op_i386.h use this variable */`
49			`register struct cpu_state *env asm(CPU_STATE_REG);`
50
51			`#include "op_i386.h"`
52
53			`/*`
54	1549	nogj	`* WARNING: Before going of and wildly editing everything in this file remember`
55	1452	nogj	`* the following about its contents:`
56			* 1) The `functions' don't EVER return. In otherwords haveing return state-
57			`* ments _anywere_ in this file is likely not to work. This is because`
58			`* dyngen just strips away the ret from the end of the function and just uses`
59			* the function `body'. If a ret statement is executed _anyware_ inside the
60			`* dynamicly generated code, then it is undefined were we shall jump to.`
61			`* 2) Because of 1), try not to have overly complicated functions. In too`
62			* complicated functions, gcc may decide to generate premature `exits'. This
63			`* is what passing the -fno-reorder-blocks command line switch to gcc helps`
64			`* with. This is ofcourse not desired and is rather flaky as we don't (and`
65			`* can't) control the kind of code that gcc generates: It may work for one`
66			`* and break for another. The less branches there are the less likely it is`
67			`* that a premature return shall occur.`
68			`* 3) If gcc decides that it is going to be a basterd then it will optimise a`
69			`* very simple condition (if/switch) with a premature exit. But gcc can't`
70			`* fuck ME over! Just stick a FORCE_RET; at the END of the offending`
71			`* function.`
72			* 4) All operations must start with `op_'. dyngen ignores all other functions.
73			`* 5) Local variables are depriciated: They hinder performance.`
74			`* 6) Function calls are expensive as the stack has to be shifted (twice).`
75			`*/`
76
77			`/#define __or_dynop __attribute__((noreturn))/`
78			`#define __or_dynop`
79
80			`/* Temporaries to hold the (simulated) registers in */`
81			`register uint32_t t0 asm(T0_REG);`
82			`register uint32_t t1 asm(T1_REG);`
83			`register uint32_t t2 asm(T2_REG);`
84
85			`#define OP_PARAM1 ((uorreg_t)(&__op_param1))`
86			`#define OP_PARAM2 ((uorreg_t)(&__op_param2))`
87			`#define OP_PARAM3 ((uorreg_t)(&__op_param3))`
88
89			`extern uorreg_t __op_param1;`
90			`extern uorreg_t __op_param2;`
91			`extern uorreg_t __op_param3;`
92
93			`#define xglue(x, y) x ## y`
94			`#define glue(x, y) xglue(x, y)`
95
96			`/* Helper function. Whenever we escape the recompiled code and there is a`
97			`* potential that an exception may happen this function must be called */`
98			`static inline void save_t_temporary(void)`
99			`{`
100			`env->t0 = t0;`
101			`env->t1 = t1;`
102			`env->t2 = t2;`
103			`}`
104
105			`/* Wrapper around do_scheduler. This is needed because op_do_sched must be as`
106			`* small as possible. */`
107			`void do_sched_wrap(void)`
108			`{`
109			`save_t_temporary();`
110			`upd_sim_cycles();`
111			`do_scheduler();`
112			`}`
113
114	1481	nogj	`/* do_scheduler wrapper for instructions that are in the delay slot */`
115			`void do_sched_wrap_delay(void)`
116			`{`
117			`save_t_temporary();`
118			`upd_sim_cycles();`
119			`env->ts_current = 1;`
120			`/* The PC gets set to the location of the jump, but do_sched increments that`
121			`* so pull it back here to point to the right location again. This could be`
122			`* done in op_add_pc/op_set_pc_pc_delay but that would enlarge the recompiled`
123			`* code. */`
124			`//env->pc -= 4;`
125			`do_scheduler();`
126			`env->ts_current = 0;`
127			`}`
128
129			`void enter_dyn_code(oraddr_t addr, struct dyn_page *dp)`
130			`{`
131			`uint16_t reg;`
132
133	1483	nogj	`addr &= config.immu.pagesize - 1;`
134	1481	nogj	`addr >>= 2;`
135
136			`reg = dp->ts_bound[addr];`
137
138			`if(reg & 0x1f)`
139			`t0 = cpu_state.reg[reg & 0x1f];`
140
141			`if((reg >> 5) & 0x1f)`
142			`t1 = cpu_state.reg[(reg >> 5) & 0x1f];`
143
144			`if((reg >> 10) & 0x1f)`
145			`t2 = cpu_state.reg[(reg >> 10) & 0x1f];`
146
147			`or_longjmp(dp->locs[addr]);`
148			`}`
149
150	1452	nogj	`__or_dynop void op_t0_imm(void)`
151			`{`
152			`t0 = OP_PARAM1;`
153			`}`
154
155			`__or_dynop void op_t1_imm(void)`
156			`{`
157			`t1 = OP_PARAM1;`
158			`}`
159
160			`__or_dynop void op_t2_imm(void)`
161			`{`
162			`t2 = OP_PARAM1;`
163			`}`
164
165			`__or_dynop void op_clear_t0(void)`
166			`{`
167			`t0 = 0;`
168			`}`
169
170			`__or_dynop void op_clear_t1(void)`
171			`{`
172			`t1 = 0;`
173			`}`
174
175			`__or_dynop void op_clear_t2(void)`
176			`{`
177			`t2 = 0;`
178			`}`
179
180			`__or_dynop void op_move_t0_t1(void)`
181			`{`
182			`t0 = t1;`
183			`}`
184
185			`__or_dynop void op_move_t0_t2(void)`
186			`{`
187			`t0 = t2;`
188			`}`
189
190			`__or_dynop void op_move_t1_t0(void)`
191			`{`
192			`t1 = t0;`
193			`}`
194
195			`__or_dynop void op_move_t1_t2(void)`
196			`{`
197			`t1 = t2;`
198			`}`
199
200			`__or_dynop void op_move_t2_t0(void)`
201			`{`
202			`t2 = t0;`
203			`}`
204
205			`__or_dynop void op_move_t2_t1(void)`
206			`{`
207			`t2 = t1;`
208			`}`
209
210	1481	nogj	`__or_dynop void op_set_pc_pc_delay(void)`
211	1452	nogj	`{`
212	1481	nogj	`env->sprs[SPR_PPC] = get_pc();`
213			`/* pc_delay is pulled back 4 since imediatly after this is run, the scheduler`
214			`* runs which also increments it by 4 */`
215			`set_pc(env->pc_delay - 4);`
216	1452	nogj	`}`
217
218			`__or_dynop void op_set_pc_delay_imm(void)`
219			`{`
220			`env->pc_delay = get_pc() + (orreg_t)OP_PARAM1;`
221			`env->delay_insn = 1;`
222			`}`
223
224			`__or_dynop void op_set_pc_delay_pc(void)`
225			`{`
226			`env->pc_delay = get_pc();`
227			`env->delay_insn = 1;`
228			`}`
229
230			`__or_dynop void op_clear_pc_delay(void)`
231			`{`
232			`env->pc_delay = 0;`
233			`env->delay_insn = 1;`
234			`}`
235
236			`__or_dynop void op_do_jump(void)`
237			`{`
238	1481	nogj	`do_jump(get_pc());`
239			`}`
240
241			`__or_dynop void op_do_jump_delay(void)`
242			`{`
243	1452	nogj	`do_jump(env->pc_delay);`
244			`}`
245
246	1481	nogj	`__or_dynop void op_clear_delay_insn(void)`
247	1452	nogj	`{`
248	1481	nogj	`env->delay_insn = 0;`
249	1452	nogj	`}`
250
251	1481	nogj	`__or_dynop void op_set_delay_insn(void)`
252	1452	nogj	`{`
253	1481	nogj	`env->delay_insn = 1;`
254	1452	nogj	`}`
255
256	1481	nogj	`__or_dynop void op_check_delay_slot(void)`
257	1452	nogj	`{`
258	1481	nogj	`if(!env->delay_insn)`
259			`OP_JUMP(OP_PARAM1);`
260	1452	nogj	`}`
261
262			`__or_dynop void op_jmp_imm(void)`
263			`{`
264			`OP_JUMP(OP_PARAM1);`
265			`}`
266
267			`__or_dynop void op_set_flag(void)`
268			`{`
269			`env->sprs[SPR_SR] \|= SPR_SR_F;`
270			`}`
271
272			`__or_dynop void op_clear_flag(void)`
273			`{`
274			`env->sprs[SPR_SR] &= ~SPR_SR_F;`
275			`}`
276
277	1481	nogj	`/* Used for the l.bf instruction. Therefore if the flag is not set, jump over`
278			`* all the jumping stuff */`
279	1452	nogj	`__or_dynop void op_check_flag(void)`
280			`{`
281	1481	nogj	`if(!(env->sprs[SPR_SR] & SPR_SR_F)) {`
282			`HANDLE_SCHED(do_sched_wrap, "no_sched_chk_flg");`
283			`OP_JUMP(OP_PARAM1);`
284			`}`
285			`}`
286
287			`/* Used for l.bf if the delay slot instruction is on another page */`
288			`__or_dynop void op_check_flag_delay(void)`
289			`{`
290	1452	nogj	`if(env->sprs[SPR_SR] & SPR_SR_F) {`
291	1481	nogj	`env->delay_insn = 1;`
292	1452	nogj	`env->pc_delay = get_pc() + (orreg_t)OP_PARAM1;`
293			`}`
294			`}`
295
296	1481	nogj	`/* Used for the l.bnf instruction. Therefore if the flag is set, jump over all`
297			`* the jumping stuff */`
298	1452	nogj	`__or_dynop void op_check_not_flag(void)`
299			`{`
300	1481	nogj	`if(env->sprs[SPR_SR] & SPR_SR_F) {`
301			`HANDLE_SCHED(do_sched_wrap, "no_sched_chk_not_flg");`
302			`OP_JUMP(OP_PARAM1);`
303			`}`
304			`}`
305
306			`/* Used for l.bnf if the delay slot instruction is on another page */`
307			`__or_dynop void op_check_not_flag_delay(void)`
308			`{`
309	1452	nogj	`if(!(env->sprs[SPR_SR] & SPR_SR_F)) {`
310	1481	nogj	`env->delay_insn = 1;`
311	1452	nogj	`env->pc_delay = get_pc() + (orreg_t)OP_PARAM1;`
312			`}`
313			`}`
314
315			`__or_dynop void op_set_ts_current(void)`
316			`{`
317			`env->ts_current = 1;`
318			`}`
319
320	1481	nogj	`__or_dynop void op_add_pc(void)`
321	1452	nogj	`{`
322	1481	nogj	`/* FIXME: Optimise */`
323			`set_pc(get_pc() + OP_PARAM1);`
324	1452	nogj	`}`
325
326			`__or_dynop void op_nop_exit(void)`
327			`{`
328			`upd_sim_cycles();`
329			`save_t_temporary();`
330			`op_support_nop_exit();`
331			`FORCE_RET;`
332			`}`
333
334			`__or_dynop void op_nop_reset(void)`
335			`{`
336			`upd_sim_cycles();`
337			`op_support_nop_reset();`
338	1481	nogj	`do_jump(EXCEPT_RESET);`
339	1452	nogj	`}`
340
341			`__or_dynop void op_nop_printf(void)`
342			`{`
343			`save_t_temporary();`
344			`upd_sim_cycles();`
345			`op_support_nop_printf();`
346			`FORCE_RET;`
347			`}`
348
349			`__or_dynop void op_nop_report(void)`
350			`{`
351			`save_t_temporary();`
352			`upd_sim_cycles();`
353			`op_support_nop_report();`
354			`FORCE_RET;`
355			`}`
356
357			`__or_dynop void op_nop_report_imm(void)`
358			`{`
359			`save_t_temporary();`
360			`upd_sim_cycles();`
361			`op_support_nop_report_imm(OP_PARAM1);`
362			`}`
363
364			`__or_dynop void op_check_null_except_t0_delay(void)`
365			`{`
366			`if(!t0) {`
367			`/* Do exception */`
368			`env->sprs[SPR_EEAR_BASE] = get_pc() - 4;`
369			`env->delay_insn = 0;`
370	1481	nogj	`do_jump(EXCEPT_ILLEGAL);`
371	1452	nogj	`}`
372			`}`
373
374
375			`__or_dynop void op_check_null_except_t0(void)`
376			`{`
377			`if(!t0) {`
378			`/* Do exception */`
379			`env->sprs[SPR_EEAR_BASE] = get_pc();`
380	1481	nogj	`do_jump(EXCEPT_ILLEGAL);`
381	1452	nogj	`}`
382			`}`
383
384			`__or_dynop void op_check_null_except_t1_delay(void)`
385			`{`
386			`if(!t1) {`
387			`/* Do exception */`
388			`env->sprs[SPR_EEAR_BASE] = get_pc() - 4;`
389			`env->delay_insn = 0;`
390	1481	nogj	`do_jump(EXCEPT_ILLEGAL);`
391	1452	nogj	`}`
392			`}`
393
394
395			`__or_dynop void op_check_null_except_t1(void)`
396			`{`
397			`if(!t1) {`
398			`/* Do exception */`
399			`env->sprs[SPR_EEAR_BASE] = get_pc();`
400	1481	nogj	`do_jump(EXCEPT_ILLEGAL);`
401	1452	nogj	`}`
402			`}`
403
404			`__or_dynop void op_check_null_except_t2_delay(void)`
405			`{`
406			`if(!t2) {`
407			`/* Do exception */`
408			`env->sprs[SPR_EEAR_BASE] = get_pc() - 4;`
409			`env->delay_insn = 0;`
410	1481	nogj	`do_jump(EXCEPT_ILLEGAL);`
411	1452	nogj	`}`
412			`}`
413
414			`__or_dynop void op_check_null_except_t2(void)`
415			`{`
416			`if(!t2) {`
417			`/* Do exception */`
418			`env->sprs[SPR_EEAR_BASE] = get_pc();`
419	1481	nogj	`do_jump(EXCEPT_ILLEGAL);`
420	1452	nogj	`}`
421			`}`
422
423			`__or_dynop void op_analysis(void)`
424			`{`
425			`env->iqueue.insn_index = OP_PARAM1;`
426			`env->iqueue.insn = OP_PARAM2;`
427			`env->iqueue.insn_addr = get_pc();`
428	1481	nogj	`save_t_temporary();`
429			`op_support_analysis();`
430	1452	nogj	`FORCE_RET;`
431			`}`
432
433			`#define OP_EXTRA`
434
435			`#define OP /`
436			`#define OP_CAST(T) (orreg_t)T`
437			`#define OP_NAME div`
438			`#include "op_arith_op.h"`
439			`#undef OP_NAME`
440			`#undef OP_CAST`
441			`#undef OP`
442
443			`#define OP /`
444			`#define OP_CAST(T) T`
445			`#define OP_NAME divu`
446			`#include "op_arith_op.h"`
447			`#undef OP_NAME`
448			`#undef OP_CAST`
449			`#undef OP`
450
451			`#define OP *`
452			`#define OP_CAST(T) T`
453			`#define OP_NAME mulu`
454			`#include "op_arith_op.h"`
455			`#undef OP_NAME`
456			`#undef OP_CAST`
457			`#undef OP`
458
459			`#define OP -`
460			`#define OP_CAST(T) (orreg_t)T`
461			`#define OP_NAME sub`
462			`#include "op_arith_op.h"`
463			`#undef OP_NAME`
464			`#undef OP_CAST`
465			`#undef OP`
466
467			`#undef OP_EXTRA`
468
469			`#define OP_HAS_IMM`
470
471			`#define OP_EXTRA + ((env->sprs[SPR_SR] & SPR_SR_CY) >> 10)`
472			`#define OP +`
473			`#define OP_CAST(T) (orreg_t)T`
474			`#define OP_NAME addc`
475			`#include "op_arith_op.h"`
476			`#undef OP_NAME`
477			`#undef OP_CAST`
478			`#undef OP`
479
480			`#undef OP_EXTRA`
481			`#define OP_EXTRA`
482
483			`#define OP +`
484			`#define OP_CAST(T) (orreg_t)T`
485			`#define OP_NAME add`
486			`#include "op_arith_op.h"`
487			`#undef OP_NAME`
488			`#undef OP_CAST`
489			`#undef OP`
490
491			`#define OP &`
492			`#define OP_CAST(T) T`
493			`#define OP_NAME and`
494			`#include "op_arith_op.h"`
495			`#undef OP_NAME`
496			`#undef OP_CAST`
497			`#undef OP`
498
499			`#define OP *`
500			`#define OP_CAST(T) (orreg_t)T`

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[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [cpu/] [or32/] [op.c] - Blame information for rev 1765