OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [peripheral/] [eth.c] - Blame information for rev 1359

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 696 ivang 
/* ethernet.c -- Simulation of Ethernet MAC
2 
   Copyright (C) 2001 by Erez Volk, erez@opencores.org
3 
                         Ivan Guzvinec, ivang@opencores.org
4 
 
5 
   This file is part of OpenRISC 1000 Architectural Simulator.
6 
 
7 
   This program is free software; you can redistribute it and/or modify
8 
   it under the terms of the GNU General Public License as published by
9 
   the Free Software Foundation; either version 2 of the License, or
10 
   (at your option) any later version.
11 
 
12 
   This program is distributed in the hope that it will be useful,
13 
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14 
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 
   GNU General Public License for more details.
16 
 
17 
   You should have received a copy of the GNU General Public License
18 
   along with this program; if not, write to the Free Software
19 
   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 
*/
21 
 
22 
#include <stdlib.h>
23 
#include <stdio.h>
24 
#include <string.h>
25 
#include <sys/types.h>
26 
#include <sys/stat.h>
27 
#include <fcntl.h>
28 
#include <sys/poll.h>
29 
#include <sys/time.h>
30 
#include <unistd.h>
31 
#include <errno.h>
32 1308 phoenix 
#include <netinet/in.h>
33 696 ivang 
 
34 867 markom 
#include "config.h"
35 1350 nogj 
 
36 
#ifdef HAVE_INTTYPES_H
37 
#include <inttypes.h>
38 
#endif
39 
 
40 
#include "port.h"
41 
#include "arch.h"
42 
#include "config.h"
43 696 ivang 
#include "abstract.h"
44 
#include "ethernet_i.h"
45 
#include "dma.h"
46 
#include "sim-config.h"
47 
#include "fields.h"
48 
#include "crc32.h"
49 889 ivang 
#include "vapi.h"
50 1308 phoenix 
#include "pic.h"
51 
#include "debug.h"
52 696 ivang 
 
53 
static struct eth_device eths[MAX_ETHERNETS];
54 
 
55 702 ivang 
/* simulator interface */
56 
static void eth_reset_controller( struct eth_device *eth);
57 889 ivang 
static void eth_vapi_read( unsigned long id, unsigned long data);
58 696 ivang 
/* register interface */
59 1359 nogj 
static void eth_write32( oraddr_t addr, uint32_t value, void *dat );
60 
static uint32_t eth_read32( oraddr_t addr, void *dat );
61 696 ivang 
/* clock */
62 
static void eth_controller_tx_clock( struct eth_device * );
63 
static void eth_controller_rx_clock( struct eth_device * );
64 
/* utility functions */
65 1350 nogj 
static int eth_find_controller( oraddr_t addr, struct eth_device **eth, oraddr_t *reladdr );
66 1244 hpanther 
struct eth_device *eth_find_vapi_device (unsigned long id, unsigned long *which);
67 702 ivang 
static ssize_t eth_read_rx_file( struct eth_device *, void *, size_t );
68 
static void eth_skip_rx_file( struct eth_device *, off_t );
69 
static void eth_rewind_rx_file( struct eth_device *, off_t );
70 
static void eth_rx_next_packet( struct eth_device * );
71 
static void eth_write_tx_bd_num( struct eth_device *, unsigned long value );
72 696 ivang 
/* ========================================================================= */
73 702 ivang 
/*  TX LOGIC                                                                 */
74 696 ivang 
/*---------------------------------------------------------------------------*/
75 
 
76 
/*
77 
 * TX clock
78 
 * Responsible for starting and finishing TX
79 
 */
80 
void eth_controller_tx_clock( struct eth_device *eth )
81 
{
82 702 ivang 
    int breakpoint = 0;
83 
    int bAdvance   = 1;
84 867 markom 
#if HAVE_ETH_PHY
85 702 ivang 
    struct sockaddr_ll sll;
86 849 markom 
#endif /* HAVE_ETH_PHY */
87 702 ivang 
    long nwritten;
88 
    unsigned long read_word;
89 696 ivang 
 
90 
    switch (eth->tx.state) {
91 702 ivang 
        case ETH_TXSTATE_IDLE:
92 
        if ( TEST_FLAG( eth->regs.moder, ETH_MODER, TXEN ) ) {
93 
 
94 
            /* wait for TxBuffer to be ready */
95 1350 nogj 
                debug (3, "TX - entering state WAIT4BD (%ld)\n", eth->tx.bd_index);
96 702 ivang 
            eth->tx.state = ETH_TXSTATE_WAIT4BD;
97 
        }
98 
        break;
99 696 ivang 
    case ETH_TXSTATE_WAIT4BD:
100 702 ivang 
        /* Read buffer descriptor */
101 
        eth->tx.bd = eth->regs.bd_ram[eth->tx.bd_index];
102 
        eth->tx.bd_addr = eth->regs.bd_ram[eth->tx.bd_index + 1];
103 
 
104 
        if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, READY ) ) {
105 
            /*****************/
106 
            /* initialize TX */
107 
            eth->tx.bytes_left = eth->tx.packet_length = GET_FIELD( eth->tx.bd, ETH_TX_BD, LENGTH );
108 
            eth->tx.bytes_sent = 0;
109 
 
110 
            /*   Initialize error status bits */
111 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, DEFER );
112 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, COLLISION );
113 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, RETRANSMIT );
114 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, UNDERRUN );
115 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, NO_CARRIER );
116 
            SET_FIELD ( eth->tx.bd, ETH_TX_BD, RETRY, 0 );
117 
 
118 
            /* Find out minimum length */
119 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, PAD ) ||
120 
                 TEST_FLAG( eth->regs.moder, ETH_MODER, PAD ) )
121 
                eth->tx.minimum_length = GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL );
122 
            else
123 
                eth->tx.minimum_length = eth->tx.packet_length;
124 
 
125 
            /* Find out maximum length */
126 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, HUGEN ) )
127 
                eth->tx.maximum_length = eth->tx.packet_length;
128 
            else
129 
                eth->tx.maximum_length = GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL );
130 
 
131 
            /* Do we need CRC on this packet? */
132 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, CRCEN ) ||
133 
                 (TEST_FLAG( eth->tx.bd, ETH_TX_BD, CRC) &&
134 
                  TEST_FLAG( eth->tx.bd, ETH_TX_BD, LAST)) )
135 
                eth->tx.add_crc = 1;
136 
            else
137 
                eth->tx.add_crc = 0;
138 
 
139 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, DLYCRCEN ) )
140 
                eth->tx.crc_dly = 1;
141 
            else
142 
                eth->tx.crc_dly = 0;
143 
            /* XXX - For now we skip CRC calculation */
144 
 
145 1350 nogj 
            debug( 3, "Ethernet: Starting TX of %lu bytes (min. %u, max. %u)\n",
146 
                   eth->tx.packet_length, eth->tx.minimum_length,
147 
                   eth->tx.maximum_length );
148 702 ivang 
 
149 
            if (eth->rtx_type == ETH_RTX_FILE) {
150 
                /* write packet length to file */
151 
                nwritten = write( eth->txfd, &(eth->tx.packet_length), sizeof(eth->tx.packet_length) );
152 
            }
153 
 
154 
            /************************************************/
155 
            /* start transmit with reading packet into FIFO */
156 
                debug (3, "TX - entering state READFIFO\n");
157 
            eth->tx.state = ETH_TXSTATE_READFIFO;
158 
        }
159 
        else if ( !TEST_FLAG( eth->regs.moder, ETH_MODER, TXEN ) ) {
160 
            /* stop TX logic */
161 
                debug (3, "TX - entering state IDLE\n");
162 
            eth->tx.state = ETH_TXSTATE_IDLE;
163 
        }
164 
 
165 
        /* stay in this state if (TXEN && !READY) */
166 
        break;
167 696 ivang 
    case ETH_TXSTATE_READFIFO:
168 744 simons 
#if 1
169 702 ivang 
        if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
170 1241 phoenix 
            read_word = eval_direct32(eth->tx.bytes_sent + eth->tx.bd_addr, &breakpoint, 0, 0);
171 702 ivang 
            eth->tx_buff[eth->tx.bytes_sent]   = (unsigned char)(read_word >> 24);
172 
            eth->tx_buff[eth->tx.bytes_sent+1] = (unsigned char)(read_word >> 16);
173 
            eth->tx_buff[eth->tx.bytes_sent+2] = (unsigned char)(read_word >> 8);
174 
            eth->tx_buff[eth->tx.bytes_sent+3] = (unsigned char)(read_word);
175 
            eth->tx.bytes_sent += 4;
176 
        }
177 744 simons 
#else
178 
        if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
179 1241 phoenix 
            eth->tx_buff[eth->tx.bytes_sent] = eval_direct8(eth->tx.bytes_sent + eth->tx.bd_addr, &breakpoint, 0, 0);
180 744 simons 
            eth->tx.bytes_sent += 1;
181 
        }
182 
#endif
183 702 ivang 
        else {
184 
            debug (3, "TX - entering state TRANSMIT\n");
185 
            eth->tx.state = ETH_TXSTATE_TRANSMIT;
186 
        }
187 
        break;
188 696 ivang 
    case ETH_TXSTATE_TRANSMIT:
189 702 ivang 
        /* send packet */
190 
        switch (eth->rtx_type) {
191 
        case ETH_RTX_FILE:
192 
            nwritten = write( eth->txfd, eth->tx_buff, eth->tx.packet_length );
193 
            break;
194 867 markom 
#if HAVE_ETH_PHY
195 702 ivang 
        case ETH_RTX_SOCK:
196 
            memset(&sll, 0, sizeof(sll));
197 705 ivang 
            sll.sll_ifindex = eth->ifr.ifr_ifindex;
198 
            nwritten = sendto(eth->rtx_sock, eth->tx_buff, eth->tx.packet_length, 0, (struct sockaddr *)&sll, sizeof(sll));
199 849 markom 
#endif /* HAVE_ETH_PHY */
200 702 ivang 
        }
201 
 
202 
        /* set BD status */
203 
        if (nwritten == eth->tx.packet_length) {
204 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
205 
            SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXB);
206 1350 nogj 
            debug (4, "ETH_INT_SOURCE = %0lx\n", eth->regs.int_source);
207 702 ivang 
 
208 705 ivang 
            debug (3, "TX - entering state IDLE\n");
209 702 ivang 
            eth->tx.state = ETH_TXSTATE_IDLE;
210 1350 nogj 
            debug (3, "send (%ld)bytes OK\n", nwritten);
211 702 ivang 
        }
212 
        else {
213 
            /* XXX - implement retry mechanism here! */
214 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
215 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, COLLISION);
216 
            SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXE);
217 1350 nogj 
            debug (4, "ETH_INT_SOURCE = %0lx\n", eth->regs.int_source);
218 702 ivang 
 
219 889 ivang 
            debug (3, "TX - entering state IDLE\n");
220 702 ivang 
            eth->tx.state = ETH_TXSTATE_IDLE;
221 
            debug (3, "send FAILED!\n");
222 
        }
223 
 
224 
        eth->regs.bd_ram[eth->tx.bd_index] = eth->tx.bd;
225 
 
226 889 ivang 
        /* generate OK interrupt */
227 
        if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, TXE_M) ||
228 
             TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, TXB_M) )
229 
        {
230 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, IRQ ) )
231 
                report_interrupt( eth->mac_int );
232 
        }
233 
 
234 702 ivang 
        /* advance to next BD */
235 
        if (bAdvance) {
236 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, WRAP ) ||
237 
                            eth->tx.bd_index >= ETH_BD_COUNT )
238 
                eth->tx.bd_index = 0;
239 
            else
240 
                eth->tx.bd_index += 2;
241 
        }
242 
 
243 
        break;
244 696 ivang 
    }
245 
}
246 
/* ========================================================================= */
247 
 
248 
 
249 
/* ========================================================================= */
250 702 ivang 
/*  RX LOGIC                                                                 */
251 696 ivang 
/*---------------------------------------------------------------------------*/
252 
 
253 
/*
254 
 * RX clock
255 
 * Responsible for starting and finishing RX
256 
 */
257 
void eth_controller_rx_clock( struct eth_device *eth )
258 
{
259 702 ivang 
    int breakpoint = 0;
260 
    long nread;
261 
    unsigned long send_word;
262 
 
263 
 
264 696 ivang 
    switch (eth->rx.state) {
265 
    case ETH_RXSTATE_IDLE:
266 702 ivang 
        if ( TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN) ) {
267 1350 nogj 
                debug (3, "RX - entering state WAIT4BD (%ld)\n", eth->rx.bd_index);
268 702 ivang 
            eth->rx.state = ETH_RXSTATE_WAIT4BD;
269 
        }
270 
        break;
271 
 
272 696 ivang 
    case ETH_RXSTATE_WAIT4BD:
273 702 ivang 
        eth->rx.bd = eth->regs.bd_ram[eth->rx.bd_index];
274 
        eth->rx.bd_addr = eth->regs.bd_ram[eth->rx.bd_index + 1];
275 
 
276 
        if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, READY ) ) {
277 
            /*****************/
278 
            /* Initialize RX */
279 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, MISS );
280 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, INVALID );
281 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, DRIBBLE );
282 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, UVERRUN );
283 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, COLLISION );
284 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG );
285 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT );
286 
 
287 
            debug( 3,  "Ethernet: Starting RX\n" );
288 
 
289 
            /* Setup file to read from */
290 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, LOOPBCK ) ) {
291 
                eth->rx.fd = eth->txfd;
292 
                eth->rx.offset = &(eth->loopback_offset);
293 
            } else {
294 
                eth->rx.fd = eth->rxfd;
295 
                eth->rx.offset = 0;
296 
            }
297 889 ivang 
            debug (3, "RX - entering state RECV\n");
298 702 ivang 
            eth->rx.state = ETH_RXSTATE_RECV;
299 
        }
300 705 ivang 
        else if (!TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN)) {
301 
          debug (3, "RX - entering state IDLE\n");
302 
          eth->rx.state = ETH_RXSTATE_IDLE;
303 
        }
304 
        else {
305 744 simons 
            nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, /*MSG_PEEK | */MSG_DONTWAIT);
306 705 ivang 
            if (nread > 0) {
307 702 ivang 
                SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, BUSY);
308 723 ivang 
                if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, BUSY_M) )
309 
                  report_interrupt(eth->mac_int);
310 702 ivang 
            }
311 
        }
312 
        break;
313 
 
314 696 ivang 
    case ETH_RXSTATE_RECV:
315 702 ivang 
        switch (eth->rtx_type) {
316 
        case ETH_RTX_FILE:
317 
            /* Read packet length */
318 
            if ( eth_read_rx_file( eth, &(eth->rx.packet_length), sizeof(eth->rx.packet_length) )
319 
                     < sizeof(eth->rx.packet_length) ) {
320 
                /* TODO: just do what real ethernet would do (some kind of error state) */
321 1350 nogj 
                debug (4, "eth_start_rx(): File does not have a packet ready for RX (len = %ld)\n", eth->rx.packet_length );
322 884 markom 
                runtime.sim.cont_run = 0;
323 702 ivang 
                break;
324 
            }
325 
 
326 
            /* Packet must be big enough to hold a header */
327 1244 hpanther 
            if ( eth->rx.packet_length < ETHER_HDR_LEN ){
328 702 ivang 
                debug( 3,  "eth_start_rx(): Packet too small\n" );
329 
                eth_rx_next_packet( eth );
330 
 
331 836 ivang 
                debug (3, "RX - entering state IDLE\n");
332 702 ivang 
                eth->rx.state = ETH_RXSTATE_IDLE;
333 
                break;
334 
            }
335 
 
336 
            eth->rx.bytes_read = 0;
337 
            eth->rx.bytes_left = eth->rx.packet_length;
338 
 
339 
            /* for now Read entire packet into memory */
340 
            nread = eth_read_rx_file( eth, eth->rx_buff, eth->rx.bytes_left );
341 844 ivang 
            if ( nread < eth->rx.bytes_left ) {
342 1350 nogj 
                debug (3, "Read %ld from %ld. Error!\n", nread, eth->rx.bytes_left);
343 844 ivang 
                eth->rx.error = 1;
344 
                break;
345 
            }
346 
 
347 
            eth->rx.packet_length = nread;
348 
            eth->rx.bytes_left = nread;
349 
            eth->rx.bytes_read = 0;
350 
 
351 
            debug (3, "RX - entering state WRITEFIFO\n");
352 
            eth->rx.state = ETH_RXSTATE_WRITEFIFO;
353 
 
354 702 ivang 
            break;
355 
 
356 
        case ETH_RTX_SOCK:
357 
            nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, MSG_DONTWAIT);
358 744 simons 
 
359 
            if (nread == 0)
360 
                break;
361 
            else if (nread < 0) {
362 
                if ( errno != EAGAIN ) {
363 889 ivang 
                    debug (3, "recv() FAILED!\n");
364 
                    break;
365 
                }
366 
                else break;
367 
            }
368 744 simons 
            /* If not promiscouos mode, check the destination address */
369 
            if (!TEST_FLAG(eth->regs.moder, ETH_MODER, PRO)) {
370 
                if (TEST_FLAG(eth->regs.moder, ETH_MODER, IAM) && (eth->rx_buff[0] & 1)) {
371 
                /* Nothing for now */
372 
                }
373 
 
374 
                if (eth->mac_address[5] != eth->rx_buff[0] ||
375 
                    eth->mac_address[4] != eth->rx_buff[1] ||
376 
                    eth->mac_address[3] != eth->rx_buff[2] ||
377 
                    eth->mac_address[2] != eth->rx_buff[3] ||
378 
                    eth->mac_address[1] != eth->rx_buff[4] ||
379 
                    eth->mac_address[0] != eth->rx_buff[5])
380 889 ivang 
                    break;
381 744 simons 
            }
382 
 
383 841 simons 
            eth->rx.packet_length = nread;
384 
            eth->rx.bytes_left = nread;
385 
            eth->rx.bytes_read = 0;
386 
 
387 
            debug (3, "RX - entering state WRITEFIFO\n");
388 
            eth->rx.state = ETH_RXSTATE_WRITEFIFO;
389 
 
390 702 ivang 
            break;
391 889 ivang 
        case ETH_RTX_VAPI:
392 1332 phoenix 
          break;
393 702 ivang 
        }
394 841 simons 
        break;
395 
 
396 696 ivang 
    case ETH_RXSTATE_WRITEFIFO:
397 744 simons 
#if 1
398 702 ivang 
        send_word = ((unsigned long)eth->rx_buff[eth->rx.bytes_read]   << 24) |
399 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+1] << 16) |
400 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+2] << 8)  |
401 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+3] );
402 1241 phoenix 
        set_direct32( eth->rx.bd_addr + eth->rx.bytes_read, send_word, &breakpoint, 0, 0);
403 702 ivang 
        /* update counters */
404 1350 nogj 
        debug (3, "Write %ld, left %ld - %08lXd\n", eth->rx.bytes_read,
405 
               eth->rx.bytes_left, send_word);
406 702 ivang 
        eth->rx.bytes_left -= 4;
407 
        eth->rx.bytes_read += 4;
408 744 simons 
#else
409 1241 phoenix 
        set_direct8( eth->rx.bd_addr + eth->rx.bytes_read, eth->rx_buff[eth->rx.bytes_read], &breakpoint, 0, 0);
410 744 simons 
        eth->rx.bytes_left -= 1;
411 
        eth->rx.bytes_read += 1;
412 
#endif
413 
 
414 702 ivang 
        if ( eth->rx.bytes_left <= 0 ) {
415 
            /* Write result to bd */
416 
            SET_FIELD( eth->rx.bd, ETH_RX_BD, LENGTH, eth->rx.packet_length );
417 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, READY);
418 705 ivang 
            SET_FLAG( eth->regs.int_source, ETH_INT_SOURCE, RXB);
419 1350 nogj 
            debug (4, "ETH_INT_SOURCE = %0lx\n", eth->regs.int_source);
420 702 ivang 
 
421 1068 simons 
            if ( eth->rx.packet_length < (GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL ) - 4) )
422 744 simons 
                SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT);
423 
            if ( eth->rx.packet_length > GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL ) )
424 702 ivang 
                SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG);
425 
 
426 
            eth->regs.bd_ram[eth->rx.bd_index] = eth->rx.bd;
427 
 
428 
            /* advance to next BD */
429 
            if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, WRAP ) || eth->rx.bd_index >= ETH_BD_COUNT )
430 1018 simons 
                eth->rx.bd_index = eth->regs.tx_bd_num << 1;
431 702 ivang 
            else
432 705 ivang 
                eth->rx.bd_index += 2;
433 702 ivang 
 
434 889 ivang 
            if ( ( TEST_FLAG( eth->regs.int_mask, ETH_INT_MASK, RXB_M ) ) &&
435 
                 ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, IRQ )              ) ) {
436 702 ivang 
                report_interrupt( eth->mac_int );
437 
            }
438 
 
439 
            /* ready to receive next packet */
440 
                debug (3, "RX - entering state IDLE\n");
441 
            eth->rx.state = ETH_RXSTATE_IDLE;
442 
        }
443 
        break;
444 696 ivang 
    }
445 
}
446 702 ivang 
 
447 696 ivang 
/* ========================================================================= */
448 702 ivang 
/* Move to next RX BD */
449 
void eth_rx_next_packet( struct eth_device *eth )
450 
{
451 
    /* Skip any possible leftovers */
452 
    if ( eth->rx.bytes_left )
453 
        eth_skip_rx_file( eth, eth->rx.bytes_left );
454 
}
455 
/* "Skip" bytes in RX file */
456 
void eth_skip_rx_file( struct eth_device *eth, off_t count )
457 
{
458 
    eth->rx.offset += count;
459 
}
460 696 ivang 
 
461 702 ivang 
/* Move RX file position back */
462 
void eth_rewind_rx_file( struct eth_device *eth, off_t count )
463 
{
464 
    eth->rx.offset -= count;
465 
}
466 
/*
467 
 * Utility function to read from the ethernet RX file
468 
 * This function moves the file pointer to the current place in the packet before reading
469 
 */
470 
ssize_t eth_read_rx_file( struct eth_device *eth, void *buf, size_t count )
471 
{
472 
    ssize_t result;
473 
 
474 
    if ( eth->rx.fd <= 0 ) {
475 
        debug( 3,  "Ethernet: No RX file\n" );
476 
        return 0;
477 
    }
478 
 
479 
    if ( eth->rx.offset )
480 
        if ( lseek( eth->rx.fd, *(eth->rx.offset), SEEK_SET ) == (off_t)-1 ) {
481 
            debug( 3,  "Ethernet: Error seeking RX file\n" );
482 
            return 0;
483 
        }
484 696 ivang 
 
485 702 ivang 
    result = read( eth->rx.fd, buf, count );
486 836 ivang 
    debug (4, "Ethernet: read result = %d \n", result);
487 702 ivang 
    if ( eth->rx.offset && result >= 0 )
488 
        *(eth->rx.offset) += result;
489 
 
490 
    return result;
491 
}
492 
 
493 
/* ========================================================================= */
494 
 
495 696 ivang 
/*
496 702 ivang 
  Reset. Initializes all registers to default and places devices in
497 
         memory address space.
498 696 ivang 
*/
499 
void eth_reset()
500 
{
501 
    static int first_time = 1;
502 
    unsigned i;
503 
 
504 
    if (!config.nethernets)
505 702 ivang 
        return;
506 696 ivang 
 
507 841 simons 
    if ( first_time )
508 702 ivang 
        memset( eths, 0, sizeof(eths) );
509 696 ivang 
 
510 
    for ( i = 0; i < MAX_ETHERNETS; ++ i ) {
511 702 ivang 
        struct eth_device *eth = &(eths[i]);
512 
 
513 849 markom 
        if (!HAVE_ETH_PHY && eth->rtx_type == ETH_RTX_SOCK) {
514 
          fprintf (stderr, "Ethernet phy not enabled in this configuration.  Configure with --enable-ethphy.\n");
515 
          exit (1);
516 
        }
517 702 ivang 
        eth->eth_number = i;
518 
        eth_reset_controller( eth );
519 841 simons 
        if ( eth->baseaddr && first_time )
520 1359 nogj 
            register_memoryarea( eth->baseaddr, ETH_ADDR_SPACE, 4, 0, eth_read32, eth_write32, NULL );
521 696 ivang 
    }
522 841 simons 
 
523 
    if ( first_time )
524 
        first_time = 0;
525 696 ivang 
}
526 841 simons 
 
527 696 ivang 
/* ========================================================================= */
528 
 
529 
 
530 702 ivang 
static void eth_reset_controller(struct eth_device *eth)
531 
{
532 
    int i = eth->eth_number;
533 1308 phoenix 
#if HAVE_ETH_PHY
534 702 ivang 
    int j;
535 
    struct sockaddr_ll sll;
536 849 markom 
#endif /* HAVE_ETH_PHY */
537 702 ivang 
 
538 
    eth->baseaddr = config.ethernets[i].baseaddr;
539 
 
540 
    if ( eth->baseaddr != 0 ) {
541 
        /* Mark which DMA controller and channels */
542 
        eth->dma        = config.ethernets[i].dma;
543 725 ivang 
        eth->mac_int    = config.ethernets[i].irq;
544 702 ivang 
        eth->tx_channel = config.ethernets[i].tx_channel;
545 
        eth->rx_channel = config.ethernets[i].rx_channel;
546 725 ivang 
        eth->rtx_type   = config.ethernets[i].rtx_type;
547 702 ivang 
 
548 
        switch (eth->rtx_type) {
549 
        case ETH_RTX_FILE:
550 
            /* (Re-)open TX/RX files */
551 
            eth->rxfile = config.ethernets[i].rxfile;
552 
            eth->txfile = config.ethernets[i].txfile;
553 
 
554 
            if ( eth->rxfd > 0 )
555 
                close( eth->rxfd );
556 
            if ( eth->txfd > 0 )
557 
                close( eth->txfd );
558 
            eth->rxfd = eth->txfd = -1;
559 
 
560 
            if ( (eth->rxfd = open( eth->rxfile, O_RDONLY )) < 0 )
561 
                fprintf( stderr, "Cannot open Ethernet RX file \"%s\"\n", eth->rxfile );
562 
            if ( (eth->txfd = open( eth->txfile,
563 1244 hpanther 
                                    O_RDWR | O_CREAT | O_APPEND
564 
 
565 
#if defined(O_SYNC)     /* BSD / Mac OS X manual doesn't know about O_SYNC */
566 
                                                                        | O_SYNC
567 
#endif
568 
                                                                        ,
569 702 ivang 
                                    S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH )) < 0 )
570 
                fprintf( stderr, "Cannot open Ethernet TX file \"%s\"\n", eth->txfile );
571 
            eth->loopback_offset = lseek( eth->txfd, 0, SEEK_END );
572 
 
573 
            break;
574 867 markom 
#if HAVE_ETH_PHY
575 702 ivang 
        case ETH_RTX_SOCK:
576 
            /* (Re-)open TX/RX sockets */
577 
            if (eth->rtx_sock != 0)
578 
                break;
579 
 
580 
            debug (3, "RTX oppening socket...\n");
581 
            eth->rtx_sock = socket(PF_PACKET, SOCK_RAW, htons(ETH_P_ALL));
582 
            if (eth->rtx_sock == -1) {
583 
                fprintf( stderr, "Cannot open rtx_sock.\n");
584 
                return;
585 
            }
586 
 
587 
            /* get interface index number */
588 
            debug (3, "RTX getting interface...\n");
589 
            memset(&(eth->ifr), 0, sizeof(eth->ifr));
590 725 ivang 
            strncpy(eth->ifr.ifr_name, config.ethernets[i].sockif, IFNAMSIZ);
591 702 ivang 
            if (ioctl(eth->rtx_sock, SIOCGIFINDEX, &(eth->ifr)) == -1) {
592 
                fprintf( stderr, "SIOCGIFINDEX failed!\n");
593 
                return;
594 
            }
595 
            debug (3, "RTX Socket Interface : %d\n", eth->ifr.ifr_ifindex);
596 
 
597 
            /* Bind to interface... */
598 
            debug (3, "Binding to the interface ifindex=%d\n", eth->ifr.ifr_ifindex);
599 
            memset(&sll, 0xff, sizeof(sll));
600 
            sll.sll_family = AF_PACKET;    /* allways AF_PACKET */
601 
            sll.sll_protocol = htons(ETH_P_ALL);
602 
            sll.sll_ifindex = eth->ifr.ifr_ifindex;
603 
            if (bind(eth->rtx_sock, (struct sockaddr *)&sll, sizeof(sll)) == -1) {
604 
                fprintf( stderr, "Error bind().\n");
605 
                return;
606 
            }
607 
 
608 
            /* first, flush all received packets. */
609 
            debug (3, "Flush");
610 
            do {
611 
                fd_set fds;
612 
                struct timeval t;
613 
 
614 
                debug( 3, ".");
615 
                FD_ZERO(&fds);
616 
                FD_SET(eth->rtx_sock, &fds);
617 
                memset(&t, 0, sizeof(t));
618 
                j = select(FD_SETSIZE, &fds, NULL, NULL, &t);
619 
                if (j > 0)
620 
                    recv(eth->rtx_sock, eth->rx_buff, j, 0);
621 
            } while (j);
622 
            debug (3, "\n");
623 
 
624 
            break;
625 849 markom 
#endif /* HAVE_ETH_PHY */
626 702 ivang 
        }
627 
 
628 
        /* Set registers to default values */
629 
        memset( &(eth->regs), 0, sizeof(eth->regs) );
630 
        eth->regs.moder = 0x0000A000;
631 
        eth->regs.ipgt = 0x00000012;
632 
        eth->regs.ipgr1 = 0x0000000C;
633 
        eth->regs.ipgr2 = 0x00000012;
634 
        eth->regs.packetlen = 0x003C0600;
635 
        eth->regs.collconf = 0x000F003F;
636 
        eth->regs.miimoder = 0x00000064;
637 1018 simons 
        eth->regs.tx_bd_num = 0x00000040;
638 702 ivang 
 
639 
        /* Initialize TX/RX status */
640 
        memset( &(eth->tx), 0, sizeof(eth->tx) );
641 
        memset( &(eth->rx), 0, sizeof(eth->rx) );
642 1018 simons 
        eth->rx.bd_index = eth->regs.tx_bd_num << 1;
643 889 ivang 
 
644 
        /* Initialize VAPI */
645 
        if (config.ethernets[i].base_vapi_id) {
646 
            eth->base_vapi_id = config.ethernets[i].base_vapi_id;
647 
            vapi_install_multi_handler( eth->base_vapi_id, ETH_NUM_VAPI_IDS, eth_vapi_read );
648 
        }
649 702 ivang 
    }
650 
}
651 
/* ========================================================================= */
652 
 
653 
 
654 696 ivang 
/*
655 
  Print register values on stdout
656 
*/
657 
void eth_status( void )
658 
{
659 
    unsigned i;
660 
 
661 
    for ( i = 0; i < MAX_ETHERNETS; ++ i ) {
662 702 ivang 
        struct eth_device *eth = &(eths[i]);
663 
 
664 
        if ( eth->baseaddr == 0 )
665 
            continue;
666 
 
667 1350 nogj 
        PRINTF( "\nEthernet MAC %u at 0x%"PRIxADDR":\n", i, eth->baseaddr );
668 997 markom 
        PRINTF( "MODER        : 0x%08lX\n", eth->regs.moder );
669 
        PRINTF( "INT_SOURCE   : 0x%08lX\n", eth->regs.int_source );
670 
        PRINTF( "INT_MASK     : 0x%08lX\n", eth->regs.int_mask );
671 
        PRINTF( "IPGT         : 0x%08lX\n", eth->regs.ipgt );
672 
        PRINTF( "IPGR1        : 0x%08lX\n", eth->regs.ipgr1 );
673 
        PRINTF( "IPGR2        : 0x%08lX\n", eth->regs.ipgr2 );
674 
        PRINTF( "PACKETLEN    : 0x%08lX\n", eth->regs.packetlen );
675 
        PRINTF( "COLLCONF     : 0x%08lX\n", eth->regs.collconf );
676 
        PRINTF( "TX_BD_NUM    : 0x%08lX\n", eth->regs.tx_bd_num );
677 
        PRINTF( "CTRLMODER    : 0x%08lX\n", eth->regs.controlmoder );
678 
        PRINTF( "MIIMODER     : 0x%08lX\n", eth->regs.miimoder );
679 
        PRINTF( "MIICOMMAND   : 0x%08lX\n", eth->regs.miicommand );
680 
        PRINTF( "MIIADDRESS   : 0x%08lX\n", eth->regs.miiaddress );
681 
        PRINTF( "MIITX_DATA   : 0x%08lX\n", eth->regs.miitx_data );
682 
        PRINTF( "MIIRX_DATA   : 0x%08lX\n", eth->regs.miirx_data );
683 
        PRINTF( "MIISTATUS    : 0x%08lX\n", eth->regs.miistatus );
684 
        PRINTF( "MAC Address  : %02X:%02X:%02X:%02X:%02X:%02X\n",
685 702 ivang 
                eth->mac_address[0], eth->mac_address[1], eth->mac_address[2],
686 
                eth->mac_address[3], eth->mac_address[4], eth->mac_address[5] );
687 997 markom 
        PRINTF( "HASH0        : 0x%08lX\n", eth->regs.hash0 );
688 
        PRINTF( "HASH1        : 0x%08lX\n", eth->regs.hash1 );
689 696 ivang 
    }
690 
}
691 
/* ========================================================================= */
692 
 
693 
 
694 
/*
695 
  Simulation hook. Must be called every clock cycle to simulate Ethernet MAC.
696 
*/
697 
void eth_clock()
698 
{
699 
    unsigned i;
700 
 
701 
    for ( i = 0; i < config.nethernets; ++ i ) {
702 702 ivang 
        eth_controller_tx_clock( &(eths[i]) );
703 
        eth_controller_rx_clock( &(eths[i]) );
704 696 ivang 
    }
705 
}
706 
/* ========================================================================= */
707 
 
708 
 
709 
/*
710 
  Read a register
711 
*/
712 1359 nogj 
uint32_t eth_read32( oraddr_t addr, void *dat )
713 696 ivang 
{
714 
    struct eth_device *eth;
715 702 ivang 
    if ( !eth_find_controller( addr, &eth, &addr ) )    {
716 1350 nogj 
        PRINTF( "eth_read32( 0x%"PRIxADDR" ): Not in registered range(s)\n", addr );
717 702 ivang 
        return 0;
718 696 ivang 
    }
719 
 
720 
    switch( addr ) {
721 
    case ETH_MODER: return eth->regs.moder;
722 
    case ETH_INT_SOURCE: return eth->regs.int_source;
723 
    case ETH_INT_MASK: return eth->regs.int_mask;
724 
    case ETH_IPGT: return eth->regs.ipgt;
725 
    case ETH_IPGR1: return eth->regs.ipgr1;
726 
    case ETH_IPGR2: return eth->regs.ipgr2;
727 
    case ETH_PACKETLEN: return eth->regs.packetlen;
728 
    case ETH_COLLCONF: return eth->regs.collconf;
729 
    case ETH_TX_BD_NUM: return eth->regs.tx_bd_num;
730 
    case ETH_CTRLMODER: return eth->regs.controlmoder;
731 
    case ETH_MIIMODER: return eth->regs.miimoder;
732 
    case ETH_MIICOMMAND: return eth->regs.miicommand;
733 
    case ETH_MIIADDRESS: return eth->regs.miiaddress;
734 
    case ETH_MIITX_DATA: return eth->regs.miitx_data;
735 
    case ETH_MIIRX_DATA: return eth->regs.miirx_data;
736 
    case ETH_MIISTATUS: return eth->regs.miistatus;
737 
    case ETH_MAC_ADDR0: return (((unsigned long)eth->mac_address[3]) << 24) |
738 702 ivang 
                               (((unsigned long)eth->mac_address[2]) << 16) |
739 
                               (((unsigned long)eth->mac_address[1]) << 8) |
740 
                                 (unsigned long)eth->mac_address[0];
741 696 ivang 
    case ETH_MAC_ADDR1: return (((unsigned long)eth->mac_address[5]) << 8) |
742 702 ivang 
                                 (unsigned long)eth->mac_address[4];
743 744 simons 
    case ETH_HASH0: return eth->regs.hash0;
744 
    case ETH_HASH1: return eth->regs.hash1;
745 702 ivang 
    /*case ETH_DMA_RX_TX: return eth_rx( eth );*/
746 696 ivang 
    }
747 
 
748 
    if ( (addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE) )
749 702 ivang 
        return eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4];
750 696 ivang 
 
751 1350 nogj 
    PRINTF( "eth_read32( 0x%"PRIxADDR" ): Illegal address\n",
752 
            addr + eth->baseaddr );
753 884 markom 
    runtime.sim.cont_run = 0;
754 696 ivang 
    return 0;
755 
}
756 
/* ========================================================================= */
757 
 
758 
 
759 
/*
760 
  Write a register
761 
*/
762 1359 nogj 
void eth_write32( oraddr_t addr, uint32_t value, void *dat )
763 696 ivang 
{
764 
    struct eth_device *eth;
765 702 ivang 
    if ( !eth_find_controller( addr, &eth, &addr ) )    {
766 1350 nogj 
        PRINTF( "eth_write32( 0x%"PRIxADDR" ): Not in registered range(s)\n", addr );
767 702 ivang 
    return;
768 696 ivang 
    }
769 
 
770 
    switch( addr ) {
771 841 simons 
    case ETH_MODER: eth->regs.moder = value; if (TEST_FLAG(value, ETH_MODER, RST)) eth_reset(); return;
772 744 simons 
    case ETH_INT_SOURCE: eth->regs.int_source &= ~value; return;
773 696 ivang 
    case ETH_INT_MASK: eth->regs.int_mask = value; return;
774 
    case ETH_IPGT: eth->regs.ipgt = value; return;
775 
    case ETH_IPGR1: eth->regs.ipgr1 = value; return;
776 
    case ETH_IPGR2: eth->regs.ipgr2 = value; return;
777 
    case ETH_PACKETLEN: eth->regs.packetlen = value; return;
778 
    case ETH_COLLCONF: eth->regs.collconf = value; return;
779 
    case ETH_TX_BD_NUM: eth_write_tx_bd_num( eth, value ); return;
780 
    case ETH_CTRLMODER: eth->regs.controlmoder = value; return;
781 
    case ETH_MIIMODER: eth->regs.miimoder = value; return;
782 
    case ETH_MIICOMMAND: eth->regs.miicommand = value; return;
783 
    case ETH_MIIADDRESS: eth->regs.miiaddress = value; return;
784 
    case ETH_MIITX_DATA: eth->regs.miitx_data = value; return;
785 
    case ETH_MIIRX_DATA: eth->regs.miirx_data = value; return;
786 
    case ETH_MIISTATUS: eth->regs.miistatus = value; return;
787 
    case ETH_MAC_ADDR0:
788 702 ivang 
        eth->mac_address[0] = value & 0xFF;
789 
        eth->mac_address[1] = (value >> 8) & 0xFF;
790 
        eth->mac_address[2] = (value >> 16) & 0xFF;
791 
        eth->mac_address[3] = (value >> 24) & 0xFF;
792 
        return;
793 696 ivang 
    case ETH_MAC_ADDR1:
794 702 ivang 
        eth->mac_address[4] = value & 0xFF;
795 
        eth->mac_address[5] = (value >> 8) & 0xFF;
796 
        return;
797 744 simons 
    case ETH_HASH0: eth->regs.hash0 = value; return;
798 
    case ETH_HASH1: eth->regs.hash1 = value; return;
799 702 ivang 
 
800 
    /*case ETH_DMA_RX_TX: eth_tx( eth, value ); return;*/
801 696 ivang 
    }
802 
 
803 
    if ( (addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE) ) {
804 702 ivang 
        eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4] = value;
805 
        return;
806 696 ivang 
    }
807 
 
808 1350 nogj 
    PRINTF( "eth_write32( 0x%"PRIxADDR" ): Illegal address\n",
809 
            addr + eth->baseaddr );
810 884 markom 
    runtime.sim.cont_run = 0;
811 696 ivang 
    return;
812 
}
813 
/* ========================================================================= */
814 
 
815 
 
816 889 ivang 
/*
817 
 *   VAPI connection to outside
818 
 */
819 
static void eth_vapi_read (unsigned long id, unsigned long data)
820 
{
821 
    unsigned long which;
822 
    struct eth_device *eth = eth_find_vapi_device( id, &which );
823 
 
824 1350 nogj 
    debug( 5, "ETH: id %08lx, data %08lx\n", id, data );
825 889 ivang 
 
826 
    if ( !eth ) {
827 1350 nogj 
        debug( 1, "ETH: VAPI ID %08lx is not ours!\n", id );
828 889 ivang 
        return;
829 
    }
830 
 
831 
    switch( which ) {
832 
    case ETH_VAPI_DATA:
833 
        break;
834 
    case ETH_VAPI_CTRL:
835 
        break;
836 
    }
837 
}
838 
/* ========================================================================= */
839 
 
840 
 
841 702 ivang 
/* When TX_BD_NUM is written, also reset current RX BD index */
842 
void eth_write_tx_bd_num( struct eth_device *eth, unsigned long value )
843 
{
844 1018 simons 
    eth->regs.tx_bd_num = value & 0xFF;
845 
    eth->rx.bd_index = eth->regs.tx_bd_num << 1;
846 702 ivang 
}
847 
/* ========================================================================= */
848 
 
849 
 
850 696 ivang 
/*
851 
  Convert a memory address to a oontroller struct and relative address.
852 
  Return nonzero on success
853 
*/
854 1350 nogj 
int eth_find_controller( oraddr_t addr, struct eth_device **eth, oraddr_t *reladdr )
855 696 ivang 
{
856 
    unsigned i;
857 
    *eth = NULL;
858 
 
859 
    for ( i = 0; i < MAX_ETHERNETS && *eth == NULL; ++ i ) {
860 702 ivang 
        if ( (addr >= eths[i].baseaddr) && (addr < eths[i].baseaddr + ETH_ADDR_SPACE) )
861 
            *eth = &(eths[i]);
862 
        }
863 696 ivang 
 
864 
    /* verify we found a controller */
865 
    if ( *eth == NULL )
866 702 ivang 
        return 0;
867 696 ivang 
 
868 
    /* Verify legal address */
869 
    if ( (addr - (*eth)->baseaddr) % 4 != 0 )
870 702 ivang 
        return 0;
871 696 ivang 
 
872 
    *reladdr = addr - (*eth)->baseaddr;
873 
    return 1;
874 
}
875 889 ivang 
 
876 
/*
877 
 * Convert VAPI id to controller struct and relative address.
878 
 */
879 1244 hpanther 
struct eth_device *eth_find_vapi_device( unsigned long id, unsigned long *which )
880 889 ivang 
{
881 
    unsigned i;
882 
 
883 
    for ( i=0; i<config.nethernets; i++) {
884 
        if ( (id>=eths[i].base_vapi_id) && (id < eths[i].base_vapi_id + ETH_NUM_VAPI_IDS)) {
885 
            *which = id - eths[i].base_vapi_id;
886 
            return &(eths[i]);
887 
        }
888 
    }
889 
 
890 
    return NULL;
891 
}
892 1358 nogj 
 
893 
/*-----------------------------------------------[ Ethernet configuration ]---*/
894 
void eth_nethernets (union param_val val, void *dat) {
895 
  if (val.int_val >= 0 && val.int_val < MAX_ETHERNETS)
896 
    config.nethernets = val.int_val;
897 
  else
898 
    CONFIG_ERROR("invalid number of devices.");
899 
}
900 
 
901 
void eth_baseaddr (union param_val val, void *dat) {
902 
  if (current_device >= 0 && current_device < config.nethernets)
903 
    config.ethernets[current_device].baseaddr = val.addr_val;
904 
  else
905 
    CONFIG_ERROR("invalid device number.");
906 
}
907 
 
908 
void eth_dma (union param_val val, void *dat) {
909 
  if (current_device >= 0 && current_device < config.nethernets)
910 
    config.ethernets[current_device].dma = val.int_val;
911 
  else
912 
    CONFIG_ERROR("invalid device number.");
913 
}
914 
 
915 
void eth_rtx_type (union param_val val, void *dat) {
916 
  if (current_device >= 0 && current_device < config.nethernets)
917 
    config.ethernets[current_device].rtx_type = val.int_val;
918 
  else
919 
    CONFIG_ERROR("invalid device number.");
920 
}
921 
 
922 
void eth_rx_channel (union param_val val, void *dat) {
923 
  if (current_device >= 0 && current_device < config.nethernets)
924 
    config.ethernets[current_device].rx_channel = val.int_val;
925 
  else
926 
    CONFIG_ERROR("invalid device number.");
927 
}
928 
 
929 
void eth_tx_channel (union param_val val, void *dat) {
930 
  if (current_device >= 0 && current_device < config.nethernets)
931 
    config.ethernets[current_device].rx_channel = val.int_val;
932 
  else
933 
    CONFIG_ERROR("invalid device number.");
934 
}
935 
 
936 
void eth_rxfile (union param_val val, void *dat) {
937 
  if (current_device >= 0 && current_device < config.nethernets)
938 
    strcpy (config.ethernets[current_device].rxfile, val.str_val);
939 
  else
940 
    CONFIG_ERROR("invalid device number.");
941 
}
942 
 
943 
void eth_txfile(union param_val val, void *dat)
944 
{
945 
  if (current_device >= 0 && current_device < config.nethernets)
946 
    strcpy (config.ethernets[current_device].txfile, val.str_val);
947 
  else
948 
    CONFIG_ERROR("invalid device number.");
949 
}
950 
 
951 
void eth_sockif(union param_val val, void *dat)
952 
{
953 
  if (current_device >= 0 && current_device < config.nethernets)
954 
    strcpy (config.ethernets[current_device].sockif, val.str_val);
955 
  else
956 
    CONFIG_ERROR("invalid device number.");
957 
}
958 
 
959 
void eth_irq(union param_val val, void *dat)
960 
{
961 
  if (current_device >= 0 && current_device < config.nethernets)
962 
    config.ethernets[current_device].irq = val.int_val;
963 
  else
964 
    CONFIG_ERROR("invalid device number.");
965 
}
966 
 
967 
void eth_vapi_id(union param_val val, void *dat)
968 
{
969 
  if (current_device >= 0 && current_device < config.nethernets)
970 
    config.ethernets[current_device].base_vapi_id = val.int_val;
971 
  else
972 
    CONFIG_ERROR("invalid device number.");
973 
}
974 
 
975 
void reg_ethernet_sec(void)
976 
{
977 
  struct config_section *sec = reg_config_sec("ethernet", NULL, NULL);
978 
 
979 
  reg_config_param(sec, "nethernets", paramt_int, eth_nethernets);
980 
  reg_config_param(sec, "device", paramt_int, change_device);
981 
  reg_config_param(sec, "irq", paramt_int, eth_irq);
982 
  reg_config_param(sec, "enddevice", paramt_int, end_device);
983 
  reg_config_param(sec, "baseaddr", paramt_int, eth_baseaddr);
984 
  reg_config_param(sec, "dma", paramt_int, eth_dma);
985 
  reg_config_param(sec, "rtx_type", paramt_int, eth_rtx_type);
986 
  reg_config_param(sec, "rx_channel", paramt_int, eth_rx_channel);
987 
  reg_config_param(sec, "tx_channel", paramt_int, eth_tx_channel);
988 
  reg_config_param(sec, "rxfile", paramt_str, eth_rxfile);
989 
  reg_config_param(sec, "txfile", paramt_str, eth_txfile);
990 
  reg_config_param(sec, "sockif", paramt_str, eth_sockif);
991 
  reg_config_param(sec, "vapi_id", paramt_int, eth_vapi_id);
992 
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.