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[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [peripheral/] [eth.c] - Blame information for rev 1486

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1 696 ivang 
/* ethernet.c -- Simulation of Ethernet MAC
2 
   Copyright (C) 2001 by Erez Volk, erez@opencores.org
3 
                         Ivan Guzvinec, ivang@opencores.org
4 
 
5 
   This file is part of OpenRISC 1000 Architectural Simulator.
6 
 
7 
   This program is free software; you can redistribute it and/or modify
8 
   it under the terms of the GNU General Public License as published by
9 
   the Free Software Foundation; either version 2 of the License, or
10 
   (at your option) any later version.
11 
 
12 
   This program is distributed in the hope that it will be useful,
13 
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14 
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 
   GNU General Public License for more details.
16 
 
17 
   You should have received a copy of the GNU General Public License
18 
   along with this program; if not, write to the Free Software
19 
   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 
*/
21 
 
22 
#include <stdlib.h>
23 
#include <stdio.h>
24 
#include <string.h>
25 
#include <sys/types.h>
26 
#include <sys/stat.h>
27 
#include <fcntl.h>
28 
#include <sys/poll.h>
29 
#include <sys/time.h>
30 
#include <unistd.h>
31 
#include <errno.h>
32 1308 phoenix 
#include <netinet/in.h>
33 696 ivang 
 
34 867 markom 
#include "config.h"
35 1350 nogj 
 
36 
#ifdef HAVE_INTTYPES_H
37 
#include <inttypes.h>
38 
#endif
39 
 
40 
#include "port.h"
41 
#include "arch.h"
42 
#include "config.h"
43 696 ivang 
#include "abstract.h"
44 
#include "ethernet_i.h"
45 
#include "dma.h"
46 
#include "sim-config.h"
47 
#include "fields.h"
48 
#include "crc32.h"
49 889 ivang 
#include "vapi.h"
50 1308 phoenix 
#include "pic.h"
51 1372 nogj 
#include "sched.h"
52 1308 phoenix 
#include "debug.h"
53 696 ivang 
 
54 1463 nogj 
DEFAULT_DEBUG_CHANNEL(eth);
55 
 
56 702 ivang 
/* simulator interface */
57 1366 nogj 
static void eth_vapi_read( unsigned long id, unsigned long data, void *dat);
58 696 ivang 
/* register interface */
59 1359 nogj 
static void eth_write32( oraddr_t addr, uint32_t value, void *dat );
60 
static uint32_t eth_read32( oraddr_t addr, void *dat );
61 696 ivang 
/* clock */
62 1372 nogj 
static void eth_controller_tx_clock( void * );
63 
static void eth_controller_rx_clock( void * );
64 696 ivang 
/* utility functions */
65 702 ivang 
static ssize_t eth_read_rx_file( struct eth_device *, void *, size_t );
66 
static void eth_skip_rx_file( struct eth_device *, off_t );
67 
static void eth_rewind_rx_file( struct eth_device *, off_t );
68 
static void eth_rx_next_packet( struct eth_device * );
69 
static void eth_write_tx_bd_num( struct eth_device *, unsigned long value );
70 696 ivang 
/* ========================================================================= */
71 702 ivang 
/*  TX LOGIC                                                                 */
72 696 ivang 
/*---------------------------------------------------------------------------*/
73 
 
74 
/*
75 
 * TX clock
76 
 * Responsible for starting and finishing TX
77 
 */
78 1372 nogj 
void eth_controller_tx_clock( void *dat )
79 696 ivang 
{
80 1372 nogj 
    struct eth_device *eth = dat;
81 702 ivang 
    int breakpoint = 0;
82 
    int bAdvance   = 1;
83 867 markom 
#if HAVE_ETH_PHY
84 702 ivang 
    struct sockaddr_ll sll;
85 849 markom 
#endif /* HAVE_ETH_PHY */
86 1463 nogj 
    long nwritten = 0;
87 702 ivang 
    unsigned long read_word;
88 696 ivang 
 
89 
    switch (eth->tx.state) {
90 1372 nogj 
    case ETH_TXSTATE_IDLE:
91 1463 nogj 
        TRACE ("TX - entering state WAIT4BD (%ld)\n", eth->tx.bd_index);
92 1372 nogj 
        eth->tx.state = ETH_TXSTATE_WAIT4BD;
93 702 ivang 
        break;
94 696 ivang 
    case ETH_TXSTATE_WAIT4BD:
95 702 ivang 
        /* Read buffer descriptor */
96 
        eth->tx.bd = eth->regs.bd_ram[eth->tx.bd_index];
97 
        eth->tx.bd_addr = eth->regs.bd_ram[eth->tx.bd_index + 1];
98 
 
99 
        if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, READY ) ) {
100 
            /*****************/
101 
            /* initialize TX */
102 
            eth->tx.bytes_left = eth->tx.packet_length = GET_FIELD( eth->tx.bd, ETH_TX_BD, LENGTH );
103 
            eth->tx.bytes_sent = 0;
104 
 
105 
            /*   Initialize error status bits */
106 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, DEFER );
107 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, COLLISION );
108 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, RETRANSMIT );
109 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, UNDERRUN );
110 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, NO_CARRIER );
111 
            SET_FIELD ( eth->tx.bd, ETH_TX_BD, RETRY, 0 );
112 
 
113 
            /* Find out minimum length */
114 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, PAD ) ||
115 
                 TEST_FLAG( eth->regs.moder, ETH_MODER, PAD ) )
116 
                eth->tx.minimum_length = GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL );
117 
            else
118 
                eth->tx.minimum_length = eth->tx.packet_length;
119 
 
120 
            /* Find out maximum length */
121 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, HUGEN ) )
122 
                eth->tx.maximum_length = eth->tx.packet_length;
123 
            else
124 
                eth->tx.maximum_length = GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL );
125 
 
126 
            /* Do we need CRC on this packet? */
127 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, CRCEN ) ||
128 
                 (TEST_FLAG( eth->tx.bd, ETH_TX_BD, CRC) &&
129 
                  TEST_FLAG( eth->tx.bd, ETH_TX_BD, LAST)) )
130 
                eth->tx.add_crc = 1;
131 
            else
132 
                eth->tx.add_crc = 0;
133 
 
134 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, DLYCRCEN ) )
135 
                eth->tx.crc_dly = 1;
136 
            else
137 
                eth->tx.crc_dly = 0;
138 
            /* XXX - For now we skip CRC calculation */
139 
 
140 1463 nogj 
            TRACE( "Ethernet: Starting TX of %lu bytes (min. %u, max. %u)\n",
141 1350 nogj 
                   eth->tx.packet_length, eth->tx.minimum_length,
142 
                   eth->tx.maximum_length );
143 702 ivang 
 
144 
            if (eth->rtx_type == ETH_RTX_FILE) {
145 
                /* write packet length to file */
146 
                nwritten = write( eth->txfd, &(eth->tx.packet_length), sizeof(eth->tx.packet_length) );
147 
            }
148 
 
149 
            /************************************************/
150 
            /* start transmit with reading packet into FIFO */
151 1463 nogj 
                TRACE ("TX - entering state READFIFO\n");
152 702 ivang 
            eth->tx.state = ETH_TXSTATE_READFIFO;
153 
        }
154 
 
155 
        /* stay in this state if (TXEN && !READY) */
156 
        break;
157 696 ivang 
    case ETH_TXSTATE_READFIFO:
158 744 simons 
#if 1
159 702 ivang 
        if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
160 1241 phoenix 
            read_word = eval_direct32(eth->tx.bytes_sent + eth->tx.bd_addr, &breakpoint, 0, 0);
161 702 ivang 
            eth->tx_buff[eth->tx.bytes_sent]   = (unsigned char)(read_word >> 24);
162 
            eth->tx_buff[eth->tx.bytes_sent+1] = (unsigned char)(read_word >> 16);
163 
            eth->tx_buff[eth->tx.bytes_sent+2] = (unsigned char)(read_word >> 8);
164 
            eth->tx_buff[eth->tx.bytes_sent+3] = (unsigned char)(read_word);
165 
            eth->tx.bytes_sent += 4;
166 
        }
167 744 simons 
#else
168 
        if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
169 1241 phoenix 
            eth->tx_buff[eth->tx.bytes_sent] = eval_direct8(eth->tx.bytes_sent + eth->tx.bd_addr, &breakpoint, 0, 0);
170 744 simons 
            eth->tx.bytes_sent += 1;
171 
        }
172 
#endif
173 702 ivang 
        else {
174 1463 nogj 
            TRACE ("TX - entering state TRANSMIT\n");
175 702 ivang 
            eth->tx.state = ETH_TXSTATE_TRANSMIT;
176 
        }
177 
        break;
178 696 ivang 
    case ETH_TXSTATE_TRANSMIT:
179 702 ivang 
        /* send packet */
180 
        switch (eth->rtx_type) {
181 
        case ETH_RTX_FILE:
182 
            nwritten = write( eth->txfd, eth->tx_buff, eth->tx.packet_length );
183 
            break;
184 867 markom 
#if HAVE_ETH_PHY
185 702 ivang 
        case ETH_RTX_SOCK:
186 
            memset(&sll, 0, sizeof(sll));
187 705 ivang 
            sll.sll_ifindex = eth->ifr.ifr_ifindex;
188 
            nwritten = sendto(eth->rtx_sock, eth->tx_buff, eth->tx.packet_length, 0, (struct sockaddr *)&sll, sizeof(sll));
189 849 markom 
#endif /* HAVE_ETH_PHY */
190 702 ivang 
        }
191 
 
192 
        /* set BD status */
193 
        if (nwritten == eth->tx.packet_length) {
194 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
195 
            SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXB);
196 1463 nogj 
            TRACE ("ETH_INT_SOURCE = %0lx\n", eth->regs.int_source);
197 702 ivang 
 
198 1463 nogj 
            TRACE ("TX - entering state WAIT4BD\n");
199 1372 nogj 
            eth->tx.state = ETH_TXSTATE_WAIT4BD;
200 1463 nogj 
            TRACE ("send (%ld)bytes OK\n", nwritten);
201 702 ivang 
        }
202 
        else {
203 
            /* XXX - implement retry mechanism here! */
204 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
205 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, COLLISION);
206 
            SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXE);
207 1463 nogj 
            TRACE ("ETH_INT_SOURCE = %0lx\n", eth->regs.int_source);
208 702 ivang 
 
209 1463 nogj 
            TRACE ("TX - entering state WAIT4BD\n");
210 1372 nogj 
            eth->tx.state = ETH_TXSTATE_WAIT4BD;
211 1463 nogj 
            TRACE ("send FAILED!\n");
212 702 ivang 
        }
213 
 
214 
        eth->regs.bd_ram[eth->tx.bd_index] = eth->tx.bd;
215 
 
216 889 ivang 
        /* generate OK interrupt */
217 
        if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, TXE_M) ||
218 
             TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, TXB_M) )
219 
        {
220 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, IRQ ) )
221 
                report_interrupt( eth->mac_int );
222 
        }
223 
 
224 702 ivang 
        /* advance to next BD */
225 
        if (bAdvance) {
226 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, WRAP ) ||
227 
                            eth->tx.bd_index >= ETH_BD_COUNT )
228 
                eth->tx.bd_index = 0;
229 
            else
230 
                eth->tx.bd_index += 2;
231 
        }
232 
 
233 
        break;
234 696 ivang 
    }
235 1372 nogj 
 
236 
    /* Reschedule */
237 1390 nogj 
    SCHED_ADD( eth_controller_tx_clock, dat, 1 );
238 696 ivang 
}
239 
/* ========================================================================= */
240 
 
241 
 
242 
/* ========================================================================= */
243 702 ivang 
/*  RX LOGIC                                                                 */
244 696 ivang 
/*---------------------------------------------------------------------------*/
245 
 
246 
/*
247 
 * RX clock
248 
 * Responsible for starting and finishing RX
249 
 */
250 1372 nogj 
void eth_controller_rx_clock( void *dat )
251 696 ivang 
{
252 1372 nogj 
    struct eth_device *eth = dat;
253 702 ivang 
    int breakpoint = 0;
254 
    long nread;
255 
    unsigned long send_word;
256 
 
257 
 
258 696 ivang 
    switch (eth->rx.state) {
259 
    case ETH_RXSTATE_IDLE:
260 1463 nogj 
        TRACE ("RX - entering state WAIT4BD (%ld)\n", eth->rx.bd_index);
261 1372 nogj 
        eth->rx.state = ETH_RXSTATE_WAIT4BD;
262 702 ivang 
        break;
263 
 
264 696 ivang 
    case ETH_RXSTATE_WAIT4BD:
265 702 ivang 
        eth->rx.bd = eth->regs.bd_ram[eth->rx.bd_index];
266 
        eth->rx.bd_addr = eth->regs.bd_ram[eth->rx.bd_index + 1];
267 
 
268 
        if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, READY ) ) {
269 
            /*****************/
270 
            /* Initialize RX */
271 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, MISS );
272 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, INVALID );
273 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, DRIBBLE );
274 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, UVERRUN );
275 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, COLLISION );
276 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG );
277 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT );
278 
 
279 1463 nogj 
            TRACE( "Ethernet: Starting RX\n" );
280 702 ivang 
 
281 
            /* Setup file to read from */
282 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, LOOPBCK ) ) {
283 
                eth->rx.fd = eth->txfd;
284 
                eth->rx.offset = &(eth->loopback_offset);
285 
            } else {
286 
                eth->rx.fd = eth->rxfd;
287 
                eth->rx.offset = 0;
288 
            }
289 1463 nogj 
            TRACE ("RX - entering state RECV\n");
290 702 ivang 
            eth->rx.state = ETH_RXSTATE_RECV;
291 
        }
292 705 ivang 
        else if (!TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN)) {
293 1463 nogj 
          TRACE ("RX - entering state IDLE\n");
294 705 ivang 
          eth->rx.state = ETH_RXSTATE_IDLE;
295 
        }
296 
        else {
297 744 simons 
            nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, /*MSG_PEEK | */MSG_DONTWAIT);
298 705 ivang 
            if (nread > 0) {
299 702 ivang 
                SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, BUSY);
300 723 ivang 
                if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, BUSY_M) )
301 
                  report_interrupt(eth->mac_int);
302 702 ivang 
            }
303 
        }
304 
        break;
305 
 
306 696 ivang 
    case ETH_RXSTATE_RECV:
307 702 ivang 
        switch (eth->rtx_type) {
308 
        case ETH_RTX_FILE:
309 
            /* Read packet length */
310 
            if ( eth_read_rx_file( eth, &(eth->rx.packet_length), sizeof(eth->rx.packet_length) )
311 
                     < sizeof(eth->rx.packet_length) ) {
312 
                /* TODO: just do what real ethernet would do (some kind of error state) */
313 1463 nogj 
                TRACE ("eth_start_rx(): File does not have a packet ready for RX (len = %ld)\n", eth->rx.packet_length );
314 
                sim_done();
315 702 ivang 
                break;
316 
            }
317 
 
318 
            /* Packet must be big enough to hold a header */
319 1244 hpanther 
            if ( eth->rx.packet_length < ETHER_HDR_LEN ){
320 1463 nogj 
                TRACE( "eth_start_rx(): Packet too small\n" );
321 702 ivang 
                eth_rx_next_packet( eth );
322 
 
323 1463 nogj 
                TRACE ("RX - entering state WAIT4BD\n");
324 1372 nogj 
                eth->rx.state = ETH_RXSTATE_WAIT4BD;
325 702 ivang 
                break;
326 
            }
327 
 
328 
            eth->rx.bytes_read = 0;
329 
            eth->rx.bytes_left = eth->rx.packet_length;
330 
 
331 
            /* for now Read entire packet into memory */
332 
            nread = eth_read_rx_file( eth, eth->rx_buff, eth->rx.bytes_left );
333 844 ivang 
            if ( nread < eth->rx.bytes_left ) {
334 1463 nogj 
                TRACE ("Read %ld from %ld. Error!\n", nread, eth->rx.bytes_left);
335 844 ivang 
                eth->rx.error = 1;
336 
                break;
337 
            }
338 
 
339 
            eth->rx.packet_length = nread;
340 
            eth->rx.bytes_left = nread;
341 
            eth->rx.bytes_read = 0;
342 
 
343 1463 nogj 
            TRACE ("RX - entering state WRITEFIFO\n");
344 844 ivang 
            eth->rx.state = ETH_RXSTATE_WRITEFIFO;
345 
 
346 702 ivang 
            break;
347 
 
348 
        case ETH_RTX_SOCK:
349 
            nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, MSG_DONTWAIT);
350 744 simons 
 
351 1463 nogj 
            if (nread == 0) {
352 
                TRACE("No data read\n");
353 744 simons 
                break;
354 1463 nogj 
            } else if (nread < 0) {
355 744 simons 
                if ( errno != EAGAIN ) {
356 1463 nogj 
                    TRACE ("recv() FAILED!\n");
357 889 ivang 
                    break;
358 
                }
359 1463 nogj 
                else
360 
                    break;
361 889 ivang 
            }
362 744 simons 
            /* If not promiscouos mode, check the destination address */
363 
            if (!TEST_FLAG(eth->regs.moder, ETH_MODER, PRO)) {
364 
                if (TEST_FLAG(eth->regs.moder, ETH_MODER, IAM) && (eth->rx_buff[0] & 1)) {
365 
                /* Nothing for now */
366 
                }
367 
 
368 
                if (eth->mac_address[5] != eth->rx_buff[0] ||
369 
                    eth->mac_address[4] != eth->rx_buff[1] ||
370 
                    eth->mac_address[3] != eth->rx_buff[2] ||
371 
                    eth->mac_address[2] != eth->rx_buff[3] ||
372 
                    eth->mac_address[1] != eth->rx_buff[4] ||
373 
                    eth->mac_address[0] != eth->rx_buff[5])
374 889 ivang 
                    break;
375 744 simons 
            }
376 
 
377 841 simons 
            eth->rx.packet_length = nread;
378 
            eth->rx.bytes_left = nread;
379 
            eth->rx.bytes_read = 0;
380 
 
381 1463 nogj 
            TRACE ("RX - entering state WRITEFIFO\n");
382 841 simons 
            eth->rx.state = ETH_RXSTATE_WRITEFIFO;
383 
 
384 702 ivang 
            break;
385 889 ivang 
        case ETH_RTX_VAPI:
386 1366 nogj 
            break;
387 702 ivang 
        }
388 841 simons 
        break;
389 
 
390 696 ivang 
    case ETH_RXSTATE_WRITEFIFO:
391 744 simons 
#if 1
392 702 ivang 
        send_word = ((unsigned long)eth->rx_buff[eth->rx.bytes_read]   << 24) |
393 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+1] << 16) |
394 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+2] << 8)  |
395 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+3] );
396 1241 phoenix 
        set_direct32( eth->rx.bd_addr + eth->rx.bytes_read, send_word, &breakpoint, 0, 0);
397 702 ivang 
        /* update counters */
398 1463 nogj 
        TRACE ("Write %ld, left %ld - %08lXd\n", eth->rx.bytes_read,
399 1350 nogj 
               eth->rx.bytes_left, send_word);
400 702 ivang 
        eth->rx.bytes_left -= 4;
401 
        eth->rx.bytes_read += 4;
402 744 simons 
#else
403 1241 phoenix 
        set_direct8( eth->rx.bd_addr + eth->rx.bytes_read, eth->rx_buff[eth->rx.bytes_read], &breakpoint, 0, 0);
404 744 simons 
        eth->rx.bytes_left -= 1;
405 
        eth->rx.bytes_read += 1;
406 
#endif
407 
 
408 702 ivang 
        if ( eth->rx.bytes_left <= 0 ) {
409 
            /* Write result to bd */
410 
            SET_FIELD( eth->rx.bd, ETH_RX_BD, LENGTH, eth->rx.packet_length );
411 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, READY);
412 705 ivang 
            SET_FLAG( eth->regs.int_source, ETH_INT_SOURCE, RXB);
413 1463 nogj 
            TRACE ("ETH_INT_SOURCE = %0lx\n", eth->regs.int_source);
414 702 ivang 
 
415 1068 simons 
            if ( eth->rx.packet_length < (GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL ) - 4) )
416 744 simons 
                SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT);
417 
            if ( eth->rx.packet_length > GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL ) )
418 702 ivang 
                SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG);
419 
 
420 
            eth->regs.bd_ram[eth->rx.bd_index] = eth->rx.bd;
421 
 
422 
            /* advance to next BD */
423 
            if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, WRAP ) || eth->rx.bd_index >= ETH_BD_COUNT )
424 1018 simons 
                eth->rx.bd_index = eth->regs.tx_bd_num << 1;
425 702 ivang 
            else
426 705 ivang 
                eth->rx.bd_index += 2;
427 702 ivang 
 
428 889 ivang 
            if ( ( TEST_FLAG( eth->regs.int_mask, ETH_INT_MASK, RXB_M ) ) &&
429 
                 ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, IRQ )              ) ) {
430 702 ivang 
                report_interrupt( eth->mac_int );
431 
            }
432 
 
433 
            /* ready to receive next packet */
434 1463 nogj 
                TRACE ("RX - entering state IDLE\n");
435 702 ivang 
            eth->rx.state = ETH_RXSTATE_IDLE;
436 
        }
437 
        break;
438 696 ivang 
    }
439 1372 nogj 
 
440 
    /* Reschedule */
441 1390 nogj 
    SCHED_ADD( eth_controller_rx_clock, dat, 1 );
442 696 ivang 
}
443 702 ivang 
 
444 696 ivang 
/* ========================================================================= */
445 702 ivang 
/* Move to next RX BD */
446 
void eth_rx_next_packet( struct eth_device *eth )
447 
{
448 
    /* Skip any possible leftovers */
449 
    if ( eth->rx.bytes_left )
450 
        eth_skip_rx_file( eth, eth->rx.bytes_left );
451 
}
452 
/* "Skip" bytes in RX file */
453 
void eth_skip_rx_file( struct eth_device *eth, off_t count )
454 
{
455 
    eth->rx.offset += count;
456 
}
457 696 ivang 
 
458 702 ivang 
/* Move RX file position back */
459 
void eth_rewind_rx_file( struct eth_device *eth, off_t count )
460 
{
461 
    eth->rx.offset -= count;
462 
}
463 
/*
464 
 * Utility function to read from the ethernet RX file
465 
 * This function moves the file pointer to the current place in the packet before reading
466 
 */
467 
ssize_t eth_read_rx_file( struct eth_device *eth, void *buf, size_t count )
468 
{
469 
    ssize_t result;
470 
 
471 
    if ( eth->rx.fd <= 0 ) {
472 1463 nogj 
        TRACE( "Ethernet: No RX file\n" );
473 702 ivang 
        return 0;
474 
    }
475 
 
476 
    if ( eth->rx.offset )
477 
        if ( lseek( eth->rx.fd, *(eth->rx.offset), SEEK_SET ) == (off_t)-1 ) {
478 1463 nogj 
            TRACE( "Ethernet: Error seeking RX file\n" );
479 702 ivang 
            return 0;
480 
        }
481 696 ivang 
 
482 702 ivang 
    result = read( eth->rx.fd, buf, count );
483 1463 nogj 
    TRACE ("Ethernet: read result = %d \n", result);
484 702 ivang 
    if ( eth->rx.offset && result >= 0 )
485 
        *(eth->rx.offset) += result;
486 
 
487 
    return result;
488 
}
489 
 
490 
/* ========================================================================= */
491 
 
492 696 ivang 
/*
493 702 ivang 
  Reset. Initializes all registers to default and places devices in
494 
         memory address space.
495 696 ivang 
*/
496 1372 nogj 
void eth_reset(void *dat)
497 696 ivang 
{
498 1372 nogj 
    struct eth_device *eth = dat;
499 1308 phoenix 
#if HAVE_ETH_PHY
500 702 ivang 
    int j;
501 
    struct sockaddr_ll sll;
502 849 markom 
#endif /* HAVE_ETH_PHY */
503 702 ivang 
 
504 
    if ( eth->baseaddr != 0 ) {
505 
        switch (eth->rtx_type) {
506 
        case ETH_RTX_FILE:
507 
            /* (Re-)open TX/RX files */
508 
            if ( eth->rxfd > 0 )
509 
                close( eth->rxfd );
510 
            if ( eth->txfd > 0 )
511 
                close( eth->txfd );
512 
            eth->rxfd = eth->txfd = -1;
513 
 
514 
            if ( (eth->rxfd = open( eth->rxfile, O_RDONLY )) < 0 )
515 
                fprintf( stderr, "Cannot open Ethernet RX file \"%s\"\n", eth->rxfile );
516 
            if ( (eth->txfd = open( eth->txfile,
517 1244 hpanther 
                                    O_RDWR | O_CREAT | O_APPEND
518 
 
519 
#if defined(O_SYNC)     /* BSD / Mac OS X manual doesn't know about O_SYNC */
520 
                                                                        | O_SYNC
521 
#endif
522 
                                                                        ,
523 702 ivang 
                                    S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH )) < 0 )
524 
                fprintf( stderr, "Cannot open Ethernet TX file \"%s\"\n", eth->txfile );
525 
            eth->loopback_offset = lseek( eth->txfd, 0, SEEK_END );
526 
 
527 
            break;
528 867 markom 
#if HAVE_ETH_PHY
529 702 ivang 
        case ETH_RTX_SOCK:
530 
            /* (Re-)open TX/RX sockets */
531 
            if (eth->rtx_sock != 0)
532 
                break;
533 
 
534 1463 nogj 
            TRACE ("RTX opening socket...\n");
535 702 ivang 
            eth->rtx_sock = socket(PF_PACKET, SOCK_RAW, htons(ETH_P_ALL));
536 
            if (eth->rtx_sock == -1) {
537 
                fprintf( stderr, "Cannot open rtx_sock.\n");
538 
                return;
539 
            }
540 
 
541 
            /* get interface index number */
542 1463 nogj 
            TRACE ("RTX getting interface...\n");
543 702 ivang 
            memset(&(eth->ifr), 0, sizeof(eth->ifr));
544 1372 nogj 
            strncpy(eth->ifr.ifr_name, eth->sockif, IFNAMSIZ);
545 702 ivang 
            if (ioctl(eth->rtx_sock, SIOCGIFINDEX, &(eth->ifr)) == -1) {
546 
                fprintf( stderr, "SIOCGIFINDEX failed!\n");
547 
                return;
548 
            }
549 1463 nogj 
            TRACE ("RTX Socket Interface : %d\n", eth->ifr.ifr_ifindex);
550 702 ivang 
 
551 
            /* Bind to interface... */
552 1463 nogj 
            TRACE ("Binding to the interface ifindex=%d\n", eth->ifr.ifr_ifindex);
553 702 ivang 
            memset(&sll, 0xff, sizeof(sll));
554 
            sll.sll_family = AF_PACKET;    /* allways AF_PACKET */
555 
            sll.sll_protocol = htons(ETH_P_ALL);
556 
            sll.sll_ifindex = eth->ifr.ifr_ifindex;
557 
            if (bind(eth->rtx_sock, (struct sockaddr *)&sll, sizeof(sll)) == -1) {
558 
                fprintf( stderr, "Error bind().\n");
559 
                return;
560 
            }
561 
 
562 
            /* first, flush all received packets. */
563 1463 nogj 
            TRACE ("Flush");
564 702 ivang 
            do {
565 
                fd_set fds;
566 
                struct timeval t;
567 
 
568 1463 nogj 
                TRACE( ".");
569 702 ivang 
                FD_ZERO(&fds);
570 
                FD_SET(eth->rtx_sock, &fds);
571 
                memset(&t, 0, sizeof(t));
572 
                j = select(FD_SETSIZE, &fds, NULL, NULL, &t);
573 
                if (j > 0)
574 
                    recv(eth->rtx_sock, eth->rx_buff, j, 0);
575 
            } while (j);
576 1463 nogj 
            TRACE ("\n");
577 702 ivang 
 
578 
            break;
579 1372 nogj 
#else /* HAVE_ETH_PHY */
580 
        case ETH_RTX_SOCK:
581 
            fprintf (stderr, "Ethernet phy not enabled in this configuration.  Configure with --enable-ethphy.\n");
582 
            exit (1);
583 
            break;
584 849 markom 
#endif /* HAVE_ETH_PHY */
585 702 ivang 
        }
586 
 
587 
        /* Set registers to default values */
588 
        memset( &(eth->regs), 0, sizeof(eth->regs) );
589 
        eth->regs.moder = 0x0000A000;
590 
        eth->regs.ipgt = 0x00000012;
591 
        eth->regs.ipgr1 = 0x0000000C;
592 
        eth->regs.ipgr2 = 0x00000012;
593 
        eth->regs.packetlen = 0x003C0600;
594 
        eth->regs.collconf = 0x000F003F;
595 
        eth->regs.miimoder = 0x00000064;
596 1018 simons 
        eth->regs.tx_bd_num = 0x00000040;
597 702 ivang 
 
598 
        /* Initialize TX/RX status */
599 
        memset( &(eth->tx), 0, sizeof(eth->tx) );
600 
        memset( &(eth->rx), 0, sizeof(eth->rx) );
601 1018 simons 
        eth->rx.bd_index = eth->regs.tx_bd_num << 1;
602 889 ivang 
 
603 
        /* Initialize VAPI */
604 1372 nogj 
        if (eth->base_vapi_id) {
605 
            vapi_install_multi_handler( eth->base_vapi_id, ETH_NUM_VAPI_IDS, eth_vapi_read, dat );
606 889 ivang 
        }
607 702 ivang 
    }
608 
}
609 
/* ========================================================================= */
610 
 
611 
 
612 696 ivang 
/*
613 
  Print register values on stdout
614 
*/
615 1372 nogj 
void eth_status( void *dat )
616 696 ivang 
{
617 1372 nogj 
    struct eth_device *eth = dat;
618 696 ivang 
 
619 1372 nogj 
    PRINTF( "\nEthernet MAC at 0x%"PRIxADDR":\n", eth->baseaddr );
620 
    PRINTF( "MODER        : 0x%08lX\n", eth->regs.moder );
621 
    PRINTF( "INT_SOURCE   : 0x%08lX\n", eth->regs.int_source );
622 
    PRINTF( "INT_MASK     : 0x%08lX\n", eth->regs.int_mask );
623 
    PRINTF( "IPGT         : 0x%08lX\n", eth->regs.ipgt );
624 
    PRINTF( "IPGR1        : 0x%08lX\n", eth->regs.ipgr1 );
625 
    PRINTF( "IPGR2        : 0x%08lX\n", eth->regs.ipgr2 );
626 
    PRINTF( "PACKETLEN    : 0x%08lX\n", eth->regs.packetlen );
627 
    PRINTF( "COLLCONF     : 0x%08lX\n", eth->regs.collconf );
628 
    PRINTF( "TX_BD_NUM    : 0x%08lX\n", eth->regs.tx_bd_num );
629 
    PRINTF( "CTRLMODER    : 0x%08lX\n", eth->regs.controlmoder );
630 
    PRINTF( "MIIMODER     : 0x%08lX\n", eth->regs.miimoder );
631 
    PRINTF( "MIICOMMAND   : 0x%08lX\n", eth->regs.miicommand );
632 
    PRINTF( "MIIADDRESS   : 0x%08lX\n", eth->regs.miiaddress );
633 
    PRINTF( "MIITX_DATA   : 0x%08lX\n", eth->regs.miitx_data );
634 
    PRINTF( "MIIRX_DATA   : 0x%08lX\n", eth->regs.miirx_data );
635 
    PRINTF( "MIISTATUS    : 0x%08lX\n", eth->regs.miistatus );
636 
    PRINTF( "MAC Address  : %02X:%02X:%02X:%02X:%02X:%02X\n",
637 
           eth->mac_address[0], eth->mac_address[1], eth->mac_address[2],
638 
           eth->mac_address[3], eth->mac_address[4], eth->mac_address[5] );
639 
    PRINTF( "HASH0        : 0x%08lX\n", eth->regs.hash0 );
640 
    PRINTF( "HASH1        : 0x%08lX\n", eth->regs.hash1 );
641 696 ivang 
}
642 
/* ========================================================================= */
643 
 
644 
 
645 
/*
646 
  Read a register
647 
*/
648 1359 nogj 
uint32_t eth_read32( oraddr_t addr, void *dat )
649 696 ivang 
{
650 1372 nogj 
    struct eth_device *eth = dat;
651 696 ivang 
 
652 
    switch( addr ) {
653 
    case ETH_MODER: return eth->regs.moder;
654 
    case ETH_INT_SOURCE: return eth->regs.int_source;
655 
    case ETH_INT_MASK: return eth->regs.int_mask;
656 
    case ETH_IPGT: return eth->regs.ipgt;
657 
    case ETH_IPGR1: return eth->regs.ipgr1;
658 
    case ETH_IPGR2: return eth->regs.ipgr2;
659 
    case ETH_PACKETLEN: return eth->regs.packetlen;
660 
    case ETH_COLLCONF: return eth->regs.collconf;
661 
    case ETH_TX_BD_NUM: return eth->regs.tx_bd_num;
662 
    case ETH_CTRLMODER: return eth->regs.controlmoder;
663 
    case ETH_MIIMODER: return eth->regs.miimoder;
664 
    case ETH_MIICOMMAND: return eth->regs.miicommand;
665 
    case ETH_MIIADDRESS: return eth->regs.miiaddress;
666 
    case ETH_MIITX_DATA: return eth->regs.miitx_data;
667 
    case ETH_MIIRX_DATA: return eth->regs.miirx_data;
668 
    case ETH_MIISTATUS: return eth->regs.miistatus;
669 
    case ETH_MAC_ADDR0: return (((unsigned long)eth->mac_address[3]) << 24) |
670 702 ivang 
                               (((unsigned long)eth->mac_address[2]) << 16) |
671 
                               (((unsigned long)eth->mac_address[1]) << 8) |
672 
                                 (unsigned long)eth->mac_address[0];
673 696 ivang 
    case ETH_MAC_ADDR1: return (((unsigned long)eth->mac_address[5]) << 8) |
674 702 ivang 
                                 (unsigned long)eth->mac_address[4];
675 744 simons 
    case ETH_HASH0: return eth->regs.hash0;
676 
    case ETH_HASH1: return eth->regs.hash1;
677 702 ivang 
    /*case ETH_DMA_RX_TX: return eth_rx( eth );*/
678 696 ivang 
    }
679 
 
680 
    if ( (addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE) )
681 702 ivang 
        return eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4];
682 696 ivang 
 
683 1350 nogj 
    PRINTF( "eth_read32( 0x%"PRIxADDR" ): Illegal address\n",
684 
            addr + eth->baseaddr );
685 696 ivang 
    return 0;
686 
}
687 
/* ========================================================================= */
688 
 
689 
 
690 
/*
691 
  Write a register
692 
*/
693 1359 nogj 
void eth_write32( oraddr_t addr, uint32_t value, void *dat )
694 696 ivang 
{
695 1372 nogj 
    struct eth_device *eth = dat;
696 
 
697 696 ivang 
    switch( addr ) {
698 1372 nogj 
    case ETH_MODER:
699 
 
700 
        if ( !TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN) &&
701 
             TEST_FLAG( value, ETH_MODER, RXEN) )
702 1390 nogj 
            SCHED_ADD( eth_controller_rx_clock, dat, 1 );
703 1372 nogj 
        else if ( !TEST_FLAG( value, ETH_MODER, RXEN) )
704 
            SCHED_FIND_REMOVE( eth_controller_rx_clock, dat);
705 
 
706 
        if ( !TEST_FLAG( eth->regs.moder, ETH_MODER, TXEN) &&
707 
             TEST_FLAG( value, ETH_MODER, TXEN) )
708 1390 nogj 
            SCHED_ADD( eth_controller_tx_clock, dat, 1 );
709 1372 nogj 
        else if ( !TEST_FLAG( value, ETH_MODER, TXEN) )
710 
            SCHED_FIND_REMOVE( eth_controller_tx_clock, dat);
711 
 
712 
        eth->regs.moder = value;
713 
 
714 
        if (TEST_FLAG(value, ETH_MODER, RST))
715 
            eth_reset( dat );
716 
        return;
717 744 simons 
    case ETH_INT_SOURCE: eth->regs.int_source &= ~value; return;
718 696 ivang 
    case ETH_INT_MASK: eth->regs.int_mask = value; return;
719 
    case ETH_IPGT: eth->regs.ipgt = value; return;
720 
    case ETH_IPGR1: eth->regs.ipgr1 = value; return;
721 
    case ETH_IPGR2: eth->regs.ipgr2 = value; return;
722 
    case ETH_PACKETLEN: eth->regs.packetlen = value; return;
723 
    case ETH_COLLCONF: eth->regs.collconf = value; return;
724 
    case ETH_TX_BD_NUM: eth_write_tx_bd_num( eth, value ); return;
725 
    case ETH_CTRLMODER: eth->regs.controlmoder = value; return;
726 
    case ETH_MIIMODER: eth->regs.miimoder = value; return;
727 
    case ETH_MIICOMMAND: eth->regs.miicommand = value; return;
728 
    case ETH_MIIADDRESS: eth->regs.miiaddress = value; return;
729 
    case ETH_MIITX_DATA: eth->regs.miitx_data = value; return;
730 
    case ETH_MIIRX_DATA: eth->regs.miirx_data = value; return;
731 
    case ETH_MIISTATUS: eth->regs.miistatus = value; return;
732 
    case ETH_MAC_ADDR0:
733 702 ivang 
        eth->mac_address[0] = value & 0xFF;
734 
        eth->mac_address[1] = (value >> 8) & 0xFF;
735 
        eth->mac_address[2] = (value >> 16) & 0xFF;
736 
        eth->mac_address[3] = (value >> 24) & 0xFF;
737 
        return;
738 696 ivang 
    case ETH_MAC_ADDR1:
739 702 ivang 
        eth->mac_address[4] = value & 0xFF;
740 
        eth->mac_address[5] = (value >> 8) & 0xFF;
741 
        return;
742 744 simons 
    case ETH_HASH0: eth->regs.hash0 = value; return;
743 
    case ETH_HASH1: eth->regs.hash1 = value; return;
744 702 ivang 
 
745 
    /*case ETH_DMA_RX_TX: eth_tx( eth, value ); return;*/
746 696 ivang 
    }
747 
 
748 
    if ( (addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE) ) {
749 702 ivang 
        eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4] = value;
750 
        return;
751 696 ivang 
    }
752 
 
753 1350 nogj 
    PRINTF( "eth_write32( 0x%"PRIxADDR" ): Illegal address\n",
754 
            addr + eth->baseaddr );
755 696 ivang 
    return;
756 
}
757 
/* ========================================================================= */
758 
 
759 
 
760 889 ivang 
/*
761 
 *   VAPI connection to outside
762 
 */
763 1366 nogj 
static void eth_vapi_read (unsigned long id, unsigned long data, void *dat)
764 889 ivang 
{
765 
    unsigned long which;
766 1372 nogj 
    struct eth_device *eth = dat;
767 889 ivang 
 
768 1372 nogj 
    which = id - eth->base_vapi_id;
769 
 
770 1463 nogj 
    TRACE( "ETH: id %08lx, data %08lx\n", id, data );
771 889 ivang 
 
772 
    if ( !eth ) {
773 1463 nogj 
        TRACE( "ETH: VAPI ID %08lx is not ours!\n", id );
774 889 ivang 
        return;
775 
    }
776 
 
777 
    switch( which ) {
778 
    case ETH_VAPI_DATA:
779 
        break;
780 
    case ETH_VAPI_CTRL:
781 
        break;
782 
    }
783 
}
784 
/* ========================================================================= */
785 
 
786 
 
787 702 ivang 
/* When TX_BD_NUM is written, also reset current RX BD index */
788 
void eth_write_tx_bd_num( struct eth_device *eth, unsigned long value )
789 
{
790 1018 simons 
    eth->regs.tx_bd_num = value & 0xFF;
791 
    eth->rx.bd_index = eth->regs.tx_bd_num << 1;
792 702 ivang 
}
793 1372 nogj 
 
794 702 ivang 
/* ========================================================================= */
795 
 
796 1372 nogj 
/*-----------------------------------------------[ Ethernet configuration ]---*/
797 
void eth_baseaddr(union param_val val, void *dat)
798 696 ivang 
{
799 1372 nogj 
  struct eth_device *eth = dat;
800 
  eth->baseaddr = val.addr_val;
801 696 ivang 
}
802 889 ivang 
 
803 1372 nogj 
void eth_dma(union param_val val, void *dat)
804 889 ivang 
{
805 1372 nogj 
  struct eth_device *eth = dat;
806 
  eth->dma = val.addr_val;
807 889 ivang 
}
808 1358 nogj 
 
809 1372 nogj 
void eth_rtx_type(union param_val val, void *dat)
810 
{
811 
  struct eth_device *eth = dat;
812 
  eth->rtx_type = val.int_val;
813 1358 nogj 
}
814 
 
815 1372 nogj 
void eth_rx_channel(union param_val val, void *dat)
816 
{
817 
  struct eth_device *eth = dat;
818 
  eth->rx_channel = val.int_val;
819 1358 nogj 
}
820 
 
821 1372 nogj 
void eth_tx_channel(union param_val val, void *dat)
822 
{
823 
  struct eth_device *eth = dat;
824 
  eth->tx_channel = val.int_val;
825 1358 nogj 
}
826 
 
827 1372 nogj 
void eth_rxfile(union param_val val, void *dat)
828 
{
829 
  struct eth_device *eth = dat;
830 
  if(!(eth->rxfile = strdup(val.str_val))) {
831 
    fprintf(stderr, "Peripheral Ethernet: Run out of memory\n");
832 
    exit(-1);
833 
  }
834 1358 nogj 
}
835 
 
836 
void eth_txfile(union param_val val, void *dat)
837 
{
838 1372 nogj 
  struct eth_device *eth = dat;
839 
  if(!(eth->txfile = strdup(val.str_val))) {
840 
    fprintf(stderr, "Peripheral Ethernet: Run out of memory\n");
841 
    exit(-1);
842 
  }
843 1358 nogj 
}
844 
 
845 
void eth_sockif(union param_val val, void *dat)
846 
{
847 1372 nogj 
  struct eth_device *eth = dat;
848 
  if(!(eth->sockif = strdup(val.str_val))) {
849 
    fprintf(stderr, "Peripheral Ethernet: Run out of memory\n");
850 
    exit(-1);
851 
  }
852 1358 nogj 
}
853 
 
854 
void eth_irq(union param_val val, void *dat)
855 
{
856 1372 nogj 
  struct eth_device *eth = dat;
857 
  eth->mac_int = val.int_val;
858 1358 nogj 
}
859 
 
860 
void eth_vapi_id(union param_val val, void *dat)
861 
{
862 1372 nogj 
  struct eth_device *eth = dat;
863 
  eth->base_vapi_id = val.int_val;
864 1358 nogj 
}
865 
 
866 1461 nogj 
void eth_enabled(union param_val val, void *dat)
867 
{
868 
  struct eth_device *eth = dat;
869 
  eth->enabled = val.int_val;
870 
}
871 
 
872 1372 nogj 
void *eth_sec_start(void)
873 
{
874 
  struct eth_device *new = malloc(sizeof(struct eth_device));
875 
 
876 
  if(!new) {
877 
    fprintf(stderr, "Peripheral Eth: Run out of memory\n");
878 
    exit(-1);
879 
  }
880 
 
881 1461 nogj 
  new->enabled = 1;
882 
 
883 1372 nogj 
  return new;
884 
}
885 
 
886 
void eth_sec_end(void *dat)
887 
{
888 
  struct eth_device *eth = dat;
889 1486 nogj 
  struct mem_ops ops;
890 1372 nogj 
 
891 1461 nogj 
  if(!eth->enabled) {
892 
    free(dat);
893 
    return;
894 
  }
895 
 
896 1486 nogj 
  memset(&ops, 0, sizeof(struct mem_ops));
897 
 
898 
  ops.readfunc32 = eth_read32;
899 
  ops.writefunc32 = eth_write32;
900 
  ops.read_dat32 = dat;
901 
  ops.write_dat32 = dat;
902 
 
903 
  /* FIXME: Correct delay? */
904 
  ops.delayr = 2;
905 
  ops.delayw = 2;
906 
  reg_mem_area( eth->baseaddr, ETH_ADDR_SPACE, 0, &ops );
907 1372 nogj 
  reg_sim_stat( eth_status, dat );
908 
  reg_sim_reset( eth_reset, dat );
909 
}
910 
 
911 1358 nogj 
void reg_ethernet_sec(void)
912 
{
913 1372 nogj 
  struct config_section *sec = reg_config_sec("ethernet", eth_sec_start, eth_sec_end);
914 1358 nogj 
 
915 
  reg_config_param(sec, "irq", paramt_int, eth_irq);
916 1461 nogj 
  reg_config_param(sec, "enabled", paramt_int, eth_enabled);
917 1358 nogj 
  reg_config_param(sec, "baseaddr", paramt_int, eth_baseaddr);
918 
  reg_config_param(sec, "dma", paramt_int, eth_dma);
919 
  reg_config_param(sec, "rtx_type", paramt_int, eth_rtx_type);
920 
  reg_config_param(sec, "rx_channel", paramt_int, eth_rx_channel);
921 
  reg_config_param(sec, "tx_channel", paramt_int, eth_tx_channel);
922 
  reg_config_param(sec, "rxfile", paramt_str, eth_rxfile);
923 
  reg_config_param(sec, "txfile", paramt_str, eth_txfile);
924 
  reg_config_param(sec, "sockif", paramt_str, eth_sockif);
925 
  reg_config_param(sec, "vapi_id", paramt_int, eth_vapi_id);
926 
}

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