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[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [peripheral/] [gpio.c] - Blame information for rev 1778

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Line No. Rev Author Line
1 444 erez
/* gpio.h -- GPIO code simulation
2
   Copyright (C) 2001 Erez Volk, erez@mailandnews.comopencores.org
3
 
4
   This file is part of OpenRISC 1000 Architectural Simulator.
5
 
6
   This program is free software; you can redistribute it and/or modify
7
   it under the terms of the GNU General Public License as published by
8
   the Free Software Foundation; either version 2 of the License, or
9
   (at your option) any later version.
10
 
11
   This program is distributed in the hope that it will be useful,
12
   but WITHOUT ANY WARRANTY; without even the implied warranty of
13
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
   GNU General Public License for more details.
15
 
16
   You should have received a copy of the GNU General Public License
17
   along with this program; if not, write to the Free Software
18
   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19
*/
20 1308 phoenix
#include <string.h>
21 444 erez
 
22 1350 nogj
#include "config.h"
23
 
24
#ifdef HAVE_INTTYPES_H
25
#include <inttypes.h>
26
#endif
27
 
28
#include "port.h"
29
#include "arch.h"
30 1308 phoenix
#include "abstract.h"
31 444 erez
#include "gpio.h"
32
#include "gpio_i.h"
33
#include "sim-config.h"
34
#include "pic.h"
35
#include "vapi.h"
36 1308 phoenix
#include "debug.h"
37 1374 nogj
#include "sched.h"
38 444 erez
 
39 1489 nogj
DEFAULT_DEBUG_CHANNEL(gpio);
40
 
41 1366 nogj
static void gpio_vapi_read( unsigned long id, unsigned long data, void *dat );
42 1359 nogj
static uint32_t gpio_read32( oraddr_t addr, void *dat );
43
static void gpio_write32( oraddr_t addr, uint32_t value, void *dat );
44 444 erez
 
45 1374 nogj
static void gpio_external_clock( unsigned long value, struct gpio_device *gpio );
46 444 erez
static void gpio_device_clock( struct gpio_device *gpio );
47 1564 nogj
static void gpio_clock( void *dat );
48 444 erez
 
49
/* Initialize all parameters and state */
50 1374 nogj
void gpio_reset( void *dat )
51 444 erez
{
52 1374 nogj
  struct gpio_device *gpio = dat;
53 444 erez
 
54 1374 nogj
  if ( gpio->baseaddr != 0 ) {
55
    /* Possibly connect to VAPI */
56
    if ( gpio->base_vapi_id ) {
57
      vapi_install_multi_handler( gpio->base_vapi_id, GPIO_NUM_VAPI_IDS, gpio_vapi_read, dat );
58 444 erez
    }
59
  }
60 1564 nogj
  SCHED_ADD(gpio_clock, dat, 1);
61 444 erez
}
62
 
63
 
64
/* Dump status */
65 1374 nogj
void gpio_status( void *dat )
66 444 erez
{
67 1374 nogj
  struct gpio_device *gpio = dat;
68 444 erez
 
69 1374 nogj
  if ( gpio->baseaddr == 0 )
70
    return;
71 444 erez
 
72 1374 nogj
  PRINTF( "\nGPIO at 0x%"PRIxADDR":\n", gpio->baseaddr );
73
  PRINTF( "RGPIO_IN     : 0x%08lX\n", gpio->curr.in );
74
  PRINTF( "RGPIO_OUT    : 0x%08lX\n", gpio->curr.out );
75
  PRINTF( "RGPIO_OE     : 0x%08lX\n", gpio->curr.oe );
76
  PRINTF( "RGPIO_INTE   : 0x%08lX\n", gpio->curr.inte );
77
  PRINTF( "RGPIO_PTRIG  : 0x%08lX\n", gpio->curr.ptrig );
78
  PRINTF( "RGPIO_AUX    : 0x%08lX\n", gpio->curr.aux );
79
  PRINTF( "RGPIO_CTRL   : 0x%08lX\n", gpio->curr.ctrl );
80
  PRINTF( "RGPIO_INTS   : 0x%08lX\n", gpio->curr.ints );
81 444 erez
}
82
 
83
 
84
/* Wishbone read */
85 1359 nogj
uint32_t gpio_read32( oraddr_t addr, void *dat )
86 444 erez
{
87 1374 nogj
  struct gpio_device *gpio = dat;
88 444 erez
 
89
  switch( addr ) {
90 502 erez
  case RGPIO_IN: return gpio->curr.in | gpio->curr.out;
91 444 erez
  case RGPIO_OUT: return gpio->curr.out;
92
  case RGPIO_OE: return gpio->curr.oe;
93
  case RGPIO_INTE: return gpio->curr.inte;
94
  case RGPIO_PTRIG: return gpio->curr.ptrig;
95
  case RGPIO_AUX: return gpio->curr.aux;
96
  case RGPIO_CTRL: return gpio->curr.ctrl;
97 502 erez
  case RGPIO_INTS: return gpio->curr.ints;
98 444 erez
  }
99 1374 nogj
 
100
  return 0;
101 444 erez
}
102
 
103
 
104
/* Wishbone write */
105 1359 nogj
void gpio_write32( oraddr_t addr, uint32_t value, void *dat )
106 444 erez
{
107 1374 nogj
  struct gpio_device *gpio = dat;
108 444 erez
 
109
  switch( addr ) {
110 1489 nogj
  case RGPIO_IN: TRACE( "GPIO: Cannot write to RGPIO_IN\n" ); break;
111 444 erez
  case RGPIO_OUT: gpio->next.out = value; break;
112
  case RGPIO_OE: gpio->next.oe = value; break;
113
  case RGPIO_INTE: gpio->next.inte = value; break;
114
  case RGPIO_PTRIG: gpio->next.ptrig = value; break;
115
  case RGPIO_AUX: gpio->next.aux = value; break;
116
  case RGPIO_CTRL: gpio->next.ctrl = value; break;
117 502 erez
  case RGPIO_INTS: gpio->next.ints = value; break;
118 444 erez
  }
119
}
120
 
121
 
122
/* Input from "outside world" */
123 1366 nogj
void gpio_vapi_read( unsigned long id, unsigned long data, void *dat )
124 444 erez
{
125
  unsigned which;
126 1374 nogj
  struct gpio_device *gpio = dat;
127 444 erez
 
128 1489 nogj
  TRACE( "GPIO: id %08lx, data %08lx\n", id, data );
129 444 erez
 
130 1374 nogj
  which = id - gpio->base_vapi_id;
131 444 erez
 
132
  switch( which ) {
133 477 erez
  case GPIO_VAPI_DATA:
134 1489 nogj
    TRACE( "GPIO: Next input from VAPI = 0x%08lx (RGPIO_OE = 0x%08lx)\n",
135 1350 nogj
           data, gpio->next.oe );
136 477 erez
    gpio->next.in = data;
137
    break;
138
  case GPIO_VAPI_AUX:
139
    gpio->auxiliary_inputs = data;
140
    break;
141
  case GPIO_VAPI_RGPIO_OE:
142
    gpio->next.oe = data;
143
    break;
144
  case GPIO_VAPI_RGPIO_INTE:
145
    gpio->next.inte = data;
146
    break;
147
  case GPIO_VAPI_RGPIO_PTRIG:
148
    gpio->next.ptrig = data;
149
    break;
150
  case GPIO_VAPI_RGPIO_AUX:
151
    gpio->next.aux = data;
152
    break;
153
  case GPIO_VAPI_RGPIO_CTRL:
154
    gpio->next.ctrl = data;
155
    break;
156
  case GPIO_VAPI_CLOCK:
157 1374 nogj
    gpio_external_clock( data, gpio );
158 477 erez
    break;
159 444 erez
  }
160 1564 nogj
}
161 444 erez
 
162 1564 nogj
/* System Clock. */
163
static void gpio_clock( void *dat )
164
{
165
  struct gpio_device *gpio = dat;
166
 
167 1374 nogj
  /* Clock the device */
168
  if ( !(gpio->curr.ctrl & RGPIO_CTRL_ECLK) )
169
    gpio_device_clock( gpio );
170 1564 nogj
  SCHED_ADD(gpio_clock, dat, 1);
171 444 erez
}
172
 
173
/* External Clock. */
174 1374 nogj
static void gpio_external_clock( unsigned long value, struct gpio_device *gpio )
175 444 erez
{
176 1374 nogj
  int use_external_clock = ((gpio->curr.ctrl & RGPIO_CTRL_ECLK) == RGPIO_CTRL_ECLK);
177
  int negative_edge = ((gpio->curr.ctrl & RGPIO_CTRL_NEC) == RGPIO_CTRL_NEC);
178 444 erez
 
179 477 erez
  /* "Normalize" clock value */
180 444 erez
  value = (value != 0);
181
 
182 1374 nogj
  gpio->next.external_clock = value;
183 444 erez
 
184 1374 nogj
  if ( use_external_clock && (gpio->next.external_clock != gpio->curr.external_clock) && (value != negative_edge) )
185
    /* Make sure that in vapi_read, we don't clock the device */
186
    if ( gpio->curr.ctrl & RGPIO_CTRL_ECLK )
187 444 erez
      gpio_device_clock( gpio );
188
}
189
 
190 1374 nogj
/* Report an interrupt to the sim */
191
void gpio_do_int( void *dat )
192
{
193
  struct gpio_device *gpio = dat;
194 477 erez
 
195 1374 nogj
  report_interrupt( gpio->irq );
196
}
197
 
198 444 erez
/* Clock as handld by one device. */
199 1374 nogj
static void gpio_device_clock( struct gpio_device *gpio )
200 444 erez
{
201 445 erez
  /* Calculate new inputs and outputs */
202
  gpio->next.in &= ~gpio->next.oe; /* Only input bits */
203
  /* Replace requested output bits with aux input */
204
  gpio->next.out = (gpio->next.out & ~gpio->next.aux) | (gpio->auxiliary_inputs & gpio->next.aux);
205
  gpio->next.out &= gpio->next.oe; /* Only output-enabled bits */
206
 
207 444 erez
  /* If any outputs changed, notify the world (i.e. vapi) */
208 477 erez
  if ( gpio->next.out != gpio->curr.out ) {
209 1489 nogj
    TRACE( "GPIO: New output 0x%08lx, RGPIO_OE = 0x%08lx\n", gpio->next.out,
210 1350 nogj
           gpio->next.oe );
211 477 erez
    if ( gpio->base_vapi_id )
212
      vapi_send( gpio->base_vapi_id + GPIO_VAPI_DATA, gpio->next.out );
213
  }
214 444 erez
 
215 445 erez
  /* If any inputs changed and interrupt enabled, generate interrupt */
216 477 erez
  if ( gpio->next.in != gpio->curr.in ) {
217 1489 nogj
    TRACE( "GPIO: New input 0x%08lx\n", gpio->next.in );
218 477 erez
 
219
    if ( gpio->next.ctrl & RGPIO_CTRL_INTE ) {
220
      unsigned changed_bits = gpio->next.in ^ gpio->curr.in; /* inputs that have changed */
221
      unsigned set_bits = changed_bits & gpio->next.in; /* inputs that have been set */
222
      unsigned cleared_bits = changed_bits & gpio->curr.in; /* inputs that have been cleared */
223
      unsigned relevant_bits = (gpio->next.ptrig & set_bits) | (~gpio->next.ptrig & cleared_bits);
224
 
225
      if ( relevant_bits & gpio->next.inte ) {
226 1489 nogj
        TRACE( "GPIO: Reporting interrupt %d\n", gpio->irq );
227 502 erez
        gpio->next.ctrl |= RGPIO_CTRL_INTS;
228
        gpio->next.ints |= relevant_bits & gpio->next.inte;
229 1374 nogj
        /* Since we can't report an interrupt during a readmem/writemem
230
         * schedule the scheduler to do it.  Read the comment above
231
         * report_interrupt in pic/pic.c */
232 1390 nogj
        SCHED_ADD( gpio_do_int, gpio, 1 );
233 477 erez
      }
234 444 erez
    }
235
  }
236
 
237
  /* Switch to values for next clock */
238
  memcpy( &(gpio->curr), &(gpio->next), sizeof(gpio->curr) );
239
}
240 1358 nogj
 
241
/*---------------------------------------------------[ GPIO configuration ]---*/
242
void gpio_baseaddr(union param_val val, void *dat)
243
{
244 1374 nogj
  struct gpio_device *gpio = dat;
245
  gpio->baseaddr = val.addr_val;
246 1358 nogj
}
247
 
248
void gpio_irq(union param_val val, void *dat)
249
{
250 1374 nogj
  struct gpio_device *gpio = dat;
251
  gpio->irq = val.int_val;
252 1358 nogj
}
253
 
254
void gpio_base_vapi_id(union param_val val, void *dat)
255
{
256 1374 nogj
  struct gpio_device *gpio = dat;
257
  gpio->base_vapi_id = val.int_val;
258 1358 nogj
}
259
 
260 1461 nogj
void gpio_enabled(union param_val val, void *dat)
261
{
262
  struct gpio_device *gpio = dat;
263
  gpio->enabled = val.int_val;
264
}
265
 
266 1374 nogj
void *gpio_sec_start(void)
267
{
268
  struct gpio_device *new = malloc(sizeof(struct gpio_device));
269
 
270
  if(!new) {
271 1383 nogj
    fprintf(stderr, "Peripheral gpio: Run out of memory\n");
272 1374 nogj
    exit(-1);
273
  }
274
 
275
  new->auxiliary_inputs = 0;
276
  memset(&new->curr, 0, sizeof(new->curr));
277
  memset(&new->next, 0, sizeof(new->next));
278
 
279 1461 nogj
  new->enabled = 1;
280
 
281 1374 nogj
  return new;
282
}
283
 
284
void gpio_sec_end(void *dat)
285
{
286
  struct gpio_device *gpio = dat;
287 1486 nogj
  struct mem_ops ops;
288 1374 nogj
 
289 1461 nogj
  if(!gpio->enabled) {
290
    free(dat);
291
    return;
292
  }
293
 
294 1486 nogj
  memset(&ops, 0, sizeof(struct mem_ops));
295
 
296
  ops.readfunc32 = gpio_read32;
297
  ops.writefunc32 = gpio_write32;
298
  ops.write_dat32 = dat;
299
  ops.read_dat32 = dat;
300
 
301
  /* FIXME: Correct delays? */
302
  ops.delayr = 2;
303
  ops.delayw = 2;
304
 
305 1374 nogj
  /* Register memory range */
306 1486 nogj
  reg_mem_area( gpio->baseaddr, GPIO_ADDR_SPACE, 0, &ops );
307 1374 nogj
 
308
  reg_sim_reset(gpio_reset, dat);
309
  reg_sim_stat(gpio_status, dat);
310
}
311
 
312 1358 nogj
void reg_gpio_sec(void)
313
{
314 1383 nogj
  struct config_section *sec = reg_config_sec("gpio", gpio_sec_start, gpio_sec_end);
315 1358 nogj
 
316 1461 nogj
  reg_config_param(sec, "enabled", paramt_int, gpio_enabled);
317 1358 nogj
  reg_config_param(sec, "baseaddr", paramt_addr, gpio_baseaddr);
318
  reg_config_param(sec, "irq", paramt_int, gpio_irq);
319
  reg_config_param(sec, "base_vapi_id", paramt_int, gpio_base_vapi_id);
320
}

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