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/* mc.c -- Simulation of Memory Controller
         Copyright (C) 2001 by Marko Mlinar, markom@opencores.org
 
         This file is part of OpenRISC 1000 Architectural Simulator.
 
         This program is free software; you can redistribute it and/or modify
         it under the terms of the GNU General Public License as published by
         the Free Software Foundation; either version 2 of the License, or
         (at your option) any later version.
 
         This program is distributed in the hope that it will be useful,
         but WITHOUT ANY WARRANTY; without even the implied warranty of
         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.    See the
         GNU General Public License for more details.
 
         You should have received a copy of the GNU General Public License
         along with this program; if not, write to the Free Software
         Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
 
/* Enable memory controller, via:
  section mc
    enable = 1
    POC = 0x13243545
  end
 
   Limitations:
    - memory refresh is not simulated
*/
 
#include <string.h>
 
#include "mc.h"
#include "abstract.h"
#include "sim-config.h"
#include "debug.h"
 
extern struct dev_memarea *dev_list;
 
static struct mc mc;
 
void set_csc_tms (int cs, unsigned long csc, unsigned long tms) {
  struct dev_memarea *mem_dev = dev_list;
 
  while (mem_dev) {
    if (mem_dev->chip_select == cs) {
      mem_dev->addr_mask = mc.ba_mask << 22;
      mem_dev->addr_compare = ((csc >> MC_CSC_SEL_OFFSET) /* & 0xff*/) << 22;
      mem_dev->valid = (csc >> MC_CSC_EN_OFFSET) & 0x01;
 
      if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {
        mem_dev->delayr = (tms & 0xff) + ((tms >> 8) & 0x0f);
        mem_dev->delayw = ((tms >> 12)  & 0x0f) + ((tms >> 16) & 0x0f) + ((tms >> 20) & 0x3f);
      } else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {
        mem_dev->delayr = 3 + ((tms >> 4) & 0x03);
        mem_dev->delayw = 3 + ((tms >> 4) & 0x03);
      } else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SSRAM) {
        mem_dev->delayr = 2;
        mem_dev->delayw = 2;
      } else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
        mem_dev->delayr = 2;
        mem_dev->delayw = 2;
      }
      return;
    }
    mem_dev = mem_dev->next;
  }
}
 
/* Set a specific MC register with value. */
void mc_write_word(unsigned long addr, unsigned long value)
{
        int chipsel;
 
        debug(5, "mc_write_word(%x,%08x)\n", addr, (unsigned)value);
 
  addr -= config.mc.baseaddr;
 
        switch (addr) {
          case MC_CSR:
            mc.csr = value;
            break;
          case MC_POC:
            fprintf (stderr, "warning: write to MC's POC register!");
            break;
          case MC_BA_MASK:
            mc.ba_mask = value & MC_BA_MASK_VALID;
      for (chipsel = 0; chipsel < N_CE; chipsel++)
        set_csc_tms (chipsel, mc.csc[chipsel], mc.tms[chipsel]);
            break;
                default:
                  if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {
                    addr -= MC_CSC(0);
                    if ((addr >> 2) & 1)
                      mc.tms[addr >> 3] = value;
                    else
                      mc.csc[addr >> 3] = value;
 
                    set_csc_tms (addr >> 3, mc.csc[addr >> 3], mc.tms[addr >> 3]);
                    break;
                  } else
                        debug(1, "write out of range (addr %x)\n", addr + config.mc.baseaddr);
        }
}
 
/* Read a specific MC register. */
unsigned long mc_read_word(unsigned long addr)
{
        unsigned long value = 0;
 
        debug(5, "mc_read_word(%x)", addr);
 
  addr -= config.mc.baseaddr;
 
        switch (addr) {
          case MC_CSR:
            value = mc.csr;
            break;
          case MC_POC:
            value = mc.poc;
            break;
          case MC_BA_MASK:
            value = mc.ba_mask;
            break;
                default:
                  if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {
                    addr -= MC_CSC(0);
                    if ((addr >> 2) & 1)
                      value = mc.tms[addr >> 3];
                    else
                      value = mc.csc[addr >> 3];
                  } else
                        debug(1, " read out of range (addr %x)\n", addr + config.mc.baseaddr);
            break;
        }
        debug(5, " value(%x)\n", value);
        return value;
}
 
/* Read POC register and init memory controler regs. */
void mc_reset()
{
  struct dev_memarea *mem_dev = dev_list;
 
  if (config.mc.enabled) {
        PRINTF("Resetting memory controller.\n");
        memset(&mc, 0, sizeof(struct mc));
 
    mc.poc = config.mc.POC;
 
    /* Set CS0 */
    mc.csc[0] = (((config.mc.POC & 0x0c) >> 2) << MC_CSC_MEMTYPE_OFFSET) | ((config.mc.POC & 0x03) << MC_CSC_BW_OFFSET) | 1;
 
    if ((mc.csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {
      mc.tms[0] = MC_TMS_ASYNC_VALID;
    } else if ((mc.csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {
      mc.tms[0] = MC_TMS_SDRAM_VALID;
    } else if ((mc.csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SSRAM) {
      mc.tms[0] = MC_TMS_SSRAM_VALID;
    } else if ((mc.csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
      mc.tms[0] = MC_TMS_SYNC_VALID;
    }
 
    while (mem_dev) {
      mem_dev->valid = 0;
      mem_dev = mem_dev->next;
    }
 
    set_csc_tms (0, mc.csc[0], mc.tms[0]);
 
        register_memoryarea(config.mc.baseaddr, MC_ADDR_SPACE, 4, 1, mc_read_word, mc_write_word);
  }
}
 
inline void mc_clock()
{
}
 
void mc_status()
{
    int i;
 
    PRINTF( "\nMemory Controller at 0x%08lX:\n", config.mc.baseaddr );
    PRINTF( "POC: 0x%08lX\n", mc.poc );
    PRINTF( "BAS: 0x%08lX\n", mc.ba_mask );
    PRINTF( "CSR: 0x%08lX\n", mc.csr );
 
    for (i=0; i<N_CE; i++) {
        PRINTF( "CE %02d -  CSC: 0x%08lX  TMS: 0x%08lX\n", i, mc.csc[i],
               mc.tms[i]);
    }
}

Line No.	Rev	Author	Line
1	239	markom	`/* mc.c -- Simulation of Memory Controller`
2			`Copyright (C) 2001 by Marko Mlinar, markom@opencores.org`
3
4			`This file is part of OpenRISC 1000 Architectural Simulator.`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License as published by`
8			`the Free Software Foundation; either version 2 of the License, or`
9			`(at your option) any later version.`
10
11			`This program is distributed in the hope that it will be useful,`
12			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`GNU General Public License for more details.`
15
16			`You should have received a copy of the GNU General Public License`
17			`along with this program; if not, write to the Free Software`
18			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.`
19			`*/`
20
21			`/* Enable memory controller, via:`
22			`section mc`
23			`enable = 1`
24			`POC = 0x13243545`
25			`end`
26
27	261	markom	`Limitations:`
28			`- memory refresh is not simulated`
29	742	ivang	`*/`
30	239	markom
31	1308	phoenix	`#include <string.h>`
32
33	239	markom	`#include "mc.h"`
34			`#include "abstract.h"`
35	261	markom	`#include "sim-config.h"`
36	1308	phoenix	`#include "debug.h"`
37	261	markom
38	539	simons	`extern struct dev_memarea *dev_list;`
39
40	261	markom	`static struct mc mc;`
41
42	539	simons	`void set_csc_tms (int cs, unsigned long csc, unsigned long tms) {`
43			`struct dev_memarea *mem_dev = dev_list;`
44
45			`while (mem_dev) {`
46			`if (mem_dev->chip_select == cs) {`
47	970	simons	`mem_dev->addr_mask = mc.ba_mask << 22;`
48			`mem_dev->addr_compare = ((csc >> MC_CSC_SEL_OFFSET) /* & 0xff*/) << 22;`
49	543	simons	`mem_dev->valid = (csc >> MC_CSC_EN_OFFSET) & 0x01;`
50	539	simons
51			`if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {`
52			`mem_dev->delayr = (tms & 0xff) + ((tms >> 8) & 0x0f);`
53			`mem_dev->delayw = ((tms >> 12) & 0x0f) + ((tms >> 16) & 0x0f) + ((tms >> 20) & 0x3f);`
54			`} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {`
55			`mem_dev->delayr = 3 + ((tms >> 4) & 0x03);`
56			`mem_dev->delayw = 3 + ((tms >> 4) & 0x03);`
57			`} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SSRAM) {`
58			`mem_dev->delayr = 2;`
59			`mem_dev->delayw = 2;`
60			`} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {`
61			`mem_dev->delayr = 2;`
62			`mem_dev->delayw = 2;`
63			`}`
64	543	simons	`return;`
65	539	simons	`}`
66			`mem_dev = mem_dev->next;`
67			`}`
68	261	markom	`}`
69
70			`/* Set a specific MC register with value. */`
71			`void mc_write_word(unsigned long addr, unsigned long value)`
72			`{`
73			`int chipsel;`
74
75	344	markom	`debug(5, "mc_write_word(%x,%08x)\n", addr, (unsigned)value);`
76	261	markom
77			`addr -= config.mc.baseaddr;`
78
79			`switch (addr) {`
80			`case MC_CSR:`
81			`mc.csr = value;`
82			`break;`
83			`case MC_POC:`
84			`fprintf (stderr, "warning: write to MC's POC register!");`
85			`break;`
86			`case MC_BA_MASK:`
87	539	simons	`mc.ba_mask = value & MC_BA_MASK_VALID;`
88	543	simons	`for (chipsel = 0; chipsel < N_CE; chipsel++)`
89			`set_csc_tms (chipsel, mc.csc[chipsel], mc.tms[chipsel]);`
90	261	markom	`break;`
91			`default:`
92			`if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {`
93			`addr -= MC_CSC(0);`
94			`if ((addr >> 2) & 1)`
95			`mc.tms[addr >> 3] = value;`
96			`else`
97			`mc.csc[addr >> 3] = value;`
98
99			`set_csc_tms (addr >> 3, mc.csc[addr >> 3], mc.tms[addr >> 3]);`
100			`break;`
101			`} else`
102	344	markom	`debug(1, "write out of range (addr %x)\n", addr + config.mc.baseaddr);`
103	261	markom	`}`
104			`}`
105
106			`/* Read a specific MC register. */`
107			`unsigned long mc_read_word(unsigned long addr)`
108			`{`
109	545	ivang	`unsigned long value = 0;`
110	261	markom
111	545	ivang	`debug(5, "mc_read_word(%x)", addr);`
112	261	markom
113			`addr -= config.mc.baseaddr;`
114
115			`switch (addr) {`
116			`case MC_CSR:`
117			`value = mc.csr;`
118			`break;`
119			`case MC_POC:`
120			`value = mc.poc;`
121			`break;`
122			`case MC_BA_MASK:`
123			`value = mc.ba_mask;`
124			`break;`
125			`default:`
126			`if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {`
127			`addr -= MC_CSC(0);`
128			`if ((addr >> 2) & 1)`
129			`value = mc.tms[addr >> 3];`
130			`else`
131			`value = mc.csc[addr >> 3];`
132			`} else`
133	545	ivang	`debug(1, " read out of range (addr %x)\n", addr + config.mc.baseaddr);`
134	261	markom	`break;`
135			`}`
136	545	ivang	`debug(5, " value(%x)\n", value);`
137	261	markom	`return value;`
138			`}`
139
140			`/* Read POC register and init memory controler regs. */`
141			`void mc_reset()`
142			`{`
143	543	simons	`struct dev_memarea *mem_dev = dev_list;`
144
145	261	markom	`if (config.mc.enabled) {`
146	997	markom	`PRINTF("Resetting memory controller.\n");`
147	261	markom	`memset(&mc, 0, sizeof(struct mc));`
148
149			`mc.poc = config.mc.POC;`
150	539	simons
151			`/* Set CS0 */`
152			`mc.csc[0] = (((config.mc.POC & 0x0c) >> 2) << MC_CSC_MEMTYPE_OFFSET) \| ((config.mc.POC & 0x03) << MC_CSC_BW_OFFSET) \| 1;`
153
154			`if ((mc.csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {`
155			`mc.tms[0] = MC_TMS_ASYNC_VALID;`
156			`} else if ((mc.csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {`
157			`mc.tms[0] = MC_TMS_SDRAM_VALID;`
158			`} else if ((mc.csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SSRAM) {`
159			`mc.tms[0] = MC_TMS_SSRAM_VALID;`
160			`} else if ((mc.csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {`
161			`mc.tms[0] = MC_TMS_SYNC_VALID;`
162			`}`
163
164	543	simons	`while (mem_dev) {`
165			`mem_dev->valid = 0;`
166			`mem_dev = mem_dev->next;`
167			`}`
168
169	539	simons	`set_csc_tms (0, mc.csc[0], mc.tms[0]);`
170
171	970	simons	`register_memoryarea(config.mc.baseaddr, MC_ADDR_SPACE, 4, 1, mc_read_word, mc_write_word);`
172	261	markom	`}`
173			`}`
174
175			`inline void mc_clock()`
176			`{`
177			`}`
178	742	ivang
179			`void mc_status()`
180			`{`
181			`int i;`
182
183	1308	phoenix	`PRINTF( "\nMemory Controller at 0x%08lX:\n", config.mc.baseaddr );`
184			`PRINTF( "POC: 0x%08lX\n", mc.poc );`
185			`PRINTF( "BAS: 0x%08lX\n", mc.ba_mask );`
186			`PRINTF( "CSR: 0x%08lX\n", mc.csr );`
187	742	ivang
188			`for (i=0; i<N_CE; i++) {`
189	1308	phoenix	`PRINTF( "CE %02d - CSC: 0x%08lX TMS: 0x%08lX\n", i, mc.csc[i],`
190			`mc.tms[i]);`
191	742	ivang	`}`
192			`}`

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