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[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [sim.cfg] - Blame information for rev 262

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section memory
  memory_table_file = "simmem.cfg"
  random_seed = 12345
  type = random
end
 
section mc
  enabled = 1
  baseaddr = 0xa0000000
  POC = 0x00000008                 /* Power on configuration register */
end
 
section uart
  enabled = 1
  nuarts = 1
 
  device 0
    baseaddr = 0x80000000
    rxfile = "/tmp/uart0.rx"
    txfile = "/tmp/uart0.tx"
    jitter = -1                     /* async behaviour */
  enddevice
end
 
section dma
  enabled = 1
  ndmas = 1
 
  device 0
    baseaddr = 0x90000000
    irq = 4
  enddevice
end

Line No.	Rev	Author	Line
1	262	markom	`section memory`
2			`memory_table_file = "simmem.cfg"`
3			`random_seed = 12345`
4			`type = random`
5			`end`
6
7	243	markom	`section mc`
8	261	markom	`enabled = 1`
9			`baseaddr = 0xa0000000`
10			`POC = 0x00000008 /* Power on configuration register */`
11	243	markom	`end`
12	261	markom
13			`section uart`
14			`enabled = 1`
15			`nuarts = 1`
16
17			`device 0`
18			`baseaddr = 0x80000000`
19			`rxfile = "/tmp/uart0.rx"`
20			`txfile = "/tmp/uart0.tx"`
21			`jitter = -1 /* async behaviour */`
22			`enddevice`
23			`end`
24
25			`section dma`
26			`enabled = 1`
27			`ndmas = 1`
28
29			`device 0`
30			`baseaddr = 0x90000000`
31			`irq = 4`
32			`enddevice`
33			`end`

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[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [sim.cfg] - Blame information for rev 262