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[/] [or1k/] [tags/] [start/] [gdb-5.0/] [opcodes/] [m32r-opinst.c] - Blame information for rev 1778

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1 106 markom 
/* Semantic operand instances for m32r.
2 
 
3 
THIS FILE IS MACHINE GENERATED WITH CGEN.
4 
 
5 
Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
6 
 
7 
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8 
 
9 
This program is free software; you can redistribute it and/or modify
10 
it under the terms of the GNU General Public License as published by
11 
the Free Software Foundation; either version 2, or (at your option)
12 
any later version.
13 
 
14 
This program is distributed in the hope that it will be useful,
15 
but WITHOUT ANY WARRANTY; without even the implied warranty of
16 
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 
GNU General Public License for more details.
18 
 
19 
You should have received a copy of the GNU General Public License along
20 
with this program; if not, write to the Free Software Foundation, Inc.,
21 
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 
 
23 
*/
24 
 
25 
#include "sysdep.h"
26 
#include "ansidecl.h"
27 
#include "bfd.h"
28 
#include "symcat.h"
29 
#include "m32r-desc.h"
30 
#include "m32r-opc.h"
31 
 
32 
/* Operand references.  */
33 
 
34 
#define INPUT CGEN_OPINST_INPUT
35 
#define OUTPUT CGEN_OPINST_OUTPUT
36 
#define END CGEN_OPINST_END
37 
#define COND_REF CGEN_OPINST_COND_REF
38 
#define OP_ENT(op) CONCAT2 (M32R_OPERAND_,op)
39 
 
40 
static const CGEN_OPINST sfmt_empty_ops[] = {
41 
  { END }
42 
};
43 
 
44 
static const CGEN_OPINST sfmt_add_ops[] = {
45 
  { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
46 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
47 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
48 
  { END }
49 
};
50 
 
51 
static const CGEN_OPINST sfmt_add3_ops[] = {
52 
  { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
53 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
54 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
55 
  { END }
56 
};
57 
 
58 
static const CGEN_OPINST sfmt_and3_ops[] = {
59 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
60 
  { INPUT, "uimm16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 },
61 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
62 
  { END }
63 
};
64 
 
65 
static const CGEN_OPINST sfmt_or3_ops[] = {
66 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
67 
  { INPUT, "ulo16", HW_H_ULO16, CGEN_MODE_UINT, OP_ENT (ULO16), 0, 0 },
68 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
69 
  { END }
70 
};
71 
 
72 
static const CGEN_OPINST sfmt_addi_ops[] = {
73 
  { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
74 
  { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
75 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
76 
  { END }
77 
};
78 
 
79 
static const CGEN_OPINST sfmt_addv_ops[] = {
80 
  { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
81 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
82 
  { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
83 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
84 
  { END }
85 
};
86 
 
87 
static const CGEN_OPINST sfmt_addv3_ops[] = {
88 
  { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
89 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
90 
  { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
91 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
92 
  { END }
93 
};
94 
 
95 
static const CGEN_OPINST sfmt_addx_ops[] = {
96 
  { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
97 
  { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
98 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
99 
  { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
100 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
101 
  { END }
102 
};
103 
 
104 
static const CGEN_OPINST sfmt_bc8_ops[] = {
105 
  { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
106 
  { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, COND_REF },
107 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
108 
  { END }
109 
};
110 
 
111 
static const CGEN_OPINST sfmt_bc24_ops[] = {
112 
  { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
113 
  { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, COND_REF },
114 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
115 
  { END }
116 
};
117 
 
118 
static const CGEN_OPINST sfmt_beq_ops[] = {
119 
  { INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF },
120 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
121 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
122 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
123 
  { END }
124 
};
125 
 
126 
static const CGEN_OPINST sfmt_beqz_ops[] = {
127 
  { INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF },
128 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
129 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
130 
  { END }
131 
};
132 
 
133 
static const CGEN_OPINST sfmt_bl8_ops[] = {
134 
  { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 },
135 
  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
136 
  { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
137 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
138 
  { END }
139 
};
140 
 
141 
static const CGEN_OPINST sfmt_bl24_ops[] = {
142 
  { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 },
143 
  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
144 
  { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
145 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
146 
  { END }
147 
};
148 
 
149 
static const CGEN_OPINST sfmt_bcl8_ops[] = {
150 
  { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
151 
  { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, COND_REF },
152 
  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
153 
  { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, COND_REF },
154 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
155 
  { END }
156 
};
157 
 
158 
static const CGEN_OPINST sfmt_bcl24_ops[] = {
159 
  { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
160 
  { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, COND_REF },
161 
  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
162 
  { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, COND_REF },
163 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
164 
  { END }
165 
};
166 
 
167 
static const CGEN_OPINST sfmt_bra8_ops[] = {
168 
  { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 },
169 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
170 
  { END }
171 
};
172 
 
173 
static const CGEN_OPINST sfmt_bra24_ops[] = {
174 
  { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 },
175 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
176 
  { END }
177 
};
178 
 
179 
static const CGEN_OPINST sfmt_cmp_ops[] = {
180 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
181 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
182 
  { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
183 
  { END }
184 
};
185 
 
186 
static const CGEN_OPINST sfmt_cmpi_ops[] = {
187 
  { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
188 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
189 
  { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
190 
  { END }
191 
};
192 
 
193 
static const CGEN_OPINST sfmt_cmpz_ops[] = {
194 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
195 
  { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
196 
  { END }
197 
};
198 
 
199 
static const CGEN_OPINST sfmt_div_ops[] = {
200 
  { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
201 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
202 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
203 
  { END }
204 
};
205 
 
206 
static const CGEN_OPINST sfmt_jc_ops[] = {
207 
  { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
208 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF },
209 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
210 
  { END }
211 
};
212 
 
213 
static const CGEN_OPINST sfmt_jl_ops[] = {
214 
  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
215 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
216 
  { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
217 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
218 
  { END }
219 
};
220 
 
221 
static const CGEN_OPINST sfmt_jmp_ops[] = {
222 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
223 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
224 
  { END }
225 
};
226 
 
227 
static const CGEN_OPINST sfmt_ld_ops[] = {
228 
  { INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
229 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
230 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
231 
  { END }
232 
};
233 
 
234 
static const CGEN_OPINST sfmt_ld_d_ops[] = {
235 
  { INPUT, "h_memory_add__DFLT_sr_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
236 
  { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
237 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
238 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
239 
  { END }
240 
};
241 
 
242 
static const CGEN_OPINST sfmt_ld_plus_ops[] = {
243 
  { INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
244 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
245 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
246 
  { OUTPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
247 
  { END }
248 
};
249 
 
250 
static const CGEN_OPINST sfmt_ld24_ops[] = {
251 
  { INPUT, "uimm24", HW_H_ADDR, CGEN_MODE_USI, OP_ENT (UIMM24), 0, 0 },
252 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
253 
  { END }
254 
};
255 
 
256 
static const CGEN_OPINST sfmt_ldi8_ops[] = {
257 
  { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
258 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
259 
  { END }
260 
};
261 
 
262 
static const CGEN_OPINST sfmt_ldi16_ops[] = {
263 
  { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
264 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
265 
  { END }
266 
};
267 
 
268 
static const CGEN_OPINST sfmt_lock_ops[] = {
269 
  { INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
270 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
271 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
272 
  { OUTPUT, "h_lock", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
273 
  { END }
274 
};
275 
 
276 
static const CGEN_OPINST sfmt_machi_ops[] = {
277 
  { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
278 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
279 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
280 
  { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
281 
  { END }
282 
};
283 
 
284 
static const CGEN_OPINST sfmt_machi_a_ops[] = {
285 
  { INPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
286 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
287 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
288 
  { OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
289 
  { END }
290 
};
291 
 
292 
static const CGEN_OPINST sfmt_mulhi_ops[] = {
293 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
294 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
295 
  { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
296 
  { END }
297 
};
298 
 
299 
static const CGEN_OPINST sfmt_mulhi_a_ops[] = {
300 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
301 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
302 
  { OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
303 
  { END }
304 
};
305 
 
306 
static const CGEN_OPINST sfmt_mv_ops[] = {
307 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
308 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
309 
  { END }
310 
};
311 
 
312 
static const CGEN_OPINST sfmt_mvfachi_ops[] = {
313 
  { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
314 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
315 
  { END }
316 
};
317 
 
318 
static const CGEN_OPINST sfmt_mvfachi_a_ops[] = {
319 
  { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
320 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
321 
  { END }
322 
};
323 
 
324 
static const CGEN_OPINST sfmt_mvfc_ops[] = {
325 
  { INPUT, "scr", HW_H_CR, CGEN_MODE_USI, OP_ENT (SCR), 0, 0 },
326 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
327 
  { END }
328 
};
329 
 
330 
static const CGEN_OPINST sfmt_mvtachi_ops[] = {
331 
  { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
332 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
333 
  { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
334 
  { END }
335 
};
336 
 
337 
static const CGEN_OPINST sfmt_mvtachi_a_ops[] = {
338 
  { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
339 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
340 
  { OUTPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
341 
  { END }
342 
};
343 
 
344 
static const CGEN_OPINST sfmt_mvtc_ops[] = {
345 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
346 
  { OUTPUT, "dcr", HW_H_CR, CGEN_MODE_USI, OP_ENT (DCR), 0, 0 },
347 
  { END }
348 
};
349 
 
350 
static const CGEN_OPINST sfmt_nop_ops[] = {
351 
  { END }
352 
};
353 
 
354 
static const CGEN_OPINST sfmt_rac_ops[] = {
355 
  { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
356 
  { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
357 
  { END }
358 
};
359 
 
360 
static const CGEN_OPINST sfmt_rac_dsi_ops[] = {
361 
  { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
362 
  { INPUT, "imm1", HW_H_UINT, CGEN_MODE_INT, OP_ENT (IMM1), 0, 0 },
363 
  { OUTPUT, "accd", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCD), 0, 0 },
364 
  { END }
365 
};
366 
 
367 
static const CGEN_OPINST sfmt_rte_ops[] = {
368 
  { INPUT, "h_bbpsw", HW_H_BBPSW, CGEN_MODE_UQI, 0, 0, 0 },
369 
  { INPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
370 
  { INPUT, "h_cr_14", HW_H_CR, CGEN_MODE_USI, 0, 14, 0 },
371 
  { INPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
372 
  { OUTPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
373 
  { OUTPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
374 
  { OUTPUT, "h_psw", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
375 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
376 
  { END }
377 
};
378 
 
379 
static const CGEN_OPINST sfmt_seth_ops[] = {
380 
  { INPUT, "hi16", HW_H_HI16, CGEN_MODE_SI, OP_ENT (HI16), 0, 0 },
381 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
382 
  { END }
383 
};
384 
 
385 
static const CGEN_OPINST sfmt_sll3_ops[] = {
386 
  { INPUT, "simm16", HW_H_SINT, CGEN_MODE_SI, OP_ENT (SIMM16), 0, 0 },
387 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
388 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
389 
  { END }
390 
};
391 
 
392 
static const CGEN_OPINST sfmt_slli_ops[] = {
393 
  { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
394 
  { INPUT, "uimm5", HW_H_UINT, CGEN_MODE_INT, OP_ENT (UIMM5), 0, 0 },
395 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
396 
  { END }
397 
};
398 
 
399 
static const CGEN_OPINST sfmt_st_ops[] = {
400 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
401 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
402 
  { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
403 
  { END }
404 
};
405 
 
406 
static const CGEN_OPINST sfmt_st_d_ops[] = {
407 
  { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
408 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
409 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
410 
  { OUTPUT, "h_memory_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
411 
  { END }
412 
};
413 
 
414 
static const CGEN_OPINST sfmt_stb_ops[] = {
415 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
416 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
417 
  { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
418 
  { END }
419 
};
420 
 
421 
static const CGEN_OPINST sfmt_stb_d_ops[] = {
422 
  { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
423 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
424 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
425 
  { OUTPUT, "h_memory_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
426 
  { END }
427 
};
428 
 
429 
static const CGEN_OPINST sfmt_sth_ops[] = {
430 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
431 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
432 
  { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
433 
  { END }
434 
};
435 
 
436 
static const CGEN_OPINST sfmt_sth_d_ops[] = {
437 
  { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
438 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
439 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
440 
  { OUTPUT, "h_memory_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
441 
  { END }
442 
};
443 
 
444 
static const CGEN_OPINST sfmt_st_plus_ops[] = {
445 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
446 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
447 
  { OUTPUT, "h_memory_new_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
448 
  { OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
449 
  { END }
450 
};
451 
 
452 
static const CGEN_OPINST sfmt_trap_ops[] = {
453 
  { INPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
454 
  { INPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
455 
  { INPUT, "h_psw", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
456 
  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
457 
  { INPUT, "uimm4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM4), 0, 0 },
458 
  { OUTPUT, "h_bbpsw", HW_H_BBPSW, CGEN_MODE_UQI, 0, 0, 0 },
459 
  { OUTPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
460 
  { OUTPUT, "h_cr_14", HW_H_CR, CGEN_MODE_USI, 0, 14, 0 },
461 
  { OUTPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
462 
  { OUTPUT, "h_psw", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
463 
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_SI, 0, 0, 0 },
464 
  { END }
465 
};
466 
 
467 
static const CGEN_OPINST sfmt_unlock_ops[] = {
468 
  { INPUT, "h_lock", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
469 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, COND_REF },
470 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, COND_REF },
471 
  { OUTPUT, "h_lock", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
472 
  { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, COND_REF },
473 
  { END }
474 
};
475 
 
476 
static const CGEN_OPINST sfmt_satb_ops[] = {
477 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
478 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
479 
  { END }
480 
};
481 
 
482 
static const CGEN_OPINST sfmt_sat_ops[] = {
483 
  { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
484 
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF },
485 
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
486 
  { END }
487 
};
488 
 
489 
static const CGEN_OPINST sfmt_sadd_ops[] = {
490 
  { INPUT, "h_accums_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 },
491 
  { INPUT, "h_accums_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
492 
  { OUTPUT, "h_accums_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 },
493 
  { END }
494 
};
495 
 
496 
static const CGEN_OPINST sfmt_macwu1_ops[] = {
497 
  { INPUT, "h_accums_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
498 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
499 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
500 
  { OUTPUT, "h_accums_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
501 
  { END }
502 
};
503 
 
504 
static const CGEN_OPINST sfmt_mulwu1_ops[] = {
505 
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
506 
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
507 
  { OUTPUT, "h_accums_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
508 
  { END }
509 
};
510 
 
511 
static const CGEN_OPINST sfmt_sc_ops[] = {
512 
  { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
513 
  { END }
514 
};
515 
 
516 
#undef INPUT
517 
#undef OUTPUT
518 
#undef END
519 
#undef COND_REF
520 
#undef OP_ENT
521 
 
522 
/* Operand instance lookup table.  */
523 
 
524 
static const CGEN_OPINST *m32r_cgen_opinst_table[MAX_INSNS] = {
525 
  0,
526 
  & sfmt_add_ops[0],
527 
  & sfmt_add3_ops[0],
528 
  & sfmt_add_ops[0],
529 
  & sfmt_and3_ops[0],
530 
  & sfmt_add_ops[0],
531 
  & sfmt_or3_ops[0],
532 
  & sfmt_add_ops[0],
533 
  & sfmt_and3_ops[0],
534 
  & sfmt_addi_ops[0],
535 
  & sfmt_addv_ops[0],
536 
  & sfmt_addv3_ops[0],
537 
  & sfmt_addx_ops[0],
538 
  & sfmt_bc8_ops[0],
539 
  & sfmt_bc24_ops[0],
540 
  & sfmt_beq_ops[0],
541 
  & sfmt_beqz_ops[0],
542 
  & sfmt_beqz_ops[0],
543 
  & sfmt_beqz_ops[0],
544 
  & sfmt_beqz_ops[0],
545 
  & sfmt_beqz_ops[0],
546 
  & sfmt_beqz_ops[0],
547 
  & sfmt_bl8_ops[0],
548 
  & sfmt_bl24_ops[0],
549 
  & sfmt_bcl8_ops[0],
550 
  & sfmt_bcl24_ops[0],
551 
  & sfmt_bc8_ops[0],
552 
  & sfmt_bc24_ops[0],
553 
  & sfmt_beq_ops[0],
554 
  & sfmt_bra8_ops[0],
555 
  & sfmt_bra24_ops[0],
556 
  & sfmt_bcl8_ops[0],
557 
  & sfmt_bcl24_ops[0],
558 
  & sfmt_cmp_ops[0],
559 
  & sfmt_cmpi_ops[0],
560 
  & sfmt_cmp_ops[0],
561 
  & sfmt_cmpi_ops[0],
562 
  & sfmt_cmp_ops[0],
563 
  & sfmt_cmpz_ops[0],
564 
  & sfmt_div_ops[0],
565 
  & sfmt_div_ops[0],
566 
  & sfmt_div_ops[0],
567 
  & sfmt_div_ops[0],
568 
  & sfmt_div_ops[0],
569 
  & sfmt_jc_ops[0],
570 
  & sfmt_jc_ops[0],
571 
  & sfmt_jl_ops[0],
572 
  & sfmt_jmp_ops[0],
573 
  & sfmt_ld_ops[0],
574 
  & sfmt_ld_d_ops[0],
575 
  & sfmt_ld_ops[0],
576 
  & sfmt_ld_d_ops[0],
577 
  & sfmt_ld_ops[0],
578 
  & sfmt_ld_d_ops[0],
579 
  & sfmt_ld_ops[0],
580 
  & sfmt_ld_d_ops[0],
581 
  & sfmt_ld_ops[0],
582 
  & sfmt_ld_d_ops[0],
583 
  & sfmt_ld_plus_ops[0],
584 
  & sfmt_ld24_ops[0],
585 
  & sfmt_ldi8_ops[0],
586 
  & sfmt_ldi16_ops[0],
587 
  & sfmt_lock_ops[0],
588 
  & sfmt_machi_ops[0],
589 
  & sfmt_machi_a_ops[0],
590 
  & sfmt_machi_ops[0],
591 
  & sfmt_machi_a_ops[0],
592 
  & sfmt_machi_ops[0],
593 
  & sfmt_machi_a_ops[0],
594 
  & sfmt_machi_ops[0],
595 
  & sfmt_machi_a_ops[0],
596 
  & sfmt_add_ops[0],
597 
  & sfmt_mulhi_ops[0],
598 
  & sfmt_mulhi_a_ops[0],
599 
  & sfmt_mulhi_ops[0],
600 
  & sfmt_mulhi_a_ops[0],
601 
  & sfmt_mulhi_ops[0],
602 
  & sfmt_mulhi_a_ops[0],
603 
  & sfmt_mulhi_ops[0],
604 
  & sfmt_mulhi_a_ops[0],
605 
  & sfmt_mv_ops[0],
606 
  & sfmt_mvfachi_ops[0],
607 
  & sfmt_mvfachi_a_ops[0],
608 
  & sfmt_mvfachi_ops[0],
609 
  & sfmt_mvfachi_a_ops[0],
610 
  & sfmt_mvfachi_ops[0],
611 
  & sfmt_mvfachi_a_ops[0],
612 
  & sfmt_mvfc_ops[0],
613 
  & sfmt_mvtachi_ops[0],
614 
  & sfmt_mvtachi_a_ops[0],
615 
  & sfmt_mvtachi_ops[0],
616 
  & sfmt_mvtachi_a_ops[0],
617 
  & sfmt_mvtc_ops[0],
618 
  & sfmt_mv_ops[0],
619 
  & sfmt_nop_ops[0],
620 
  & sfmt_mv_ops[0],
621 
  & sfmt_rac_ops[0],
622 
  & sfmt_rac_dsi_ops[0],
623 
  & sfmt_rac_ops[0],
624 
  & sfmt_rac_dsi_ops[0],
625 
  & sfmt_rte_ops[0],
626 
  & sfmt_seth_ops[0],
627 
  & sfmt_add_ops[0],
628 
  & sfmt_sll3_ops[0],
629 
  & sfmt_slli_ops[0],
630 
  & sfmt_add_ops[0],
631 
  & sfmt_sll3_ops[0],
632 
  & sfmt_slli_ops[0],
633 
  & sfmt_add_ops[0],
634 
  & sfmt_sll3_ops[0],
635 
  & sfmt_slli_ops[0],
636 
  & sfmt_st_ops[0],
637 
  & sfmt_st_d_ops[0],
638 
  & sfmt_stb_ops[0],
639 
  & sfmt_stb_d_ops[0],
640 
  & sfmt_sth_ops[0],
641 
  & sfmt_sth_d_ops[0],
642 
  & sfmt_st_plus_ops[0],
643 
  & sfmt_st_plus_ops[0],
644 
  & sfmt_add_ops[0],
645 
  & sfmt_addv_ops[0],
646 
  & sfmt_addx_ops[0],
647 
  & sfmt_trap_ops[0],
648 
  & sfmt_unlock_ops[0],
649 
  & sfmt_satb_ops[0],
650 
  & sfmt_satb_ops[0],
651 
  & sfmt_sat_ops[0],
652 
  & sfmt_cmpz_ops[0],
653 
  & sfmt_sadd_ops[0],
654 
  & sfmt_macwu1_ops[0],
655 
  & sfmt_machi_ops[0],
656 
  & sfmt_mulwu1_ops[0],
657 
  & sfmt_macwu1_ops[0],
658 
  & sfmt_sc_ops[0],
659 
  & sfmt_sc_ops[0],
660 
};
661 
 
662 
/* Function to call before using the operand instance table.  */
663 
 
664 
void
665 
m32r_cgen_init_opinst_table (cd)
666 
     CGEN_CPU_DESC cd;
667 
{
668 
  int i;
669 
  const CGEN_OPINST **oi = & m32r_cgen_opinst_table[0];
670 
  CGEN_INSN *insns = (CGEN_INSN *) cd->insn_table.init_entries;
671 
  for (i = 0; i < MAX_INSNS; ++i)
672 
    insns[i].opinst = oi[i];
673 
}

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