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/* @(#)pceb.h 5.18 93/07/30 16:40:12, Srini, AMD */
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/******************************************************************************
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* Copyright 1991 Advanced Micro Devices, Inc.
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*
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* This software is the property of Advanced Micro Devices, Inc (AMD) which
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* specifically grants the user the right to modify, use and distribute this
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* software provided this notice is not removed or altered. All other rights
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* are reserved by AMD.
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*
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* AMD MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS
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* SOFTWARE. IN NO EVENT SHALL AMD BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL
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* DAMAGES IN CONNECTION WITH OR ARISING FROM THE FURNISHING, PERFORMANCE, OR
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* USE OF THIS SOFTWARE.
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*
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* So that all may benefit from your experience, please report any problems
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* or suggestions about this software to the 29K Technical Support Center at
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* 800-29-29-AMD (800-292-9263) in the USA, or 0800-89-1131 in the UK, or
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* 0031-11-1129 in Japan, toll free. The direct dial number is 512-462-4118.
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*
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* Advanced Micro Devices, Inc.
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* 29K Support Products
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* Mail Stop 573
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* 5900 E. Ben White Blvd.
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* Austin, TX 78741
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* 800-292-9263
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*****************************************************************************
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* Engineer: Srini Subramanian.
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*****************************************************************************
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** This file defines values used in accessing the PCEB board.
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*****************************************************************************
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*/
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/*
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** PCEB register addresses
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*/
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#define PCEB_PC229K_OFFSET 32
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#define PCEB_PC29K2PC_OFFSET 34
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#define PCEB_PCCNF_OFFSET 36
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/*
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** PC229K register bit definitions.
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*/
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#define PCEB_P_REQ 0x80 /* Request bit from PC to 29k */
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#define PCEB_S_ENA 0x40 /* Enable interrupts to PC */
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#define PCEB_LB_END 0x20 /* Set for Big Endian access to 29k */
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#define PCEB_S_RESET 0x10 /* Reset the 29k processor */
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#define PCEB_S_WARN 0x08 /* Assert WARN to the 29k */
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#define PCEB_WINENA 0x04 /* Enable PC memory window */
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#define PCEB_S_CTL1 0x02 /* Processor CTRL1 input */
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#define PCEB_S_CTL0 0x01 /* Processor CTRL0 input */
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#define PCEB_S_HALT PCEB_S_CTL1
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#define PCEB_S_NORMAL (PCEB_S_CTL1 | PCEB_S_CTL0)
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/*
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** 29K2PC register bit definitions.
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*/
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#define PCEB_S_REQ 0x80 /* Request bit from 29k to PC */
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#define PCEB_P_ENA 0x40 /* Enable interrupts to 29k */
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#define PCEB_S_STAT2 0x04 /* STAT2 signal from 29k processor */
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#define PCEB_S_STAT1 0x02 /* STAT1 signal from 29k processor */
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#define PCEB_S_STAT0 0x01 /* STAT0 signal from 29k processor */
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/*
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** Shared memory definitions
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*/
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/*
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** The "anchors" defined below represent addresses in the Am29000
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** data memory space. At these addresses are pointers to shared
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** memory buffers.
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*/
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#define PCEB_RECV_BUF_PTR 0x0400 /* Host receive buffer pointer */
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#define PCEB_SEND_BUF 0x0404 /* Host send buffer */
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